0c2be2b94a2955b329be510a605a4db4e203289c
The file is empty.
Description
Digital Electronic System Design Laboratory
https://github.com/Cd16d/DESD
301 MiB
Languages
VHDL
86%
Tcl
9%
Python
2.7%
Verilog
2.2%
Makefile
0.1%