29 lines
469 B
VHDL
29 lines
469 B
VHDL
library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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entity led_blinker is
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generic (
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CLK_PERIOD_NS: POSITIVE :=10;
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BLINK_PERIOD_MS : POSITIVE :=1000;
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N_BLINKS : POSITIVE := 4
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);
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port (
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clk : in std_logic;
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aresetn : in std_logic;
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start_blink : in std_logic;
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led: out std_logic
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);
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end entity led_blinker;
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architecture rtl of led_blinker is
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begin
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end architecture;
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