163 lines
4.7 KiB
VHDL
163 lines
4.7 KiB
VHDL
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-- Company:
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-- Engineer:
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--
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-- Create Date: 04/17/2025
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-- Design Name:
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-- Module Name: tb_bram_writer - sim
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-- Project Name:
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-- Target Devices:
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-- Tool Versions:
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-- Description: Testbench for bram_writer, rewritten in the style of tb_packetizer.vhd
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--
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-- Dependencies:
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--
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-- Revision:
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-- Revision 0.01 - File Created
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-- Additional Comments:
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--
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----------------------------------------------------------------------------------
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LIBRARY ieee;
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USE ieee.std_logic_1164.ALL;
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USE ieee.numeric_std.ALL;
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ENTITY tb_bram_writer IS
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END tb_bram_writer;
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ARCHITECTURE sim OF tb_bram_writer IS
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-- Testbench constants
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CONSTANT ADDR_WIDTH : POSITIVE := 4;
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CONSTANT IMG_SIZE : POSITIVE := 4; -- Increased size for more memory
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-- Component declaration for bram_writer
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COMPONENT bram_writer IS
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GENERIC (
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ADDR_WIDTH : POSITIVE;
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IMG_SIZE : POSITIVE
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);
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PORT (
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clk : IN STD_LOGIC;
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aresetn : IN STD_LOGIC;
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s_axis_tdata : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
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s_axis_tvalid : IN STD_LOGIC;
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s_axis_tready : OUT STD_LOGIC;
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s_axis_tlast : IN STD_LOGIC;
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conv_addr : IN STD_LOGIC_VECTOR(ADDR_WIDTH-1 DOWNTO 0);
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conv_data : OUT STD_LOGIC_VECTOR(6 DOWNTO 0);
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start_conv : OUT STD_LOGIC;
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done_conv : IN STD_LOGIC;
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write_ok : OUT STD_LOGIC;
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overflow : OUT STD_LOGIC;
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underflow : OUT STD_LOGIC
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);
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END COMPONENT;
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-- Signals for DUT
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SIGNAL clk : STD_LOGIC := '0';
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SIGNAL aresetn : STD_LOGIC := '0';
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SIGNAL s_axis_tdata : STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');
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SIGNAL s_axis_tvalid : STD_LOGIC := '0';
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SIGNAL s_axis_tready : STD_LOGIC;
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SIGNAL s_axis_tlast : STD_LOGIC := '0';
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SIGNAL conv_addr : STD_LOGIC_VECTOR(ADDR_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
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SIGNAL conv_data : STD_LOGIC_VECTOR(6 DOWNTO 0);
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SIGNAL start_conv : STD_LOGIC;
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SIGNAL done_conv : STD_LOGIC := '0';
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SIGNAL write_ok : STD_LOGIC;
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SIGNAL overflow : STD_LOGIC;
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SIGNAL underflow : STD_LOGIC;
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-- Stimulus memory for input data
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TYPE mem_type IS ARRAY(0 TO (IMG_SIZE*IMG_SIZE)-1) OF STD_LOGIC_VECTOR(7 DOWNTO 0);
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SIGNAL mem : mem_type := (
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0 => x"3A",
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1 => x"7F",
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2 => x"12",
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3 => x"9C",
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4 => x"55",
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5 => x"2B",
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6 => x"81",
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7 => x"04",
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8 => x"6E",
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9 => x"F2",
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10 => x"1D",
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11 => x"C7",
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12 => x"99",
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13 => x"0A",
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14 => x"B3",
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15 => x"5D"
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);
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BEGIN
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-- Clock generation
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clk <= NOT clk AFTER 5 ns;
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-- DUT instantiation
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uut: bram_writer
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GENERIC MAP (
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ADDR_WIDTH => ADDR_WIDTH,
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IMG_SIZE => IMG_SIZE
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)
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PORT MAP (
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clk => clk,
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aresetn => aresetn,
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s_axis_tdata => s_axis_tdata,
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s_axis_tvalid => s_axis_tvalid,
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s_axis_tready => s_axis_tready,
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s_axis_tlast => s_axis_tlast,
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conv_addr => conv_addr,
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conv_data => conv_data,
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start_conv => start_conv,
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done_conv => done_conv,
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write_ok => write_ok,
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overflow => overflow,
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underflow => underflow
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);
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-- Stimulus process
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stimulus : PROCESS
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BEGIN
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-- Reset
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aresetn <= '0';
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WAIT FOR 20 ns;
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aresetn <= '1';
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WAIT UNTIL rising_edge(clk);
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-- Send IMG_SIZE*IMG_SIZE data words
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FOR i IN 0 TO IMG_SIZE*IMG_SIZE-1 LOOP
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s_axis_tdata <= mem(i);
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s_axis_tvalid <= '1';
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IF i = IMG_SIZE*IMG_SIZE-1 THEN
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s_axis_tlast <= '1';
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ELSE
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s_axis_tlast <= '0';
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END IF;
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-- Wait for handshake
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WAIT UNTIL s_axis_tvalid = '1' AND s_axis_tready = '1' AND rising_edge(clk);
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s_axis_tvalid <= '0';
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END LOOP;
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s_axis_tlast <= '0';
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-- Wait for write_ok and start_conv
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WAIT UNTIL write_ok = '1';
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WAIT UNTIL rising_edge(clk);
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-- Read out data using conv_addr
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FOR i IN 0 TO IMG_SIZE*IMG_SIZE-1 LOOP
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conv_addr <= std_logic_vector(to_unsigned(i, ADDR_WIDTH));
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WAIT UNTIL rising_edge(clk);
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END LOOP;
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-- Simulate convolution done
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done_conv <= '1';
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WAIT UNTIL rising_edge(clk);
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done_conv <= '0';
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-- Wait and finish
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WAIT;
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END PROCESS;
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END sim; |