57 lines
1.3 KiB
VHDL
57 lines
1.3 KiB
VHDL
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-- Company:
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-- Engineer:
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--
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-- Create Date: 03.03.2025 14:49:43
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-- Design Name:
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-- Module Name: ShiftRegister_v0 - Behavioral
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-- Project Name:
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-- Target Devices:
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-- Tool Versions:
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-- Description:
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--
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-- Dependencies:
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--
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-- Revision:
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-- Revision 0.01 - File Created
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-- Additional Comments:
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--
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----------------------------------------------------------------------------------
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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-- Uncomment the following library declaration if using
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-- arithmetic functions with Signed or Unsigned values
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--use IEEE.NUMERIC_STD.ALL;
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-- Uncomment the following library declaration if instantiating
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-- any Xilinx leaf cells in this code.
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--library UNISIM;
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--use UNISIM.VComponents.all;
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entity ShiftRegister_v0 is
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Port ( reset : in STD_LOGIC;
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clk : in STD_LOGIC;
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din : in STD_LOGIC;
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dout : out STD_LOGIC);
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end ShiftRegister_v0;
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architecture Behavioral of ShiftRegister_v0 is
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signal sr : std_logic := '0';
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begin
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process(clk, reset)
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begin
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if reset = '1' then
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sr <= '0';
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elsif rising_edge(clk) then
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sr <= din;
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end if;
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end process;
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dout <= sr;
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end Behavioral;
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