Update .gitignore and enhance README.md; add new VHDL files for KittCarPWM, ShiftRegisters, and PulseWidthModulator
This commit is contained in:
PickleRick committed
1 parent
c29b83ba63
commit
163ad448f8
23 files changed
+669
-279
No files matched your search
@@ -50,6 +50,7 @@
|
||||
*.sim/
|
||||
*.cache/
|
||||
*.hw/
|
||||
*.srcs/
|
||||
.hwdbg/
|
||||
*.ip_user_files/
|
||||
.webtalk/
|
||||
|
||||
-56
@@ -1,56 +0,0 @@
|
||||
----------------------------------------------------------------------------------
|
||||
-- Company:
|
||||
-- Engineer:
|
||||
--
|
||||
-- Create Date: 03.03.2025 14:21:16
|
||||
-- Design Name:
|
||||
-- Module Name: shift_register_v0 - Behavioral
|
||||
-- Project Name:
|
||||
-- Target Devices:
|
||||
-- Tool Versions:
|
||||
-- Description:
|
||||
--
|
||||
-- Dependencies:
|
||||
--
|
||||
-- Revision:
|
||||
-- Revision 0.01 - File Created
|
||||
-- Additional Comments:
|
||||
--
|
||||
----------------------------------------------------------------------------------
|
||||
|
||||
|
||||
library IEEE;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
|
||||
-- Uncomment the following library declaration if using
|
||||
-- arithmetic functions with Signed or Unsigned values
|
||||
--use IEEE.NUMERIC_STD.ALL;
|
||||
|
||||
-- Uncomment the following library declaration if instantiating
|
||||
-- any Xilinx leaf cells in this code.
|
||||
--library UNISIM;
|
||||
--use UNISIM.VComponents.all;
|
||||
|
||||
entity shift_register_v0 is
|
||||
Port ( reset : in STD_LOGIC;
|
||||
clk : in STD_LOGIC;
|
||||
din : in STD_LOGIC;
|
||||
dout : out STD_LOGIC);
|
||||
end shift_register_v0;
|
||||
|
||||
architecture Behavioral of shift_register_v0 is
|
||||
signal sr : std_logic := '0';
|
||||
begin
|
||||
|
||||
process(clk, reset)
|
||||
begin
|
||||
if reset = '1' then
|
||||
sr <= '0';
|
||||
elsif rising_edge(clk) then
|
||||
sr <= din;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
dout <= sr;
|
||||
|
||||
end Behavioral;
|
||||
File renamed without changes.
File renamed without changes.
File renamed without changes.
File renamed without changes.
File renamed without changes.
File renamed without changes.
File renamed without changes.
File renamed without changes.
+9
-12
@@ -3,7 +3,7 @@
|
||||
<!-- -->
|
||||
<!-- Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. -->
|
||||
|
||||
<Project Version="7" Minor="54" Path="C:/DESD/LAB0/lab0_pulse_width_modulator/lab0_pulse_width_modulator.xpr">
|
||||
<Project Version="7" Minor="54" Path="C:/DESD/LAB0/vivado/lab0_pulse_width_modulator/lab0_pulse_width_modulator.xpr">
|
||||
<DefaultLaunch Dir="$PRUNDIR"/>
|
||||
<Configuration>
|
||||
<Option Name="Id" Val="5e30cf21c5094cb99e69e33f328f026e"/>
|
||||
@@ -33,7 +33,7 @@
|
||||
<Option Name="SimulatorGccInstallDirActiveHdl" Val=""/>
|
||||
<Option Name="TargetLanguage" Val="VHDL"/>
|
||||
<Option Name="BoardPart" Val="digilentinc.com:basys3:part0:1.1"/>
|
||||
<Option Name="BoardPartRepoPaths" Val="$PPRDIR/../../../Users/david/AppData/Roaming/Xilinx/Vivado/2020.2/xhub/board_store/xilinx_board_store"/>
|
||||
<Option Name="BoardPartRepoPaths" Val="$PPRDIR/../../../../Users/david/AppData/Roaming/Xilinx/Vivado/2020.2/xhub/board_store/xilinx_board_store"/>
|
||||
<Option Name="ActiveSimSet" Val="sim_1"/>
|
||||
<Option Name="DefaultLib" Val="xil_defaultlib"/>
|
||||
<Option Name="ProjectType" Val="Default"/>
|
||||
@@ -76,7 +76,7 @@
|
||||
<FileSets Version="1" Minor="31">
|
||||
<FileSet Name="sources_1" Type="DesignSrcs" RelSrcDir="$PSRCDIR/sources_1" RelGenDir="$PGENDIR/sources_1">
|
||||
<Filter Type="Srcs"/>
|
||||
<File Path="$PSRCDIR/sources_1/new/lab0_pulse_width_modulator.vhd">
|
||||
<File Path="$PPRDIR/../../src/PulseWidthModulator.vhd">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
@@ -95,7 +95,8 @@
|
||||
</Config>
|
||||
</FileSet>
|
||||
<FileSet Name="sim_1" Type="SimulationSrcs" RelSrcDir="$PSRCDIR/sim_1" RelGenDir="$PGENDIR/sim_1">
|
||||
<File Path="$PPRDIR/../../../Users/david/Downloads/tb_PulseWidthModulator.vhd">
|
||||
<Filter Type="Srcs"/>
|
||||
<File Path="$PPRDIR/../../sim/tb_PulseWidthModulator.vhd">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
@@ -142,22 +143,18 @@
|
||||
</Simulator>
|
||||
</Simulators>
|
||||
<Runs Version="1" Minor="15">
|
||||
<Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7a35tcpg236-1" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" IncludeInArchive="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/synth_1">
|
||||
<Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7a35tcpg236-1" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" IncludeInArchive="true" AutoIncrementalDir="$PPRDIR/../../lab0_pulse_width_modulator/lab0_pulse_width_modulator.srcs/utils_1/imports/synth_1">
|
||||
<Strategy Version="1" Minor="2">
|
||||
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2020">
|
||||
<Desc>Vivado Synthesis Defaults</Desc>
|
||||
</StratHandle>
|
||||
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2020"/>
|
||||
<Step Id="synth_design"/>
|
||||
</Strategy>
|
||||
<ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2020"/>
|
||||
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
|
||||
<RQSFiles/>
|
||||
</Run>
|
||||
<Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7a35tcpg236-1" ConstrsSet="constrs_1" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" SynthRun="synth_1" IncludeInArchive="true" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/impl_1">
|
||||
<Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7a35tcpg236-1" ConstrsSet="constrs_1" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" SynthRun="synth_1" IncludeInArchive="true" GenFullBitstream="true" AutoIncrementalDir="$PPRDIR/../../lab0_pulse_width_modulator/lab0_pulse_width_modulator.srcs/utils_1/imports/impl_1">
|
||||
<Strategy Version="1" Minor="2">
|
||||
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2020">
|
||||
<Desc>Default settings for Implementation.</Desc>
|
||||
</StratHandle>
|
||||
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2020"/>
|
||||
<Step Id="init_design"/>
|
||||
<Step Id="opt_design"/>
|
||||
<Step Id="power_opt_design"/>
|
||||
+5
-5
@@ -3,7 +3,7 @@
|
||||
<!-- -->
|
||||
<!-- Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. -->
|
||||
|
||||
<Project Version="7" Minor="54" Path="C:/DESD/LAB0/lab_0_shift_register/lab_0_shift_register.xpr">
|
||||
<Project Version="7" Minor="54" Path="C:/DESD/LAB0/vivado/lab0_shift_register_v0/lab0_shift_register_v0.xpr">
|
||||
<DefaultLaunch Dir="$PRUNDIR"/>
|
||||
<Configuration>
|
||||
<Option Name="Id" Val="79acb559a79942b0a66a9383c435cb5b"/>
|
||||
@@ -74,7 +74,7 @@
|
||||
<FileSets Version="1" Minor="31">
|
||||
<FileSet Name="sources_1" Type="DesignSrcs" RelSrcDir="$PSRCDIR/sources_1" RelGenDir="$PGENDIR/sources_1">
|
||||
<Filter Type="Srcs"/>
|
||||
<File Path="$PSRCDIR/sources_1/new/ShiftRegister_v0.vhd">
|
||||
<File Path="$PPRDIR/../../src/ShiftRegister_v0.vhd">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
@@ -94,7 +94,7 @@
|
||||
</FileSet>
|
||||
<FileSet Name="sim_1" Type="SimulationSrcs" RelSrcDir="$PSRCDIR/sim_1" RelGenDir="$PGENDIR/sim_1">
|
||||
<Filter Type="Srcs"/>
|
||||
<File Path="$PPRDIR/../../../Users/david/Downloads/tb_ShiftRegister/tb_ShiftRegister_v0.vhd">
|
||||
<File Path="$PPRDIR/../../sim/tb_ShiftRegister_v0.vhd">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
@@ -141,7 +141,7 @@
|
||||
</Simulator>
|
||||
</Simulators>
|
||||
<Runs Version="1" Minor="15">
|
||||
<Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7a35tcpg236-1" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" IncludeInArchive="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/synth_1">
|
||||
<Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7a35tcpg236-1" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" IncludeInArchive="true" AutoIncrementalDir="$PPRDIR/../../lab_0_shift_register/lab_0_shift_register.srcs/utils_1/imports/synth_1">
|
||||
<Strategy Version="1" Minor="2">
|
||||
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2020"/>
|
||||
<Step Id="synth_design"/>
|
||||
@@ -150,7 +150,7 @@
|
||||
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
|
||||
<RQSFiles/>
|
||||
</Run>
|
||||
<Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7a35tcpg236-1" ConstrsSet="constrs_1" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" SynthRun="synth_1" IncludeInArchive="true" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/impl_1">
|
||||
<Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7a35tcpg236-1" ConstrsSet="constrs_1" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" SynthRun="synth_1" IncludeInArchive="true" GenFullBitstream="true" AutoIncrementalDir="$PPRDIR/../../lab_0_shift_register/lab_0_shift_register.srcs/utils_1/imports/impl_1">
|
||||
<Strategy Version="1" Minor="2">
|
||||
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2020"/>
|
||||
<Step Id="init_design"/>
|
||||
+7
-7
@@ -3,7 +3,7 @@
|
||||
<!-- -->
|
||||
<!-- Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. -->
|
||||
|
||||
<Project Version="7" Minor="54" Path="C:/DESD/LAB0/lab0_shift_register_v1/lab0_shift_register_v1.xpr">
|
||||
<Project Version="7" Minor="54" Path="C:/DESD/LAB0/vivado/lab0_shift_register_v1/lab0_shift_register_v1.xpr">
|
||||
<DefaultLaunch Dir="$PRUNDIR"/>
|
||||
<Configuration>
|
||||
<Option Name="Id" Val="b6c8e7e1e5944b109219f67e64ef5d5f"/>
|
||||
@@ -33,7 +33,7 @@
|
||||
<Option Name="SimulatorGccInstallDirActiveHdl" Val=""/>
|
||||
<Option Name="TargetLanguage" Val="VHDL"/>
|
||||
<Option Name="BoardPart" Val="digilentinc.com:basys3:part0:1.1"/>
|
||||
<Option Name="BoardPartRepoPaths" Val="$PPRDIR/../../../Users/david/AppData/Roaming/Xilinx/Vivado/2020.2/xhub/board_store/xilinx_board_store"/>
|
||||
<Option Name="BoardPartRepoPaths" Val="$PPRDIR/../../../../Users/david/AppData/Roaming/Xilinx/Vivado/2020.2/xhub/board_store/xilinx_board_store"/>
|
||||
<Option Name="ActiveSimSet" Val="sim_1"/>
|
||||
<Option Name="DefaultLib" Val="xil_defaultlib"/>
|
||||
<Option Name="ProjectType" Val="Default"/>
|
||||
@@ -47,7 +47,7 @@
|
||||
<Option Name="IPStaticSourceDir" Val="$PIPUSERFILESDIR/ipstatic"/>
|
||||
<Option Name="EnableBDX" Val="FALSE"/>
|
||||
<Option Name="DSABoardId" Val="basys3"/>
|
||||
<Option Name="WTXSimLaunchSim" Val="9"/>
|
||||
<Option Name="WTXSimLaunchSim" Val="10"/>
|
||||
<Option Name="WTModelSimLaunchSim" Val="0"/>
|
||||
<Option Name="WTQuestaLaunchSim" Val="0"/>
|
||||
<Option Name="WTIesLaunchSim" Val="0"/>
|
||||
@@ -76,7 +76,7 @@
|
||||
<FileSets Version="1" Minor="31">
|
||||
<FileSet Name="sources_1" Type="DesignSrcs" RelSrcDir="$PSRCDIR/sources_1" RelGenDir="$PGENDIR/sources_1">
|
||||
<Filter Type="Srcs"/>
|
||||
<File Path="$PSRCDIR/sources_1/new/ShiftRegister_v1.vhd">
|
||||
<File Path="$PPRDIR/../../src/ShiftRegister_v1.vhd">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
@@ -96,7 +96,7 @@
|
||||
</FileSet>
|
||||
<FileSet Name="sim_1" Type="SimulationSrcs" RelSrcDir="$PSRCDIR/sim_1" RelGenDir="$PGENDIR/sim_1">
|
||||
<Filter Type="Srcs"/>
|
||||
<File Path="$PPRDIR/../../../Users/david/Downloads/tb_ShiftRegister/tb_ShiftRegister_v1.vhd">
|
||||
<File Path="$PPRDIR/../../sim/tb_ShiftRegister_v1.vhd">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
@@ -143,7 +143,7 @@
|
||||
</Simulator>
|
||||
</Simulators>
|
||||
<Runs Version="1" Minor="15">
|
||||
<Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7a35tcpg236-1" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" IncludeInArchive="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/synth_1">
|
||||
<Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7a35tcpg236-1" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" IncludeInArchive="true" AutoIncrementalDir="$PPRDIR/../../lab0_shift_register_v1/lab0_shift_register_v1.srcs/utils_1/imports/synth_1">
|
||||
<Strategy Version="1" Minor="2">
|
||||
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2020"/>
|
||||
<Step Id="synth_design"/>
|
||||
@@ -152,7 +152,7 @@
|
||||
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
|
||||
<RQSFiles/>
|
||||
</Run>
|
||||
<Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7a35tcpg236-1" ConstrsSet="constrs_1" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" SynthRun="synth_1" IncludeInArchive="true" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/impl_1">
|
||||
<Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7a35tcpg236-1" ConstrsSet="constrs_1" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" SynthRun="synth_1" IncludeInArchive="true" GenFullBitstream="true" AutoIncrementalDir="$PPRDIR/../../lab0_shift_register_v1/lab0_shift_register_v1.srcs/utils_1/imports/impl_1">
|
||||
<Strategy Version="1" Minor="2">
|
||||
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2020"/>
|
||||
<Step Id="init_design"/>
|
||||
+10
-13
@@ -3,7 +3,7 @@
|
||||
<!-- -->
|
||||
<!-- Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. -->
|
||||
|
||||
<Project Version="7" Minor="54" Path="C:/DESD/LAB0/lab0_shift_register_v2/lab0_shift_register_v2.xpr">
|
||||
<Project Version="7" Minor="54" Path="C:/DESD/LAB0/vivado/lab0_shift_register_v2/lab0_shift_register_v2.xpr">
|
||||
<DefaultLaunch Dir="$PRUNDIR"/>
|
||||
<Configuration>
|
||||
<Option Name="Id" Val="9314b9120ade4657994d00a93c65e94d"/>
|
||||
@@ -33,7 +33,7 @@
|
||||
<Option Name="SimulatorGccInstallDirActiveHdl" Val=""/>
|
||||
<Option Name="TargetLanguage" Val="VHDL"/>
|
||||
<Option Name="BoardPart" Val="digilentinc.com:basys3:part0:1.1"/>
|
||||
<Option Name="BoardPartRepoPaths" Val="$PPRDIR/../../../Users/david/AppData/Roaming/Xilinx/Vivado/2020.2/xhub/board_store/xilinx_board_store"/>
|
||||
<Option Name="BoardPartRepoPaths" Val="$PPRDIR/../../../../Users/david/AppData/Roaming/Xilinx/Vivado/2020.2/xhub/board_store/xilinx_board_store"/>
|
||||
<Option Name="ActiveSimSet" Val="sim_1"/>
|
||||
<Option Name="DefaultLib" Val="xil_defaultlib"/>
|
||||
<Option Name="ProjectType" Val="Default"/>
|
||||
@@ -47,7 +47,7 @@
|
||||
<Option Name="IPStaticSourceDir" Val="$PIPUSERFILESDIR/ipstatic"/>
|
||||
<Option Name="EnableBDX" Val="FALSE"/>
|
||||
<Option Name="DSABoardId" Val="basys3"/>
|
||||
<Option Name="WTXSimLaunchSim" Val="3"/>
|
||||
<Option Name="WTXSimLaunchSim" Val="4"/>
|
||||
<Option Name="WTModelSimLaunchSim" Val="0"/>
|
||||
<Option Name="WTQuestaLaunchSim" Val="0"/>
|
||||
<Option Name="WTIesLaunchSim" Val="0"/>
|
||||
@@ -76,7 +76,7 @@
|
||||
<FileSets Version="1" Minor="31">
|
||||
<FileSet Name="sources_1" Type="DesignSrcs" RelSrcDir="$PSRCDIR/sources_1" RelGenDir="$PGENDIR/sources_1">
|
||||
<Filter Type="Srcs"/>
|
||||
<File Path="$PSRCDIR/sources_1/new/ShiftRegister_v2.vhd">
|
||||
<File Path="$PPRDIR/../../src/ShiftRegister_v2.vhd">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
@@ -95,7 +95,8 @@
|
||||
</Config>
|
||||
</FileSet>
|
||||
<FileSet Name="sim_1" Type="SimulationSrcs" RelSrcDir="$PSRCDIR/sim_1" RelGenDir="$PGENDIR/sim_1">
|
||||
<File Path="$PPRDIR/../../../Users/david/Downloads/tb_ShiftRegister/tb_ShiftRegister_v2.vhd">
|
||||
<Filter Type="Srcs"/>
|
||||
<File Path="$PPRDIR/../../sim/tb_ShiftRegister_v2.vhd">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
@@ -142,22 +143,18 @@
|
||||
</Simulator>
|
||||
</Simulators>
|
||||
<Runs Version="1" Minor="15">
|
||||
<Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7a35tcpg236-1" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" IncludeInArchive="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/synth_1">
|
||||
<Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7a35tcpg236-1" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" IncludeInArchive="true" AutoIncrementalDir="$PPRDIR/../../lab0_shift_register_v2/lab0_shift_register_v2.srcs/utils_1/imports/synth_1">
|
||||
<Strategy Version="1" Minor="2">
|
||||
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2020">
|
||||
<Desc>Vivado Synthesis Defaults</Desc>
|
||||
</StratHandle>
|
||||
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2020"/>
|
||||
<Step Id="synth_design"/>
|
||||
</Strategy>
|
||||
<ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2020"/>
|
||||
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
|
||||
<RQSFiles/>
|
||||
</Run>
|
||||
<Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7a35tcpg236-1" ConstrsSet="constrs_1" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" SynthRun="synth_1" IncludeInArchive="true" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/impl_1">
|
||||
<Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7a35tcpg236-1" ConstrsSet="constrs_1" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" SynthRun="synth_1" IncludeInArchive="true" GenFullBitstream="true" AutoIncrementalDir="$PPRDIR/../../lab0_shift_register_v2/lab0_shift_register_v2.srcs/utils_1/imports/impl_1">
|
||||
<Strategy Version="1" Minor="2">
|
||||
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2020">
|
||||
<Desc>Default settings for Implementation.</Desc>
|
||||
</StratHandle>
|
||||
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2020"/>
|
||||
<Step Id="init_design"/>
|
||||
<Step Id="opt_design"/>
|
||||
<Step Id="power_opt_design"/>
|
||||
File renamed without changes.
@@ -1,84 +0,0 @@
|
||||
-- File: KittCar_v0.vhd
|
||||
-- Description: This file implements the KittCar entity
|
||||
-- Known problem: The counter is not working properly
|
||||
|
||||
---------- DEFAULT LIBRARY ---------
|
||||
LIBRARY IEEE;
|
||||
USE IEEE.STD_LOGIC_1164.ALL;
|
||||
USE IEEE.NUMERIC_STD.ALL;
|
||||
------------------------------------
|
||||
|
||||
ENTITY KittCar IS
|
||||
GENERIC (
|
||||
|
||||
CLK_PERIOD_NS : POSITIVE RANGE 1 TO 100 := 10; -- clk period in nanoseconds
|
||||
MIN_KITT_CAR_STEP_MS : POSITIVE RANGE 1 TO 2000 := 1; -- Minimum step period in milliseconds (i.e., value in milliseconds of Delta_t)
|
||||
|
||||
NUM_OF_SWS : INTEGER RANGE 1 TO 16 := 16; -- Number of input switches
|
||||
NUM_OF_LEDS : INTEGER RANGE 1 TO 16 := 16 -- Number of output LEDs
|
||||
|
||||
);
|
||||
PORT (
|
||||
|
||||
------- Reset/Clock --------
|
||||
reset : IN STD_LOGIC;
|
||||
clk : IN STD_LOGIC;
|
||||
----------------------------
|
||||
|
||||
-------- LEDs/SWs ----------
|
||||
sw : IN STD_LOGIC_VECTOR(NUM_OF_SWS - 1 DOWNTO 0); -- Switches avaiable on Basys3
|
||||
led : OUT STD_LOGIC_VECTOR(NUM_OF_LEDS - 1 DOWNTO 0) -- LEDs avaiable on Basys3
|
||||
----------------------------
|
||||
|
||||
);
|
||||
END KittCar;
|
||||
|
||||
ARCHITECTURE Behavioral OF KittCar IS
|
||||
SIGNAL leds_sr : STD_LOGIC_VECTOR(led'RANGE) := (OTHERS => '0');
|
||||
SIGNAL counter : UNSIGNED(47 DOWNTO 0) := (OTHERS => '0');
|
||||
SIGNAL n_period : POSITIVE RANGE 1 TO 2 ** NUM_OF_SWS := 1;
|
||||
BEGIN
|
||||
|
||||
PROCESS (clk, reset)
|
||||
VARIABLE up : STD_LOGIC := '1';
|
||||
BEGIN
|
||||
-- up/down logic
|
||||
IF leds_sr(NUM_OF_LEDS - 1) = '1' THEN
|
||||
up := '0';
|
||||
ELSIF leds_sr(0) = '1' THEN
|
||||
up := '1';
|
||||
END IF;
|
||||
|
||||
-- Reset the leds
|
||||
IF unsigned(leds_sr) = 0 THEN
|
||||
leds_sr <= (0 => '1', OTHERS => '0');
|
||||
END IF;
|
||||
|
||||
IF reset = '1' THEN
|
||||
leds_sr <= (OTHERS => '0');
|
||||
up := '1';
|
||||
counter <= (OTHERS => '0');
|
||||
ELSIF rising_edge(clk) THEN
|
||||
-- Calculate the number of periods
|
||||
IF counter >= ((MIN_KITT_CAR_STEP_MS * 1000000) * n_period) THEN
|
||||
counter <= (OTHERS => '0');
|
||||
-- Shift the leds
|
||||
IF up = '1' THEN
|
||||
leds_sr <= leds_sr(NUM_OF_LEDS - 2 DOWNTO 0) & '0';
|
||||
ELSIF up = '0' THEN
|
||||
leds_sr <= '0' & leds_sr(NUM_OF_LEDS - 1 DOWNTO 1);
|
||||
END IF;
|
||||
ELSE
|
||||
counter <= counter + to_unsigned(CLK_PERIOD_NS, counter'LENGTH);
|
||||
END IF;
|
||||
END IF;
|
||||
END PROCESS;
|
||||
|
||||
PROCESS (sw)
|
||||
BEGIN
|
||||
n_period <= to_integer(unsigned(sw)) + 1;
|
||||
END PROCESS;
|
||||
|
||||
led <= leds_sr;
|
||||
|
||||
END Behavioral;
|
||||
@@ -1,94 +0,0 @@
|
||||
-- File: KittCar_v2.vhd
|
||||
-- Description: Counter prescaler & unsigned n_period
|
||||
-- Known problem: Not yet tested
|
||||
|
||||
---------- DEFAULT LIBRARY ---------
|
||||
LIBRARY IEEE;
|
||||
USE IEEE.STD_LOGIC_1164.ALL;
|
||||
USE IEEE.NUMERIC_STD.ALL;
|
||||
------------------------------------
|
||||
|
||||
ENTITY KittCar IS
|
||||
GENERIC (
|
||||
|
||||
CLK_PERIOD_NS : POSITIVE RANGE 1 TO 100 := 10; -- clk period in nanoseconds
|
||||
MIN_KITT_CAR_STEP_MS : POSITIVE RANGE 1 TO 2000 := 1; -- Minimum step period in milliseconds (i.e., value in milliseconds of Delta_t)
|
||||
|
||||
NUM_OF_SWS : INTEGER RANGE 1 TO 16 := 16; -- Number of input switches
|
||||
NUM_OF_LEDS : INTEGER RANGE 1 TO 16 := 16 -- Number of output LEDs
|
||||
|
||||
);
|
||||
PORT (
|
||||
|
||||
------- Reset/Clock --------
|
||||
reset : IN STD_LOGIC;
|
||||
clk : IN STD_LOGIC;
|
||||
----------------------------
|
||||
|
||||
-------- LEDs/SWs ----------
|
||||
sw : IN STD_LOGIC_VECTOR(NUM_OF_SWS - 1 DOWNTO 0); -- Switches avaiable on Basys3
|
||||
led : OUT STD_LOGIC_VECTOR(NUM_OF_LEDS - 1 DOWNTO 0) -- LEDs avaiable on Basys3
|
||||
----------------------------
|
||||
|
||||
);
|
||||
END KittCar;
|
||||
|
||||
ARCHITECTURE Behavioral OF KittCar IS
|
||||
SIGNAL leds_sr : STD_LOGIC_VECTOR(led'RANGE) := (OTHERS => '0');
|
||||
SIGNAL n_period : UNSIGNED(sw'RANGE) := to_unsigned(1, sw'LENGTH);
|
||||
SIGNAL up : STD_LOGIC := '1';
|
||||
BEGIN
|
||||
|
||||
-- Sincronous logic
|
||||
PROCESS (clk, reset)
|
||||
VARIABLE counter_ns : UNSIGNED(19 DOWNTO 0) := (OTHERS => '0'); -- 20-bit counter for nanoseconds
|
||||
VARIABLE counter_ms : UNSIGNED(26 DOWNTO 0) := (OTHERS => '0'); -- 27-bit counter for milliseconds
|
||||
BEGIN
|
||||
IF reset = '1' THEN
|
||||
leds_sr <= (OTHERS => '0');
|
||||
counter_ns := (OTHERS => '0');
|
||||
counter_ms := (OTHERS => '0');
|
||||
ELSIF rising_edge(clk) THEN
|
||||
|
||||
-- Kitt logic
|
||||
IF unsigned(leds_sr) = 0 THEN
|
||||
leds_sr(0) <= '1';
|
||||
up <= '1';
|
||||
ELSIF leds_sr(led'HIGH) = '1' THEN
|
||||
up <= '0';
|
||||
ELSIF leds_sr(led'LOW) = '1' THEN
|
||||
up <= '1';
|
||||
END IF;
|
||||
|
||||
-- Handle counters
|
||||
counter_ns := counter_ns + to_unsigned(CLK_PERIOD_NS, counter_ns'LENGTH);
|
||||
IF counter_ns >= to_unsigned(1000000, counter_ns'LENGTH) THEN
|
||||
counter_ms := counter_ms + 1;
|
||||
counter_ns := (OTHERS => '0');
|
||||
END IF;
|
||||
|
||||
-- Calculate the number of periods
|
||||
IF counter_ms >= to_unsigned(MIN_KITT_CAR_STEP_MS, counter_ms'LENGTH) * n_period THEN
|
||||
|
||||
-- Shift the leds
|
||||
IF up = '1' THEN
|
||||
leds_sr <= leds_sr(NUM_OF_LEDS - 2 DOWNTO 0) & '0';
|
||||
ELSIF up = '0' THEN
|
||||
leds_sr <= '0' & leds_sr(NUM_OF_LEDS - 1 DOWNTO 1);
|
||||
END IF;
|
||||
|
||||
-- Reset the counter
|
||||
counter_ms := (OTHERS => '0');
|
||||
END IF;
|
||||
END IF;
|
||||
END PROCESS;
|
||||
|
||||
-- Handle the switch
|
||||
PROCESS (sw)
|
||||
BEGIN
|
||||
n_period <= unsigned(sw) + 1;
|
||||
END PROCESS;
|
||||
|
||||
led <= leds_sr;
|
||||
|
||||
END Behavioral;
|
||||
File renamed without changes.
@@ -0,0 +1,37 @@
|
||||
---------- DEFAULT LIBRARY ---------
|
||||
library IEEE;
|
||||
use IEEE.STD_LOGIC_1164.all;
|
||||
use IEEE.NUMERIC_STD.ALL;
|
||||
------------------------------------
|
||||
|
||||
entity KittCarPWM is
|
||||
Generic (
|
||||
|
||||
CLK_PERIOD_NS : POSITIVE RANGE 1 TO 100 := 10; -- clk period in nanoseconds
|
||||
MIN_KITT_CAR_STEP_MS : POSITIVE RANGE 1 TO 2000 := 1; -- Minimum step period in milliseconds (i.e., value in milliseconds of Delta_t)
|
||||
|
||||
NUM_OF_SWS : INTEGER RANGE 1 TO 16 := 16; -- Number of input switches
|
||||
NUM_OF_LEDS : INTEGER RANGE 1 TO 16 := 16; -- Number of output LEDs
|
||||
|
||||
TAIL_LENGTH : INTEGER RANGE 1 TO 16 := 4 -- Tail length
|
||||
);
|
||||
Port (
|
||||
|
||||
------- Reset/Clock --------
|
||||
reset : IN STD_LOGIC;
|
||||
clk : IN STD_LOGIC;
|
||||
----------------------------
|
||||
|
||||
-------- LEDs/SWs ----------
|
||||
sw : IN STD_LOGIC_VECTOR(NUM_OF_SWS-1 downto 0); -- Switches avaiable on Basys3
|
||||
leds : OUT STD_LOGIC_VECTOR(NUM_OF_LEDS-1 downto 0) -- LEDs avaiable on Basys3
|
||||
----------------------------
|
||||
|
||||
);
|
||||
end KittCarPWM;
|
||||
|
||||
architecture Behavioral of KittCarPWM is
|
||||
|
||||
begin
|
||||
|
||||
end Behavioral;
|
||||
@@ -3,7 +3,7 @@
|
||||
<!-- -->
|
||||
<!-- Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. -->
|
||||
|
||||
<Project Version="7" Minor="54" Path="C:/DESD/LAB1/lab1_kit_car/lab1_kit_car.xpr">
|
||||
<Project Version="7" Minor="54" Path="C:/DESD/LAB1/vivado/lab1_kit_car/lab1_kit_car.xpr">
|
||||
<DefaultLaunch Dir="$PRUNDIR"/>
|
||||
<Configuration>
|
||||
<Option Name="Id" Val="803666bc5e1744d3ae915c39740ba6f4"/>
|
||||
@@ -33,7 +33,7 @@
|
||||
<Option Name="SimulatorGccInstallDirActiveHdl" Val=""/>
|
||||
<Option Name="TargetLanguage" Val="VHDL"/>
|
||||
<Option Name="BoardPart" Val=""/>
|
||||
<Option Name="BoardPartRepoPaths" Val="$PPRDIR/../../../Users/david/AppData/Roaming/Xilinx/Vivado/2020.2/xhub/board_store/xilinx_board_store"/>
|
||||
<Option Name="BoardPartRepoPaths" Val="$PPRDIR/../../../../Users/david/AppData/Roaming/Xilinx/Vivado/2020.2/xhub/board_store/xilinx_board_store"/>
|
||||
<Option Name="ActiveSimSet" Val="sim_1"/>
|
||||
<Option Name="DefaultLib" Val="xil_defaultlib"/>
|
||||
<Option Name="ProjectType" Val="Default"/>
|
||||
@@ -75,7 +75,7 @@
|
||||
<FileSets Version="1" Minor="31">
|
||||
<FileSet Name="sources_1" Type="DesignSrcs" RelSrcDir="$PSRCDIR/sources_1" RelGenDir="$PGENDIR/sources_1">
|
||||
<Filter Type="Srcs"/>
|
||||
<File Path="$PSRCDIR/sources_1/new/KittCar_v2.vhd">
|
||||
<File Path="$PPRDIR/../../src/KittCar.vhd">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
@@ -89,7 +89,7 @@
|
||||
</FileSet>
|
||||
<FileSet Name="constrs_1" Type="Constrs" RelSrcDir="$PSRCDIR/constrs_1" RelGenDir="$PGENDIR/constrs_1">
|
||||
<Filter Type="Constrs"/>
|
||||
<File Path="$PPRDIR/../basys3_master.xdc">
|
||||
<File Path="$PPRDIR/../../cons/basys3_master.xdc">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
@@ -142,7 +142,7 @@
|
||||
</Simulator>
|
||||
</Simulators>
|
||||
<Runs Version="1" Minor="15">
|
||||
<Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7a35tcpg236-1" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" Dir="$PRUNDIR/synth_1" IncludeInArchive="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/synth_1">
|
||||
<Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7a35tcpg236-1" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" Dir="$PRUNDIR/synth_1" IncludeInArchive="true" AutoIncrementalDir="$PPRDIR/../../lab1_kit_car/lab1_kit_car.srcs/utils_1/imports/synth_1">
|
||||
<Strategy Version="1" Minor="2">
|
||||
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2020"/>
|
||||
<Step Id="synth_design"/>
|
||||
@@ -152,7 +152,7 @@
|
||||
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
|
||||
<RQSFiles/>
|
||||
</Run>
|
||||
<Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7a35tcpg236-1" ConstrsSet="constrs_1" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" Dir="$PRUNDIR/impl_1" SynthRun="synth_1" IncludeInArchive="true" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/impl_1">
|
||||
<Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7a35tcpg236-1" ConstrsSet="constrs_1" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" Dir="$PRUNDIR/impl_1" SynthRun="synth_1" IncludeInArchive="true" GenFullBitstream="true" AutoIncrementalDir="$PPRDIR/../../lab1_kit_car/lab1_kit_car.srcs/utils_1/imports/impl_1">
|
||||
<Strategy Version="1" Minor="2">
|
||||
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2020"/>
|
||||
<Step Id="init_design"/>
|
||||
@@ -0,0 +1,294 @@
|
||||
## This file is a general .xdc for the Basys3 rev B board
|
||||
## To use it in a project:
|
||||
## - uncomment the lines corresponding to used pins
|
||||
## - rename the used ports (in each line, after get_ports) according to the top level signal names in the project
|
||||
|
||||
## Clock signal
|
||||
#set_property PACKAGE_PIN W5 [get_ports clk]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports clk]
|
||||
#create_clock -add -name sys_clk_pin -period 10.00 -waveform {0 5} [get_ports clk]
|
||||
|
||||
## Switches
|
||||
#set_property PACKAGE_PIN V17 [get_ports {sw[0]}]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports {sw[0]}]
|
||||
#set_property PACKAGE_PIN V16 [get_ports {sw[1]}]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports {sw[1]}]
|
||||
#set_property PACKAGE_PIN W16 [get_ports {sw[2]}]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports {sw[2]}]
|
||||
#set_property PACKAGE_PIN W17 [get_ports {sw[3]}]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports {sw[3]}]
|
||||
#set_property PACKAGE_PIN W15 [get_ports {sw[4]}]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports {sw[4]}]
|
||||
#set_property PACKAGE_PIN V15 [get_ports {sw[5]}]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports {sw[5]}]
|
||||
#set_property PACKAGE_PIN W14 [get_ports {sw[6]}]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports {sw[6]}]
|
||||
#set_property PACKAGE_PIN W13 [get_ports {sw[7]}]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports {sw[7]}]
|
||||
#set_property PACKAGE_PIN V2 [get_ports {sw[8]}]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports {sw[8]}]
|
||||
#set_property PACKAGE_PIN T3 [get_ports {sw[9]}]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports {sw[9]}]
|
||||
#set_property PACKAGE_PIN T2 [get_ports {sw[10]}]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports {sw[10]}]
|
||||
#set_property PACKAGE_PIN R3 [get_ports {sw[11]}]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports {sw[11]}]
|
||||
#set_property PACKAGE_PIN W2 [get_ports {sw[12]}]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports {sw[12]}]
|
||||
#set_property PACKAGE_PIN U1 [get_ports {sw[13]}]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports {sw[13]}]
|
||||
#set_property PACKAGE_PIN T1 [get_ports {sw[14]}]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports {sw[14]}]
|
||||
#set_property PACKAGE_PIN R2 [get_ports {sw[15]}]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports {sw[15]}]
|
||||
|
||||
|
||||
## LEDs
|
||||
#set_property PACKAGE_PIN U16 [get_ports {led[0]}]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports {led[0]}]
|
||||
#set_property PACKAGE_PIN E19 [get_ports {led[1]}]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports {led[1]}]
|
||||
#set_property PACKAGE_PIN U19 [get_ports {led[2]}]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports {led[2]}]
|
||||
#set_property PACKAGE_PIN V19 [get_ports {led[3]}]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports {led[3]}]
|
||||
#set_property PACKAGE_PIN W18 [get_ports {led[4]}]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports {led[4]}]
|
||||
#set_property PACKAGE_PIN U15 [get_ports {led[5]}]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports {led[5]}]
|
||||
#set_property PACKAGE_PIN U14 [get_ports {led[6]}]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports {led[6]}]
|
||||
#set_property PACKAGE_PIN V14 [get_ports {led[7]}]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports {led[7]}]
|
||||
#set_property PACKAGE_PIN V13 [get_ports {led[8]}]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports {led[8]}]
|
||||
#set_property PACKAGE_PIN V3 [get_ports {led[9]}]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports {led[9]}]
|
||||
#set_property PACKAGE_PIN W3 [get_ports {led[10]}]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports {led[10]}]
|
||||
#set_property PACKAGE_PIN U3 [get_ports {led[11]}]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports {led[11]}]
|
||||
#set_property PACKAGE_PIN P3 [get_ports {led[12]}]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports {led[12]}]
|
||||
#set_property PACKAGE_PIN N3 [get_ports {led[13]}]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports {led[13]}]
|
||||
#set_property PACKAGE_PIN P1 [get_ports {led[14]}]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports {led[14]}]
|
||||
#set_property PACKAGE_PIN L1 [get_ports {led[15]}]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports {led[15]}]
|
||||
|
||||
|
||||
##7 segment display
|
||||
#set_property PACKAGE_PIN W7 [get_ports {seg[0]}]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports {seg[0]}]
|
||||
#set_property PACKAGE_PIN W6 [get_ports {seg[1]}]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports {seg[1]}]
|
||||
#set_property PACKAGE_PIN U8 [get_ports {seg[2]}]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports {seg[2]}]
|
||||
#set_property PACKAGE_PIN V8 [get_ports {seg[3]}]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports {seg[3]}]
|
||||
#set_property PACKAGE_PIN U5 [get_ports {seg[4]}]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports {seg[4]}]
|
||||
#set_property PACKAGE_PIN V5 [get_ports {seg[5]}]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports {seg[5]}]
|
||||
#set_property PACKAGE_PIN U7 [get_ports {seg[6]}]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports {seg[6]}]
|
||||
|
||||
#set_property PACKAGE_PIN V7 [get_ports dp]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports dp]
|
||||
|
||||
#set_property PACKAGE_PIN U2 [get_ports {an[0]}]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports {an[0]}]
|
||||
#set_property PACKAGE_PIN U4 [get_ports {an[1]}]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports {an[1]}]
|
||||
#set_property PACKAGE_PIN V4 [get_ports {an[2]}]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports {an[2]}]
|
||||
#set_property PACKAGE_PIN W4 [get_ports {an[3]}]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports {an[3]}]
|
||||
|
||||
|
||||
##Buttons
|
||||
#set_property PACKAGE_PIN U18 [get_ports btnC]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports btnC]
|
||||
#set_property PACKAGE_PIN T18 [get_ports btnU]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports btnU]
|
||||
#set_property PACKAGE_PIN W19 [get_ports btnL]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports btnL]
|
||||
#set_property PACKAGE_PIN T17 [get_ports btnR]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports btnR]
|
||||
#set_property PACKAGE_PIN U17 [get_ports btnD]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports btnD]
|
||||
|
||||
|
||||
|
||||
##Pmod Header JA
|
||||
##Sch name = JA1
|
||||
#set_property PACKAGE_PIN J1 [get_ports {JA[0]}]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports {JA[0]}]
|
||||
##Sch name = JA2
|
||||
#set_property PACKAGE_PIN L2 [get_ports {JA[1]}]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports {JA[1]}]
|
||||
##Sch name = JA3
|
||||
#set_property PACKAGE_PIN J2 [get_ports {JA[2]}]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports {JA[2]}]
|
||||
##Sch name = JA4
|
||||
#set_property PACKAGE_PIN G2 [get_ports {JA[3]}]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports {JA[3]}]
|
||||
##Sch name = JA7
|
||||
#set_property PACKAGE_PIN H1 [get_ports {JA[4]}]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports {JA[4]}]
|
||||
##Sch name = JA8
|
||||
#set_property PACKAGE_PIN K2 [get_ports {JA[5]}]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports {JA[5]}]
|
||||
##Sch name = JA9
|
||||
#set_property PACKAGE_PIN H2 [get_ports {JA[6]}]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports {JA[6]}]
|
||||
##Sch name = JA10
|
||||
#set_property PACKAGE_PIN G3 [get_ports {JA[7]}]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports {JA[7]}]
|
||||
|
||||
|
||||
|
||||
##Pmod Header JB
|
||||
##Sch name = JB1
|
||||
#set_property PACKAGE_PIN A14 [get_ports {JB[0]}]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports {JB[0]}]
|
||||
##Sch name = JB2
|
||||
#set_property PACKAGE_PIN A16 [get_ports {JB[1]}]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports {JB[1]}]
|
||||
##Sch name = JB3
|
||||
#set_property PACKAGE_PIN B15 [get_ports {JB[2]}]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports {JB[2]}]
|
||||
##Sch name = JB4
|
||||
#set_property PACKAGE_PIN B16 [get_ports {JB[3]}]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports {JB[3]}]
|
||||
##Sch name = JB7
|
||||
#set_property PACKAGE_PIN A15 [get_ports {JB[4]}]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports {JB[4]}]
|
||||
##Sch name = JB8
|
||||
#set_property PACKAGE_PIN A17 [get_ports {JB[5]}]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports {JB[5]}]
|
||||
##Sch name = JB9
|
||||
#set_property PACKAGE_PIN C15 [get_ports {JB[6]}]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports {JB[6]}]
|
||||
##Sch name = JB10
|
||||
#set_property PACKAGE_PIN C16 [get_ports {JB[7]}]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports {JB[7]}]
|
||||
|
||||
|
||||
|
||||
##Pmod Header JC
|
||||
##Sch name = JC1
|
||||
#set_property PACKAGE_PIN K17 [get_ports {JC[0]}]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports {JC[0]}]
|
||||
##Sch name = JC2
|
||||
#set_property PACKAGE_PIN M18 [get_ports {JC[1]}]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports {JC[1]}]
|
||||
##Sch name = JC3
|
||||
#set_property PACKAGE_PIN N17 [get_ports {JC[2]}]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports {JC[2]}]
|
||||
##Sch name = JC4
|
||||
#set_property PACKAGE_PIN P18 [get_ports {JC[3]}]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports {JC[3]}]
|
||||
##Sch name = JC7
|
||||
#set_property PACKAGE_PIN L17 [get_ports {JC[4]}]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports {JC[4]}]
|
||||
##Sch name = JC8
|
||||
#set_property PACKAGE_PIN M19 [get_ports {JC[5]}]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports {JC[5]}]
|
||||
##Sch name = JC9
|
||||
#set_property PACKAGE_PIN P17 [get_ports {JC[6]}]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports {JC[6]}]
|
||||
##Sch name = JC10
|
||||
#set_property PACKAGE_PIN R18 [get_ports {JC[7]}]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports {JC[7]}]
|
||||
|
||||
|
||||
##Pmod Header JXADC
|
||||
##Sch name = XA1_P
|
||||
#set_property PACKAGE_PIN J3 [get_ports {JXADC[0]}]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports {JXADC[0]}]
|
||||
##Sch name = XA2_P
|
||||
#set_property PACKAGE_PIN L3 [get_ports {JXADC[1]}]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports {JXADC[1]}]
|
||||
##Sch name = XA3_P
|
||||
#set_property PACKAGE_PIN M2 [get_ports {JXADC[2]}]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports {JXADC[2]}]
|
||||
##Sch name = XA4_P
|
||||
#set_property PACKAGE_PIN N2 [get_ports {JXADC[3]}]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports {JXADC[3]}]
|
||||
##Sch name = XA1_N
|
||||
#set_property PACKAGE_PIN K3 [get_ports {JXADC[4]}]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports {JXADC[4]}]
|
||||
##Sch name = XA2_N
|
||||
#set_property PACKAGE_PIN M3 [get_ports {JXADC[5]}]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports {JXADC[5]}]
|
||||
##Sch name = XA3_N
|
||||
#set_property PACKAGE_PIN M1 [get_ports {JXADC[6]}]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports {JXADC[6]}]
|
||||
##Sch name = XA4_N
|
||||
#set_property PACKAGE_PIN N1 [get_ports {JXADC[7]}]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports {JXADC[7]}]
|
||||
|
||||
|
||||
|
||||
##VGA Connector
|
||||
#set_property PACKAGE_PIN G19 [get_ports {vgaRed[0]}]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports {vgaRed[0]}]
|
||||
#set_property PACKAGE_PIN H19 [get_ports {vgaRed[1]}]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports {vgaRed[1]}]
|
||||
#set_property PACKAGE_PIN J19 [get_ports {vgaRed[2]}]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports {vgaRed[2]}]
|
||||
#set_property PACKAGE_PIN N19 [get_ports {vgaRed[3]}]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports {vgaRed[3]}]
|
||||
#set_property PACKAGE_PIN N18 [get_ports {vgaBlue[0]}]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports {vgaBlue[0]}]
|
||||
#set_property PACKAGE_PIN L18 [get_ports {vgaBlue[1]}]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports {vgaBlue[1]}]
|
||||
#set_property PACKAGE_PIN K18 [get_ports {vgaBlue[2]}]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports {vgaBlue[2]}]
|
||||
#set_property PACKAGE_PIN J18 [get_ports {vgaBlue[3]}]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports {vgaBlue[3]}]
|
||||
#set_property PACKAGE_PIN J17 [get_ports {vgaGreen[0]}]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports {vgaGreen[0]}]
|
||||
#set_property PACKAGE_PIN H17 [get_ports {vgaGreen[1]}]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports {vgaGreen[1]}]
|
||||
#set_property PACKAGE_PIN G17 [get_ports {vgaGreen[2]}]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports {vgaGreen[2]}]
|
||||
#set_property PACKAGE_PIN D17 [get_ports {vgaGreen[3]}]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports {vgaGreen[3]}]
|
||||
#set_property PACKAGE_PIN P19 [get_ports Hsync]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports Hsync]
|
||||
#set_property PACKAGE_PIN R19 [get_ports Vsync]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports Vsync]
|
||||
|
||||
|
||||
##USB-RS232 Interface
|
||||
#set_property PACKAGE_PIN B18 [get_ports RsRx]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports RsRx]
|
||||
#set_property PACKAGE_PIN A18 [get_ports RsTx]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports RsTx]
|
||||
|
||||
|
||||
##USB HID (PS/2)
|
||||
#set_property PACKAGE_PIN C17 [get_ports PS2Clk]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports PS2Clk]
|
||||
#set_property PULLUP true [get_ports PS2Clk]
|
||||
#set_property PACKAGE_PIN B17 [get_ports PS2Data]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports PS2Data]
|
||||
#set_property PULLUP true [get_ports PS2Data]
|
||||
|
||||
|
||||
##Quad SPI Flash
|
||||
##Note that CCLK_0 cannot be placed in 7 series devices. You can access it using the
|
||||
##STARTUPE2 primitive.
|
||||
#set_property PACKAGE_PIN D18 [get_ports {QspiDB[0]}]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports {QspiDB[0]}]
|
||||
#set_property PACKAGE_PIN D19 [get_ports {QspiDB[1]}]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports {QspiDB[1]}]
|
||||
#set_property PACKAGE_PIN G18 [get_ports {QspiDB[2]}]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports {QspiDB[2]}]
|
||||
#set_property PACKAGE_PIN F18 [get_ports {QspiDB[3]}]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports {QspiDB[3]}]
|
||||
#set_property PACKAGE_PIN K19 [get_ports QspiCSn]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports QspiCSn]
|
||||
@@ -0,0 +1,294 @@
|
||||
## This file is a general .xdc for the Basys3 rev B board
|
||||
## To use it in a project:
|
||||
## - uncomment the lines corresponding to used pins
|
||||
## - rename the used ports (in each line, after get_ports) according to the top level signal names in the project
|
||||
|
||||
## Clock signal
|
||||
#set_property PACKAGE_PIN W5 [get_ports clk]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports clk]
|
||||
#create_clock -add -name sys_clk_pin -period 10.00 -waveform {0 5} [get_ports clk]
|
||||
|
||||
## Switches
|
||||
#set_property PACKAGE_PIN V17 [get_ports {sw[0]}]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports {sw[0]}]
|
||||
#set_property PACKAGE_PIN V16 [get_ports {sw[1]}]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports {sw[1]}]
|
||||
#set_property PACKAGE_PIN W16 [get_ports {sw[2]}]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports {sw[2]}]
|
||||
#set_property PACKAGE_PIN W17 [get_ports {sw[3]}]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports {sw[3]}]
|
||||
#set_property PACKAGE_PIN W15 [get_ports {sw[4]}]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports {sw[4]}]
|
||||
#set_property PACKAGE_PIN V15 [get_ports {sw[5]}]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports {sw[5]}]
|
||||
#set_property PACKAGE_PIN W14 [get_ports {sw[6]}]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports {sw[6]}]
|
||||
#set_property PACKAGE_PIN W13 [get_ports {sw[7]}]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports {sw[7]}]
|
||||
#set_property PACKAGE_PIN V2 [get_ports {sw[8]}]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports {sw[8]}]
|
||||
#set_property PACKAGE_PIN T3 [get_ports {sw[9]}]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports {sw[9]}]
|
||||
#set_property PACKAGE_PIN T2 [get_ports {sw[10]}]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports {sw[10]}]
|
||||
#set_property PACKAGE_PIN R3 [get_ports {sw[11]}]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports {sw[11]}]
|
||||
#set_property PACKAGE_PIN W2 [get_ports {sw[12]}]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports {sw[12]}]
|
||||
#set_property PACKAGE_PIN U1 [get_ports {sw[13]}]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports {sw[13]}]
|
||||
#set_property PACKAGE_PIN T1 [get_ports {sw[14]}]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports {sw[14]}]
|
||||
#set_property PACKAGE_PIN R2 [get_ports {sw[15]}]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports {sw[15]}]
|
||||
|
||||
|
||||
## LEDs
|
||||
#set_property PACKAGE_PIN U16 [get_ports {led[0]}]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports {led[0]}]
|
||||
#set_property PACKAGE_PIN E19 [get_ports {led[1]}]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports {led[1]}]
|
||||
#set_property PACKAGE_PIN U19 [get_ports {led[2]}]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports {led[2]}]
|
||||
#set_property PACKAGE_PIN V19 [get_ports {led[3]}]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports {led[3]}]
|
||||
#set_property PACKAGE_PIN W18 [get_ports {led[4]}]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports {led[4]}]
|
||||
#set_property PACKAGE_PIN U15 [get_ports {led[5]}]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports {led[5]}]
|
||||
#set_property PACKAGE_PIN U14 [get_ports {led[6]}]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports {led[6]}]
|
||||
#set_property PACKAGE_PIN V14 [get_ports {led[7]}]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports {led[7]}]
|
||||
#set_property PACKAGE_PIN V13 [get_ports {led[8]}]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports {led[8]}]
|
||||
#set_property PACKAGE_PIN V3 [get_ports {led[9]}]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports {led[9]}]
|
||||
#set_property PACKAGE_PIN W3 [get_ports {led[10]}]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports {led[10]}]
|
||||
#set_property PACKAGE_PIN U3 [get_ports {led[11]}]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports {led[11]}]
|
||||
#set_property PACKAGE_PIN P3 [get_ports {led[12]}]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports {led[12]}]
|
||||
#set_property PACKAGE_PIN N3 [get_ports {led[13]}]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports {led[13]}]
|
||||
#set_property PACKAGE_PIN P1 [get_ports {led[14]}]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports {led[14]}]
|
||||
#set_property PACKAGE_PIN L1 [get_ports {led[15]}]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports {led[15]}]
|
||||
|
||||
|
||||
##7 segment display
|
||||
#set_property PACKAGE_PIN W7 [get_ports {seg[0]}]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports {seg[0]}]
|
||||
#set_property PACKAGE_PIN W6 [get_ports {seg[1]}]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports {seg[1]}]
|
||||
#set_property PACKAGE_PIN U8 [get_ports {seg[2]}]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports {seg[2]}]
|
||||
#set_property PACKAGE_PIN V8 [get_ports {seg[3]}]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports {seg[3]}]
|
||||
#set_property PACKAGE_PIN U5 [get_ports {seg[4]}]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports {seg[4]}]
|
||||
#set_property PACKAGE_PIN V5 [get_ports {seg[5]}]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports {seg[5]}]
|
||||
#set_property PACKAGE_PIN U7 [get_ports {seg[6]}]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports {seg[6]}]
|
||||
|
||||
#set_property PACKAGE_PIN V7 [get_ports dp]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports dp]
|
||||
|
||||
#set_property PACKAGE_PIN U2 [get_ports {an[0]}]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports {an[0]}]
|
||||
#set_property PACKAGE_PIN U4 [get_ports {an[1]}]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports {an[1]}]
|
||||
#set_property PACKAGE_PIN V4 [get_ports {an[2]}]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports {an[2]}]
|
||||
#set_property PACKAGE_PIN W4 [get_ports {an[3]}]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports {an[3]}]
|
||||
|
||||
|
||||
##Buttons
|
||||
#set_property PACKAGE_PIN U18 [get_ports btnC]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports btnC]
|
||||
#set_property PACKAGE_PIN T18 [get_ports btnU]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports btnU]
|
||||
#set_property PACKAGE_PIN W19 [get_ports btnL]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports btnL]
|
||||
#set_property PACKAGE_PIN T17 [get_ports btnR]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports btnR]
|
||||
#set_property PACKAGE_PIN U17 [get_ports btnD]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports btnD]
|
||||
|
||||
|
||||
|
||||
##Pmod Header JA
|
||||
##Sch name = JA1
|
||||
#set_property PACKAGE_PIN J1 [get_ports {JA[0]}]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports {JA[0]}]
|
||||
##Sch name = JA2
|
||||
#set_property PACKAGE_PIN L2 [get_ports {JA[1]}]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports {JA[1]}]
|
||||
##Sch name = JA3
|
||||
#set_property PACKAGE_PIN J2 [get_ports {JA[2]}]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports {JA[2]}]
|
||||
##Sch name = JA4
|
||||
#set_property PACKAGE_PIN G2 [get_ports {JA[3]}]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports {JA[3]}]
|
||||
##Sch name = JA7
|
||||
#set_property PACKAGE_PIN H1 [get_ports {JA[4]}]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports {JA[4]}]
|
||||
##Sch name = JA8
|
||||
#set_property PACKAGE_PIN K2 [get_ports {JA[5]}]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports {JA[5]}]
|
||||
##Sch name = JA9
|
||||
#set_property PACKAGE_PIN H2 [get_ports {JA[6]}]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports {JA[6]}]
|
||||
##Sch name = JA10
|
||||
#set_property PACKAGE_PIN G3 [get_ports {JA[7]}]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports {JA[7]}]
|
||||
|
||||
|
||||
|
||||
##Pmod Header JB
|
||||
##Sch name = JB1
|
||||
#set_property PACKAGE_PIN A14 [get_ports {JB[0]}]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports {JB[0]}]
|
||||
##Sch name = JB2
|
||||
#set_property PACKAGE_PIN A16 [get_ports {JB[1]}]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports {JB[1]}]
|
||||
##Sch name = JB3
|
||||
#set_property PACKAGE_PIN B15 [get_ports {JB[2]}]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports {JB[2]}]
|
||||
##Sch name = JB4
|
||||
#set_property PACKAGE_PIN B16 [get_ports {JB[3]}]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports {JB[3]}]
|
||||
##Sch name = JB7
|
||||
#set_property PACKAGE_PIN A15 [get_ports {JB[4]}]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports {JB[4]}]
|
||||
##Sch name = JB8
|
||||
#set_property PACKAGE_PIN A17 [get_ports {JB[5]}]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports {JB[5]}]
|
||||
##Sch name = JB9
|
||||
#set_property PACKAGE_PIN C15 [get_ports {JB[6]}]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports {JB[6]}]
|
||||
##Sch name = JB10
|
||||
#set_property PACKAGE_PIN C16 [get_ports {JB[7]}]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports {JB[7]}]
|
||||
|
||||
|
||||
|
||||
##Pmod Header JC
|
||||
##Sch name = JC1
|
||||
#set_property PACKAGE_PIN K17 [get_ports {JC[0]}]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports {JC[0]}]
|
||||
##Sch name = JC2
|
||||
#set_property PACKAGE_PIN M18 [get_ports {JC[1]}]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports {JC[1]}]
|
||||
##Sch name = JC3
|
||||
#set_property PACKAGE_PIN N17 [get_ports {JC[2]}]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports {JC[2]}]
|
||||
##Sch name = JC4
|
||||
#set_property PACKAGE_PIN P18 [get_ports {JC[3]}]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports {JC[3]}]
|
||||
##Sch name = JC7
|
||||
#set_property PACKAGE_PIN L17 [get_ports {JC[4]}]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports {JC[4]}]
|
||||
##Sch name = JC8
|
||||
#set_property PACKAGE_PIN M19 [get_ports {JC[5]}]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports {JC[5]}]
|
||||
##Sch name = JC9
|
||||
#set_property PACKAGE_PIN P17 [get_ports {JC[6]}]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports {JC[6]}]
|
||||
##Sch name = JC10
|
||||
#set_property PACKAGE_PIN R18 [get_ports {JC[7]}]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports {JC[7]}]
|
||||
|
||||
|
||||
##Pmod Header JXADC
|
||||
##Sch name = XA1_P
|
||||
#set_property PACKAGE_PIN J3 [get_ports {JXADC[0]}]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports {JXADC[0]}]
|
||||
##Sch name = XA2_P
|
||||
#set_property PACKAGE_PIN L3 [get_ports {JXADC[1]}]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports {JXADC[1]}]
|
||||
##Sch name = XA3_P
|
||||
#set_property PACKAGE_PIN M2 [get_ports {JXADC[2]}]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports {JXADC[2]}]
|
||||
##Sch name = XA4_P
|
||||
#set_property PACKAGE_PIN N2 [get_ports {JXADC[3]}]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports {JXADC[3]}]
|
||||
##Sch name = XA1_N
|
||||
#set_property PACKAGE_PIN K3 [get_ports {JXADC[4]}]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports {JXADC[4]}]
|
||||
##Sch name = XA2_N
|
||||
#set_property PACKAGE_PIN M3 [get_ports {JXADC[5]}]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports {JXADC[5]}]
|
||||
##Sch name = XA3_N
|
||||
#set_property PACKAGE_PIN M1 [get_ports {JXADC[6]}]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports {JXADC[6]}]
|
||||
##Sch name = XA4_N
|
||||
#set_property PACKAGE_PIN N1 [get_ports {JXADC[7]}]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports {JXADC[7]}]
|
||||
|
||||
|
||||
|
||||
##VGA Connector
|
||||
#set_property PACKAGE_PIN G19 [get_ports {vgaRed[0]}]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports {vgaRed[0]}]
|
||||
#set_property PACKAGE_PIN H19 [get_ports {vgaRed[1]}]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports {vgaRed[1]}]
|
||||
#set_property PACKAGE_PIN J19 [get_ports {vgaRed[2]}]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports {vgaRed[2]}]
|
||||
#set_property PACKAGE_PIN N19 [get_ports {vgaRed[3]}]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports {vgaRed[3]}]
|
||||
#set_property PACKAGE_PIN N18 [get_ports {vgaBlue[0]}]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports {vgaBlue[0]}]
|
||||
#set_property PACKAGE_PIN L18 [get_ports {vgaBlue[1]}]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports {vgaBlue[1]}]
|
||||
#set_property PACKAGE_PIN K18 [get_ports {vgaBlue[2]}]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports {vgaBlue[2]}]
|
||||
#set_property PACKAGE_PIN J18 [get_ports {vgaBlue[3]}]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports {vgaBlue[3]}]
|
||||
#set_property PACKAGE_PIN J17 [get_ports {vgaGreen[0]}]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports {vgaGreen[0]}]
|
||||
#set_property PACKAGE_PIN H17 [get_ports {vgaGreen[1]}]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports {vgaGreen[1]}]
|
||||
#set_property PACKAGE_PIN G17 [get_ports {vgaGreen[2]}]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports {vgaGreen[2]}]
|
||||
#set_property PACKAGE_PIN D17 [get_ports {vgaGreen[3]}]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports {vgaGreen[3]}]
|
||||
#set_property PACKAGE_PIN P19 [get_ports Hsync]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports Hsync]
|
||||
#set_property PACKAGE_PIN R19 [get_ports Vsync]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports Vsync]
|
||||
|
||||
|
||||
##USB-RS232 Interface
|
||||
#set_property PACKAGE_PIN B18 [get_ports RsRx]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports RsRx]
|
||||
#set_property PACKAGE_PIN A18 [get_ports RsTx]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports RsTx]
|
||||
|
||||
|
||||
##USB HID (PS/2)
|
||||
#set_property PACKAGE_PIN C17 [get_ports PS2Clk]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports PS2Clk]
|
||||
#set_property PULLUP true [get_ports PS2Clk]
|
||||
#set_property PACKAGE_PIN B17 [get_ports PS2Data]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports PS2Data]
|
||||
#set_property PULLUP true [get_ports PS2Data]
|
||||
|
||||
|
||||
##Quad SPI Flash
|
||||
##Note that CCLK_0 cannot be placed in 7 series devices. You can access it using the
|
||||
##STARTUPE2 primitive.
|
||||
#set_property PACKAGE_PIN D18 [get_ports {QspiDB[0]}]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports {QspiDB[0]}]
|
||||
#set_property PACKAGE_PIN D19 [get_ports {QspiDB[1]}]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports {QspiDB[1]}]
|
||||
#set_property PACKAGE_PIN G18 [get_ports {QspiDB[2]}]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports {QspiDB[2]}]
|
||||
#set_property PACKAGE_PIN F18 [get_ports {QspiDB[3]}]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports {QspiDB[3]}]
|
||||
#set_property PACKAGE_PIN K19 [get_ports QspiCSn]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports QspiCSn]
|
||||
@@ -21,8 +21,12 @@ The course focuses on:
|
||||
- Implement and test **VHDL architectures** using Vivado and Basys 3
|
||||
- Learn about **FPGA timing, power, I/O, and memory management**
|
||||
|
||||
<!-- ## 📂 Repository Structure
|
||||
This section outlines the organization of the repository, including directories for source files, simulations, and documentation. -->
|
||||
## 📂 Repository Structure
|
||||
- `LABx/`
|
||||
- `src/`: VHDL source files
|
||||
- `sim/`: Simulation files
|
||||
- `cons/`: Constraint files
|
||||
- `vivado/`: Vivado project files
|
||||
|
||||
## 📬 Contact
|
||||
For any questions or issues open an issue in this repository.
|
||||
Reference in new issue
Block a user