Cd16d 1d779b7d3a Add testbench for balance_controller and update Vivado project files

2025-05-22 11:22:57 +02:00

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cons

Add initial design files and project configuration for LAB3

2025-05-12 14:20:41 +02:00

design

Add Vivado project files and testbench configurations for volume multiplier and volume saturator

2025-05-21 00:31:23 +02:00

ip

Add AXI4-Stream UART IP and associated files

2025-05-12 18:16:58 +02:00

sim

Add testbench for balance_controller and update Vivado project files

2025-05-22 11:22:57 +02:00

src

Add testbench for balance_controller and update Vivado project files

2025-05-22 11:22:57 +02:00

test

Refactor code structure for improved readability and maintainability

2025-05-17 20:03:03 +02:00

vivado

Add testbench for balance_controller and update Vivado project files

2025-05-22 11:22:57 +02:00