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PickleRick
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DESD
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1d779b7d3a2e5fe28f4ecd67aad25c81d6b414ab
DESD
/
LAB3
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vivado
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Cd16d
1d779b7d3a
Add testbench for balance_controller and update Vivado project files
2025-05-22 11:22:57 +02:00
..
balance_controller
Add testbench for balance_controller and update Vivado project files
2025-05-22 11:22:57 +02:00
diligent_jstk
Refactor volume_saturator VHDL code for improved readability and structure; update project files for consistent path references and disable unused components in lab3 design.
2025-05-19 16:24:36 +02:00
lab3
Add Vivado project files and testbench configurations for volume multiplier and volume saturator
2025-05-21 00:31:23 +02:00
loopback_I2S
Add AXI4-Stream UART IP and associated files
2025-05-12 18:16:58 +02:00
volume_multiplier
Refactor volume_multiplier
2025-05-21 20:37:47 +02:00
volume_saturator
Add Vivado project files and testbench configurations for volume multiplier and volume saturator
2025-05-21 00:31:23 +02:00
