Cd16d
b11c65043f
- Created board.xit for physical constraints related to UART interface. - Added vv_index.xml to define the AXI4-Stream UART IP with relevant metadata. - Implemented GUI for AXI4-Stream UART parameters in AXI4Stream_UART_v1_0.tcl and AXI4Stream_UART_v1_1.tcl. - Initialized Vivado project files for diligent_jstk and loopback_I2S designs, including synthesis and implementation settings. - Configured file sets and simulation options for both projects.
239 lines
9.5 KiB
VHDL
239 lines
9.5 KiB
VHDL
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---- * ) ----
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----` ) /( ( ) ( ( ( ( ( ( ( ( ( ( ( ----
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---- ( )(_)))\ ( ))\ )\ ( )\))( )\ ( ))\ ))\ )( )\ ( )\))( ----
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----(_(_())((_) )\ ' /((_) ((_) )\ ) ((_))\((_) )\ ) /((_)/((_)(()\((_) )\ ) ((_))\ ----
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----|_ _| (_) _((_)) (_)) | __| _(_/( (()(_)(_) _(_/( (_)) (_)) ((_)(_) _(_/( (()(_) ----
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---- | | | || ' \()/ -_) | _| | ' \))/ _` | | || ' \))/ -_)/ -_) | '_|| || ' \))/ _` | ----
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---- |_| |_||_|_|_| \___| |___||_||_| \__, | |_||_||_| \___|\___| |_| |_||_||_| \__, | ----
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---- |___/ |___/ ----
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---- _____ _ ___ __ _ _ _ __ _ ----
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---- o O O |_ _| (_) _ __ ___ | __| _ _ / _` | (_) _ _ ___ ___ _ _ (_) _ _ / _` | ----
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---- o | | | | | ' \ / -_) | _| | ' \ \__, | | | | ' \ / -_) / -_) | '_| | | | ' \ \__, | ----
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---- TS__[O] _|_|_ _|_|_ |_|_|_| \___| |___| |_||_| |___/ _|_|_ |_||_| \___| \___| _|_|_ _|_|_ |_||_| |___/ ----
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---- {======|_|"""""|_|"""""|_|"""""|_|"""""|_|"""""|_|"""""|_|"""""|_|"""""|_|"""""|_|"""""|_|"""""|_|"""""|_|"""""|_|"""""|_|"""""| ----
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----./o--000'"`-0-0-'"`-0-0-'"`-0-0-'"`-0-0-'"`-0-0-'"`-0-0-'"`-0-0-'"`-0-0-'"`-0-0-'"`-0-0-'"`-0-0-'"`-0-0-'"`-0-0-'"`-0-0-'"`-0-0-' ----
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-------------------------------------DESCRIPTION------------------------------------------
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------------------------------------------------------------------------------------------
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-- Modulo di pi<70> basso livello per la gestione dei dati tra FIFO in e FIFO out ed il --
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-- modulo FTDI 2232H in modalita FT245 Asynchronous. La priorit<69> <20> data ai dati in --
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-- arrivo dal PC verso FPGA. --
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-- Il clock in ingresso deve avere un periodo di 10 ns per garantire i tempi --
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-- rischiesti dal 2232H --
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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entity UART_Manager is
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generic(
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UART_BAUD_RATE : positive;
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UART_CLOCK_FREQUENCY : positive --The associated clock frequency
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);
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Port (
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---------Global---------
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clk_uart : IN STD_LOGIC;
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reset : IN STD_LOGIC;
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------------------------
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---------Connessioni comunicazione UART-----------
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UART_TX : OUT STD_LOGIC;
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UART_RX : IN STD_LOGIC;
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---------------------------------------------------
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------------FIFO_DATA_RX (8bit)-------------
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FIFO_DATA_RX_rst : OUT STD_LOGIC;
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FIFO_DATA_RX_clk : OUT STD_LOGIC;
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FIFO_DATA_RX_din : OUT STD_LOGIC_VECTOR(8-1 DOWNTO 0);
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FIFO_DATA_RX_wr_en : OUT STD_LOGIC;
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FIFO_DATA_RX_full : IN STD_LOGIC;
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FIFO_DATA_RX_almost_full : IN STD_LOGIC;
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--------------------------------------------
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------------FIFO_DATA_TX (8bit)-------------
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--FIFO_DATA_RX_rst : OUT STD_LOGIC;
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FIFO_DATA_TX_clk : OUT STD_LOGIC;
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FIFO_DATA_TX_dout : IN STD_LOGIC_VECTOR(8-1 DOWNTO 0);
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FIFO_DATA_TX_rd_en : OUT STD_LOGIC;
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FIFO_DATA_TX_empty : IN STD_LOGIC;
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FIFO_DATA_TX_almost_empty : IN STD_LOGIC
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--------------------------------------------
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);
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end UART_Manager;
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architecture Behavioral of UART_Manager is
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-------------------COMPONENT------------------
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COMPONENT UART_engine
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GENERIC(
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BAUD_RATE : positive;
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CLOCK_FREQUENCY : positive
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);
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PORT(
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--SYSTEM UART
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clock : IN std_logic;
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reset : IN std_logic;
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-- FPGA-->PC
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data_stream_in : IN std_logic_vector(7 downto 0);
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data_stream_in_stb : IN std_logic;
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data_stream_in_ack : OUT std_logic;
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data_stream_in_done : OUT std_logic;
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tx : OUT std_logic;
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-- PC-->FPGA
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data_stream_out : OUT std_logic_vector(7 downto 0);
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data_stream_out_stb : OUT std_logic;
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rx : IN std_logic
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);
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END COMPONENT;
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----------------------------------------------
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--------------------SIGNALS-------------------
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signal state : STD_LOGIC_VECTOR(7 DOWNTO 0):=x"00";
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--TX:fromFPGAtoPC
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signal data_stream_in : STD_LOGIC_VECTOR(7 DOWNTO 0) := (others=>'0');
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signal data_stream_in_stb : STD_LOGIC := '0';
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signal data_stream_in_ack : STD_LOGIC := '0';
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signal data_stream_in_done : STD_LOGIC := '0';
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signal state_TX : STD_LOGIC_VECTOR(7 DOWNTO 0):=x"FF";
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--RX:fromPCtoFPGA
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signal data_stream_out : STD_LOGIC_VECTOR(7 DOWNTO 0) := (others=>'0');
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signal data_stream_out_stb : STD_LOGIC := '0';
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----------------------------------------------
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begin
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Inst_uart: UART_engine
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GENERIC MAP (
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BAUD_RATE => UART_BAUD_RATE,
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CLOCK_FREQUENCY => UART_CLOCK_FREQUENCY
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)
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PORT MAP(
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clock => clk_uart,
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reset => reset,
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-- FPGA-->PC
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data_stream_in => data_stream_in, --byte FPGA->PC, (in)
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data_stream_in_stb => data_stream_in_stb, --'1' per 1 clock inizia la fase di trasmisisone a PC di data_stream_in (in)
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data_stream_in_ack => data_stream_in_ack, --'1' per 1 clock vuol dire che START TX (data_stream_in_stb='1') <20> stata capita (in)
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data_stream_in_done => data_stream_in_done, --'1' indica la fine della trasmisione (out)
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tx => UART_TX,
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-- PC-->FPGA
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data_stream_out => data_stream_out, --byte PC->FPGA, (out)
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data_stream_out_stb => data_stream_out_stb, --'1' per 1 clock indica che su data_stream_out c'<27> un nuovo dato (out)
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-- data_stream_out => FIFO_RX_din,
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-- data_stream_out_stb => FIFO_RX_wr_en,
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rx => UART_RX
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);
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fromFPGAtoPC : process(clk_uart, reset)
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begin
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if (reset = '1') then
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state_TX <= x"00";
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--UART
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data_stream_in <= (others => '0');
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data_stream_in_stb <= '0';
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--FIFO_TX
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FIFO_DATA_TX_rd_en <= '0';
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elsif rising_edge(clk_uart) then
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case state_TX is
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when x"FF" =>
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if(reset = '0') then
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state_TX <= x"00";
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else
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state_TX <= x"FF";
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end if;
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--UART
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data_stream_in <= (others => '0');
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data_stream_in_stb <= '0';
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--FIFO_TX
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FIFO_DATA_TX_rd_en <= '0';
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when x"00" =>
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FIFO_DATA_TX_rd_en <= '0';
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data_stream_in_stb <= '0';
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if (FIFO_DATA_TX_empty = '0') then --nessun dato da trasmettere al PC
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state_TX <= x"01"; --si hanno dati in FIFO TX da passare al PC
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FIFO_DATA_TX_rd_en <= '1'; --abilita lettura FIFO
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data_stream_in <= FIFO_DATA_TX_dout; --dai alla UART il byte in uscita dalla fifo gi<67> pronto
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data_stream_in_stb <= '1'; --abilita TX della UART
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end if;
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when x"01" =>
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FIFO_DATA_TX_rd_en <= '0'; --blocca la lettura FIFO
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--tieni data_stream_in_stb attivo finche la UART non inizia a trasferire data_stream_in_ack='0'
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if (data_stream_in_ack = '1') then
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state_TX <= x"02";
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data_stream_in_stb <= '0';
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end if;
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when x"02" =>
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-- data_stream_in_done = '1' significa fin trasmisisone UART
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if (data_stream_in_done = '1') then
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state_TX <= x"00";
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end if;
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when others =>
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state_TX <= x"00";
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end case;
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end if;
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end process;
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fromPCtoFPGA : process(clk_uart, reset)
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begin
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if (reset = '1') then
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FIFO_DATA_RX_din <= (others => '0');
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FIFO_DATA_RX_wr_en <= '0';
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elsif rising_edge(clk_uart) then
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FIFO_DATA_RX_wr_en <= '0';
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if (data_stream_out_stb = '1') then --arrivato nuovo dato sulla UART, caricalo in FIGO RX
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FIFO_DATA_RX_wr_en <= '1';
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FIFO_DATA_RX_din <= data_stream_out;
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end if;
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end if;
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end process;
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--------------------ASSIGMENT------------------
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FIFO_DATA_RX_clk <= clk_uart;
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FIFO_DATA_TX_clk <= clk_uart;
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FIFO_DATA_RX_rst <= reset;
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-----------------------------------------------
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end Behavioral;
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