Davide 1eb2181d1d Update design files for diligent_jstk: change synthesis flow mode to Hierarchical, adjust XCI paths, and enhance UART viewer for real-time coordinate visualization with updated axis limits.

2025-05-17 13:29:40 +02:00

..

diligent_jstk

Update design files for diligent_jstk: change synthesis flow mode to Hierarchical, adjust XCI paths, and enhance UART viewer for real-time coordinate visualization with updated axis limits.

2025-05-17 13:29:40 +02:00

lab_3

Refactor lab_3.bda to update node IDs and edge connections; modify digilent_jstk2.vhd to increase packet delay and adjust state machine; enhance uart_viewer.py for real-time coordinate visualization using matplotlib; update diligent_jstk.xpr simulation settings and remove unused file sets; add new Vivado project zip files for diligent_jstk and lab3.

2025-05-16 16:43:45 +02:00

loopback_I2S

Add AXI4-Stream UART IP and associated files

2025-05-12 18:16:58 +02:00