Davide 1eb2181d1d Update design files for diligent_jstk: change synthesis flow mode to Hierarchical, adjust XCI paths, and enhance UART viewer for real-time coordinate visualization with updated axis limits.

2025-05-17 13:29:40 +02:00

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cons

Add initial design files and project configuration for LAB3

2025-05-12 14:20:41 +02:00

design

Update design files for diligent_jstk: change synthesis flow mode to Hierarchical, adjust XCI paths, and enhance UART viewer for real-time coordinate visualization with updated axis limits.

2025-05-17 13:29:40 +02:00

ip

Add AXI4-Stream UART IP and associated files

2025-05-12 18:16:58 +02:00

sim

Update VHDL and Python files for improved functionality and performance

2025-05-15 16:46:09 +02:00

src

Update design files for diligent_jstk: change synthesis flow mode to Hierarchical, adjust XCI paths, and enhance UART viewer for real-time coordinate visualization with updated axis limits.

2025-05-17 13:29:40 +02:00

test

Update design files for diligent_jstk: change synthesis flow mode to Hierarchical, adjust XCI paths, and enhance UART viewer for real-time coordinate visualization with updated axis limits.

2025-05-17 13:29:40 +02:00

vivado

Refactor diligent_jstk design files: update clock wizard paths, modify interface nets, enhance uart_viewer.py for real-time data visualization, and remove unused Vivado project zip file.

2025-05-16 22:49:31 +02:00