Davide 1eb2181d1d Update design files for diligent_jstk: change synthesis flow mode to Hierarchical, adjust XCI paths, and enhance UART viewer for real-time coordinate visualization with updated axis limits.

2025-05-17 13:29:40 +02:00

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uart_viewer.py

Update design files for diligent_jstk: change synthesis flow mode to Hierarchical, adjust XCI paths, and enhance UART viewer for real-time coordinate visualization with updated axis limits.

2025-05-17 13:29:40 +02:00