256 lines
16 KiB
VHDL
256 lines
16 KiB
VHDL
LIBRARY IEEE;
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USE IEEE.STD_LOGIC_1164.ALL;
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USE IEEE.NUMERIC_STD.ALL;
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-- Entity: LFO_1 (Low Frequency Oscillator)
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-- Purpose: Applies tremolo effect to audio by modulating amplitude with a triangular wave
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-- Creates classic audio effects like vibrato, tremolo, and amplitude modulation
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-- Implements a 3-stage pipeline for efficient real-time audio processing
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ENTITY LFO_1 IS
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GENERIC (
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CHANNEL_LENGHT : INTEGER := 24; -- Bit width of audio samples (24-bit signed)
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JOYSTICK_LENGHT : INTEGER := 10; -- Bit width of joystick input (10-bit = 0-1023 range)
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CLK_PERIOD_NS : INTEGER := 10; -- Clock period in nanoseconds (10ns = 100MHz)
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TRIANGULAR_COUNTER_LENGHT : INTEGER := 10 -- Bit width of triangular wave counter (affects modulation depth)
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);
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PORT (
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-- Clock and Reset
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aclk : IN STD_LOGIC; -- Main system clock
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aresetn : IN STD_LOGIC; -- Active-low asynchronous reset
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-- LFO_1 Control inputs
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lfo_period : IN STD_LOGIC_VECTOR(JOYSTICK_LENGHT - 1 DOWNTO 0); -- Controls LFO_1 frequency (joystick Y-axis)
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lfo_enable : IN STD_LOGIC; -- Enable/bypass LFO_1 effect
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-- Slave AXI Stream interface (audio input)
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s_axis_tvalid : IN STD_LOGIC; -- Input data valid signal
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s_axis_tdata : IN STD_LOGIC_VECTOR(CHANNEL_LENGHT - 1 DOWNTO 0); -- Audio sample input
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s_axis_tlast : IN STD_LOGIC; -- Channel indicator (0=left, 1=right)
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s_axis_tready : OUT STD_LOGIC; -- Ready to accept input data
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-- Master AXI Stream interface (audio output)
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m_axis_tvalid : OUT STD_LOGIC; -- Output data valid signal
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m_axis_tdata : OUT STD_LOGIC_VECTOR(CHANNEL_LENGHT - 1 DOWNTO 0); -- Modulated audio sample output
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m_axis_tlast : OUT STD_LOGIC; -- Channel indicator passthrough
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m_axis_tready : IN STD_LOGIC -- Downstream ready signal
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);
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END ENTITY LFO_1;
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ARCHITECTURE Behavioral OF LFO_1 IS
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-- Constants for LFO_1 timing configuration
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CONSTANT BASE_PERIOD_MICROSECONDS : INTEGER := 1000; -- Base period: 1ms (1kHz base frequency)
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CONSTANT FREQUENCY_ADJUSTMENT_FACTOR : INTEGER := 90; -- Frequency adjustment sensitivity (clock cycles per joystick unit)
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CONSTANT JOYSTICK_CENTER_VALUE : INTEGER := 2 ** (JOYSTICK_LENGHT - 1); -- Joystick center position (512 for 10-bit)
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-- Calculate base clock cycles for 1ms period at current clock frequency
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CONSTANT BASE_CLOCK_CYCLES : INTEGER := BASE_PERIOD_MICROSECONDS * 1000 / CLK_PERIOD_NS;
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-- Calculate frequency range limits based on joystick range
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-- Minimum frequency (fastest LFO_1): occurs when joystick is at minimum position
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CONSTANT MIN_CLOCK_CYCLES : INTEGER := BASE_CLOCK_CYCLES - FREQUENCY_ADJUSTMENT_FACTOR * (2 ** (JOYSTICK_LENGHT - 1));
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-- Maximum frequency (slowest LFO_1): occurs when joystick is at maximum position
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CONSTANT MAX_CLOCK_CYCLES : INTEGER := BASE_CLOCK_CYCLES + FREQUENCY_ADJUSTMENT_FACTOR * (2 ** (JOYSTICK_LENGHT - 1) - 1);
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-- Internal signals for LFO_1 control
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-- Period adjustment based on joystick input (positive = slower, negative = faster)
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SIGNAL period_adjustment_delta : INTEGER RANGE - 2 ** (JOYSTICK_LENGHT - 1) * FREQUENCY_ADJUSTMENT_FACTOR
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TO (2 ** (JOYSTICK_LENGHT - 1) - 1) * FREQUENCY_ADJUSTMENT_FACTOR := 0;
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SIGNAL current_period_cycles : INTEGER RANGE MIN_CLOCK_CYCLES TO MAX_CLOCK_CYCLES := BASE_CLOCK_CYCLES;
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-- Pipeline stage 1 registers - Input processing and period calculation
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SIGNAL audio_data_stage1 : STD_LOGIC_VECTOR(CHANNEL_LENGHT - 1 DOWNTO 0) := (OTHERS => '0'); -- Registered audio input
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SIGNAL enable_flag_stage1 : STD_LOGIC := '0'; -- Registered LFO_1 enable
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SIGNAL valid_flag_stage1 : STD_LOGIC := '0'; -- Valid data in stage 1
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SIGNAL last_flag_stage1 : STD_LOGIC := '0'; -- Registered channel indicator
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-- Pipeline stage 2 registers - Triangular wave generation
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SIGNAL triangular_wave_value : unsigned(TRIANGULAR_COUNTER_LENGHT - 1 DOWNTO 0) := (OTHERS => '0'); -- Current triangular wave amplitude
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SIGNAL wave_direction_up : STD_LOGIC := '1'; -- Triangle wave direction: '1' = ascending, '0' = descending
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SIGNAL timing_counter : NATURAL RANGE 0 TO MAX_CLOCK_CYCLES := 0; -- Clock cycle counter for LFO_1 timing
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SIGNAL enable_flag_stage2 : STD_LOGIC := '0'; -- LFO_1 enable flag for stage 2
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SIGNAL valid_flag_stage2 : STD_LOGIC := '0'; -- Valid data in stage 2
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SIGNAL last_flag_stage2 : STD_LOGIC := '0'; -- Channel indicator for stage 2
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SIGNAL audio_data_stage2 : STD_LOGIC_VECTOR(CHANNEL_LENGHT - 1 DOWNTO 0) := (OTHERS => '0'); -- Audio data for stage 2
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-- Pipeline stage 3 registers - Modulation and output
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-- Extended width to accommodate multiplication result before scaling
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SIGNAL multiplication_result : STD_LOGIC_VECTOR(CHANNEL_LENGHT + TRIANGULAR_COUNTER_LENGHT - 1 DOWNTO 0) := (OTHERS => '0');
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-- Internal AXI4-Stream control signals
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SIGNAL master_valid_internal : STD_LOGIC := '0'; -- Internal output valid signal
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SIGNAL slave_ready_internal : STD_LOGIC := '1'; -- Internal input ready signal
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BEGIN
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-- Direct connection: tlast passes through unchanged (maintains channel timing)
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m_axis_tlast <= last_flag_stage1;
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-- Pipeline stage 1: Input registration and LFO_1 period calculation
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-- This stage captures input data and calculates the LFO_1 period based on joystick position
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input_processing_stage : PROCESS (aclk)
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BEGIN
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IF rising_edge(aclk) THEN
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IF aresetn = '0' THEN
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-- Reset all stage 1 registers to safe initial states
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audio_data_stage1 <= (OTHERS => '0'); -- Clear audio data
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current_period_cycles <= BASE_CLOCK_CYCLES; -- Set to base frequency
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enable_flag_stage1 <= '0'; -- Disable LFO_1
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valid_flag_stage1 <= '0'; -- No valid data
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last_flag_stage1 <= '0'; -- Clear channel indicator
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ELSE
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-- Calculate LFO_1 period based on joystick y-axis input
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-- Joystick mapping:
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-- 0-511: Faster than base frequency (shorter period)
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-- 512: Base frequency (1kHz)
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-- 513-1023: Slower than base frequency (longer period)
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period_adjustment_delta <= (to_integer(unsigned(lfo_period)) - JOYSTICK_CENTER_VALUE) * FREQUENCY_ADJUSTMENT_FACTOR;
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current_period_cycles <= BASE_CLOCK_CYCLES - period_adjustment_delta;
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-- AXI4-Stream handshake: accept new data when both valid and ready
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IF s_axis_tvalid = '1' AND slave_ready_internal = '1' THEN
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audio_data_stage1 <= s_axis_tdata; -- Register input audio sample
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enable_flag_stage1 <= lfo_enable; -- Register enable control
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valid_flag_stage1 <= '1'; -- Mark data as valid for next stage
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last_flag_stage1 <= s_axis_tlast; -- Register channel boundary signal
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ELSE
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valid_flag_stage1 <= '0'; -- No valid data to pass to next stage
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END IF;
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END IF;
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END IF;
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END PROCESS input_processing_stage;
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-- Pipeline stage 2: Triangular wave generation
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-- This stage generates the triangular wave that will modulate the audio amplitude
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triangular_wave_generator : PROCESS (aclk)
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BEGIN
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IF rising_edge(aclk) THEN
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IF aresetn = '0' THEN
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-- Reset triangular wave generator to initial state
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timing_counter <= 0; -- Clear timing counter
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triangular_wave_value <= (OTHERS => '0'); -- Start at zero amplitude
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wave_direction_up <= '1'; -- Start counting up
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enable_flag_stage2 <= '0'; -- Disable LFO_1
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valid_flag_stage2 <= '0'; -- No valid data
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last_flag_stage2 <= '0'; -- Clear channel indicator
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audio_data_stage2 <= (OTHERS => '0'); -- Clear audio data
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ELSE
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-- Pass through pipeline registers from stage 1 to stage 2
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enable_flag_stage2 <= enable_flag_stage1; -- Forward enable flag
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valid_flag_stage2 <= valid_flag_stage1; -- Forward valid flag
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last_flag_stage2 <= last_flag_stage1; -- Forward channel indicator
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audio_data_stage2 <= audio_data_stage1; -- Forward audio data
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-- Generate triangular wave when LFO_1 is enabled
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IF enable_flag_stage1 = '1' THEN
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-- Clock divider: update triangular counter based on calculated period
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IF timing_counter < current_period_cycles THEN
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timing_counter <= timing_counter + 1; -- Count towards period target
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ELSE
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timing_counter <= 0; -- Reset counter for next period
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-- Update triangular wave: count up or down based on current direction
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-- This creates the classic triangular waveform shape
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IF wave_direction_up = '1' THEN
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-- Ascending phase: check if we reached maximum amplitude
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IF triangular_wave_value = (2 ** TRIANGULAR_COUNTER_LENGHT) - 1 THEN
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wave_direction_up <= '0'; -- Switch to descending phase
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triangular_wave_value <= triangular_wave_value - 1; -- Start decreasing
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ELSE
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triangular_wave_value <= triangular_wave_value + 1; -- Continue increasing
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END IF;
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ELSE
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-- Descending phase: check if we reached minimum amplitude
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IF triangular_wave_value = 0 THEN
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wave_direction_up <= '1'; -- Switch to ascending phase
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triangular_wave_value <= triangular_wave_value + 1; -- Start increasing
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ELSE
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triangular_wave_value <= triangular_wave_value - 1; -- Continue decreasing
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END IF;
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END IF;
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END IF;
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ELSE
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-- LFO_1 disabled: reset triangular wave generator to idle state
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timing_counter <= 0; -- Clear timing counter
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triangular_wave_value <= (OTHERS => '0'); -- Reset to zero amplitude
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wave_direction_up <= '1'; -- Reset to ascending direction
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END IF;
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END IF;
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END IF;
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END PROCESS triangular_wave_generator;
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-- Pipeline stage 3: Audio modulation and output control
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-- This stage applies the LFO_1 effect by multiplying audio samples with the triangular wave
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modulation_and_output : PROCESS (aclk)
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BEGIN
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IF rising_edge(aclk) THEN
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IF aresetn = '0' THEN
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-- Reset output stage to safe initial state
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m_axis_tdata <= (OTHERS => '0'); -- Clear output data
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master_valid_internal <= '0'; -- No valid output
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slave_ready_internal <= '1'; -- Ready to accept input
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ELSE
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-- Output flow control: handle backpressure from downstream modules
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IF master_valid_internal = '1' AND m_axis_tready = '0' THEN
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-- Downstream not ready: maintain current output valid state
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-- This implements proper AXI4-Stream backpressure handling
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master_valid_internal <= '1';
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ELSIF valid_flag_stage2 = '1' THEN
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-- New data available from stage 2: apply LFO_1 effect or bypass
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IF enable_flag_stage2 = '1' THEN
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-- Apply LFO_1 tremolo effect: multiply audio sample by triangular wave
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-- This creates amplitude modulation (tremolo effect)
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multiplication_result <= STD_LOGIC_VECTOR(
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resize(
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signed(audio_data_stage2) * signed('0' & triangular_wave_value),
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multiplication_result'length
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)
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);
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-- Scale down result by removing lower bits (equivalent to division by 2^TRIANGULAR_COUNTER_LENGHT)
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-- This maintains proper audio amplitude range after multiplication
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m_axis_tdata <= multiplication_result(multiplication_result'high DOWNTO TRIANGULAR_COUNTER_LENGHT);
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ELSE
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-- LFO_1 disabled: pass audio through unchanged (bypass mode)
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-- This allows seamless switching between effect and clean audio
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m_axis_tdata <= audio_data_stage2;
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END IF;
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master_valid_internal <= '1'; -- Mark output as valid
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ELSE
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-- No new data available: clear output valid flag
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master_valid_internal <= '0';
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END IF;
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-- AXI4-Stream ready signal management for proper flow control
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IF master_valid_internal = '1' AND m_axis_tready = '1' THEN
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-- Successful output handshake: ready for new input data
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slave_ready_internal <= '1';
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ELSIF s_axis_tvalid = '1' AND slave_ready_internal = '1' THEN
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-- Accepted new input: not ready until current output is consumed
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-- This prevents data loss in the pipeline
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slave_ready_internal <= '0';
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END IF;
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END IF;
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END IF;
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END PROCESS modulation_and_output;
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-- Output signal assignments
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s_axis_tready <= slave_ready_internal; -- Connect internal ready to output port
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m_axis_tvalid <= master_valid_internal; -- Connect internal valid to output port
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-- LFO_1 Effect Summary:
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-- 1. Stage 1: Calculates LFO_1 frequency based on joystick position
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-- 2. Stage 2: Generates triangular wave at calculated frequency
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-- 3. Stage 3: Multiplies audio samples by triangular wave (tremolo effect)
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--
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-- Audio Effect Characteristics:
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-- - Tremolo: Periodic amplitude modulation creates "shaking" sound
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-- - Frequency range: Approximately 0.1Hz to 10Hz (typical for audio LFO_1)
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-- - Modulation depth: Controlled by TRIANGULAR_COUNTER_LENGHT generic
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-- - Bypass capability: Clean audio passthrough when disabled
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--
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-- Pipeline Benefits:
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-- - Maintains real-time audio processing with no dropouts
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-- - Allows complex calculations without affecting audio timing
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-- - Provides proper AXI4-Stream flow control and backpressure handling
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END ARCHITECTURE Behavioral; |