Cd16d
60a8aa912d
- Created a new Block Design Archive (lab_3.bda) for LAB3, defining nodes and edges for the design. - Added a placeholder README file in the simulation directory. - Initialized a Vivado project file (lab3.xpr) with configuration settings and source files for synthesis and simulation. - Updated vhdl_ls.toml to include LAB3 source and simulation files for VHDL language server support.
31 lines
541 B
TOML
31 lines
541 B
TOML
[libraries]
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# Assign separate libraries for each project
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lab0_lib.files = [
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"LAB0/src/**/*.vhd",
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"LAB0/sim/**/*.vhd"
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]
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lab1_lib.files = [
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"LAB1/src/**/*.vhd",
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"LAB1/sim/**/*.vhd"
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]
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lab2_lib.files = [
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"LAB2/src/*.vhd",
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"LAB2/sim/**/*.vhd"
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]
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lab3_lib.files = [
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"LAB3/src/**/*.vhd",
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"LAB3/sim/**/*.vhd"
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]
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xpm.files = [
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"C:/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_VCOMP.vhd"
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]
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xpm.is_third_party = true
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unisim.files = [
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"C:/Xilinx/Vivado/2020.2/data/vhdl/src/unisims/**/*.vhd"
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]
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unisim.is_third_party = true |