50 lines
1.4 KiB
VHDL
50 lines
1.4 KiB
VHDL
--Copyright 1986-2020 Xilinx, Inc. All Rights Reserved.
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----------------------------------------------------------------------------------
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--Tool Version: Vivado v.2020.2 (win64) Build 3064766 Wed Nov 18 09:12:45 MST 2020
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--Date : Tue Apr 22 22:53:03 2025
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--Host : Davide-Samsung running 64-bit major release (build 9200)
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--Command : generate_target lab_2_wrapper.bd
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--Design : lab_2_wrapper
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--Purpose : IP block netlist
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----------------------------------------------------------------------------------
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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library UNISIM;
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use UNISIM.VCOMPONENTS.ALL;
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entity lab_2_wrapper is
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port (
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led_of : out STD_LOGIC;
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led_ok : out STD_LOGIC;
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led_uf : out STD_LOGIC;
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reset : in STD_LOGIC;
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sys_clock : in STD_LOGIC;
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usb_uart_rxd : in STD_LOGIC;
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usb_uart_txd : out STD_LOGIC
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);
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end lab_2_wrapper;
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architecture STRUCTURE of lab_2_wrapper is
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component lab_2 is
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port (
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led_of : out STD_LOGIC;
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led_ok : out STD_LOGIC;
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led_uf : out STD_LOGIC;
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sys_clock : in STD_LOGIC;
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reset : in STD_LOGIC;
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usb_uart_txd : out STD_LOGIC;
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usb_uart_rxd : in STD_LOGIC
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);
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end component lab_2;
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begin
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lab_2_i: component lab_2
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port map (
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led_of => led_of,
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led_ok => led_ok,
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led_uf => led_uf,
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reset => reset,
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sys_clock => sys_clock,
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usb_uart_rxd => usb_uart_rxd,
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usb_uart_txd => usb_uart_txd
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);
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end STRUCTURE;
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