Davide 75fb66e531 Refactor rgb2gray and divider_by_3: update signal handling, enhance state management, and improve stimulus memory for better functionality and clarity

2025-04-24 11:25:39 +02:00

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cons

Reorder reset, sys_clock and USB UART ports in lab_2_wrapper and update synthesis flow mode in lab_2.bd

2025-04-09 11:40:21 +02:00

design

Create design folder and update projects

2025-04-22 22:56:28 +02:00

ip/AXI4-Stream_UART

Add new AXI4-Stream UART IP and update .gitignore for Lab2 files

2025-03-31 18:35:29 +02:00

sim

Refactor rgb2gray and divider_by_3: update signal handling, enhance state management, and improve stimulus memory for better functionality and clarity

2025-04-24 11:25:39 +02:00

src

Refactor rgb2gray and divider_by_3: update signal handling, enhance state management, and improve stimulus memory for better functionality and clarity

2025-04-24 11:25:39 +02:00

test

Add testbench for LED blinker, enhance bram_writer with state management, and update test script for overflow/underflow handling

2025-04-17 22:55:49 +02:00

vivado

Refactor testbench for bram_writer: update description, increase image size, and enhance signal handling for improved simulation accuracy

2025-04-23 01:49:46 +02:00