399 lines
17 KiB
VHDL
399 lines
17 KiB
VHDL
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---- * ) ----
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----` ) /( ( ) ( ( ( ( ( ( ( ( ( ( ( ----
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---- ( )(_)))\ ( ))\ )\ ( )\))( )\ ( ))\ ))\ )( )\ ( )\))( ----
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----(_(_())((_) )\ ' /((_) ((_) )\ ) ((_))\((_) )\ ) /((_)/((_)(()\((_) )\ ) ((_))\ ----
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----|_ _| (_) _((_)) (_)) | __| _(_/( (()(_)(_) _(_/( (_)) (_)) ((_)(_) _(_/( (()(_) ----
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---- | | | || ' \()/ -_) | _| | ' \))/ _` | | || ' \))/ -_)/ -_) | '_|| || ' \))/ _` | ----
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---- |_| |_||_|_|_| \___| |___||_||_| \__, | |_||_||_| \___|\___| |_| |_||_||_| \__, | ----
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---- |___/ |___/ ----
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-------------------------------------------------------------------------------------------------
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-------------------------------------------------------------------------------------------------
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------------------------------------------------------------------------------------------------------------------------------------------
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------------------------------------------------------------------------------------------------------------------------------------------
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------------------------------------------------------------------------------------------------------------------------------------------
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---- _____ _ ___ __ _ _ _ __ _ ----
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---- o O O |_ _| (_) _ __ ___ | __| _ _ / _` | (_) _ _ ___ ___ _ _ (_) _ _ / _` | ----
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---- o | | | | | ' \ / -_) | _| | ' \ \__, | | | | ' \ / -_) / -_) | '_| | | | ' \ \__, | ----
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---- TS__[O] _|_|_ _|_|_ |_|_|_| \___| |___| |_||_| |___/ _|_|_ |_||_| \___| \___| _|_|_ _|_|_ |_||_| |___/ ----
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---- {======|_|"""""|_|"""""|_|"""""|_|"""""|_|"""""|_|"""""|_|"""""|_|"""""|_|"""""|_|"""""|_|"""""|_|"""""|_|"""""|_|"""""|_|"""""| ----
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----./o--000'"`-0-0-'"`-0-0-'"`-0-0-'"`-0-0-'"`-0-0-'"`-0-0-'"`-0-0-'"`-0-0-'"`-0-0-'"`-0-0-'"`-0-0-'"`-0-0-'"`-0-0-'"`-0-0-'"`-0-0-' ----
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------------------------------------------------------------------------------------------------------------------------------------------
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------------------------------------------------------------------------------------------------------------------------------------------
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-------------------------------------DESCRIPTION------------------------------------------
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------------------------------------------------------------------------------------------
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-- Bridge FT245Async to AXI4-Stream. --
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------------------------------------------------------------------------------------------
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------------------------------------------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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library xpm;
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use xpm.vcomponents.all;
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entity AXI4Stream_UART_v1_0 is
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generic (
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------------------UART PARAMETER-------------------
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UART_BAUD_RATE : positive := 115_200;
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UART_CLOCK_FREQUENCY : positive := 100_000_000; --The associated clock frequency
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----------------------------------------------------
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-- Parameters of Axi Master Bus Interface M00_AXIS_RX
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C_M00_AXIS_RX_TDATA_WIDTH : integer := 8;
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-- Parameters of Axi Slave Bus Interface S00_AXIS_TX
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C_S00_AXIS_TX_TDATA_WIDTH : integer := 8
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);
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port (
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---------Global---------
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clk_uart : IN STD_LOGIC;
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rst : IN STD_LOGIC;
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------------------------
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---------Connessioni comunicazione UART-----------
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UART_TX : OUT STD_LOGIC;
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UART_RX : IN STD_LOGIC;
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---------------------------------------------------
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---Ports of Axi Master Bus Interface M00_AXIS_RX---
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m00_axis_rx_aclk : IN STD_LOGIC;
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m00_axis_rx_aresetn : IN STD_LOGIC;
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m00_axis_rx_tvalid : OUT STD_LOGIC;
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m00_axis_rx_tdata : OUT STD_LOGIC_VECTOR(C_M00_AXIS_RX_TDATA_WIDTH-1 DOWNTO 0);
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m00_axis_rx_tready : IN STD_LOGIC;
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--------------------------------------------------
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---Ports of Axi Slave Bus Interface S00_AXIS_TX---
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s00_axis_tx_aclk : IN STD_LOGIC;
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s00_axis_tx_aresetn : IN STD_LOGIC;
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s00_axis_tx_tready : OUT STD_LOGIC;
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s00_axis_tx_tdata : IN STD_LOGIC_VECTOR(C_S00_AXIS_TX_TDATA_WIDTH-1 DOWNTO 0);
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s00_axis_tx_tvalid : IN STD_LOGIC
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--------------------------------------------------
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);
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end AXI4Stream_UART_v1_0;
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architecture arch_imp of AXI4Stream_UART_v1_0 is
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--------------------------------COMPONENTS DECLARATION-----------------------------------
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component UART_Manager is
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generic(
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UART_BAUD_RATE : positive;
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UART_CLOCK_FREQUENCY : positive --The associated clock frequency
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);
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Port (
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---------Global---------
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clk_uart : IN STD_LOGIC;
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reset : IN STD_LOGIC;
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------------------------
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---------Connessioni comunicazione UART-----------
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UART_TX : OUT STD_LOGIC;
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UART_RX : IN STD_LOGIC;
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---------------------------------------------------
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------------FIFO_DATA_RX (8bit)-------------
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FIFO_DATA_RX_rst : OUT STD_LOGIC;
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FIFO_DATA_RX_clk : OUT STD_LOGIC;
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FIFO_DATA_RX_din : OUT STD_LOGIC_VECTOR(8-1 DOWNTO 0);
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FIFO_DATA_RX_wr_en : OUT STD_LOGIC;
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FIFO_DATA_RX_full : IN STD_LOGIC;
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FIFO_DATA_RX_almost_full : IN STD_LOGIC;
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--------------------------------------------
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------------FIFO_DATA_TX (8bit)-------------
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--FIFO_DATA_RX_rst : OUT STD_LOGIC;
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FIFO_DATA_TX_clk : OUT STD_LOGIC;
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FIFO_DATA_TX_dout : IN STD_LOGIC_VECTOR(8-1 DOWNTO 0);
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FIFO_DATA_TX_rd_en : OUT STD_LOGIC;
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FIFO_DATA_TX_empty : IN STD_LOGIC;
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FIFO_DATA_TX_almost_empty : IN STD_LOGIC
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--------------------------------------------
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);
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end component UART_Manager;
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component AXI4Stream_UART_v1_0_M00_AXIS_RX is
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generic (
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-- Width of S_AXIS address bus. The slave accepts the read and write addresses of width C_M_AXIS_TDATA_WIDTH.
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C_M_AXIS_TDATA_WIDTH : integer := 8
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);
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port (
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--------------FIFO_DATA (8bit)--------------
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--FIFO_DATA_rst : OUT STD_LOGIC; Reset lo da chi scrive la FIFO
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FIFO_DATA_clk : OUT STD_LOGIC;
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FIFO_DATA_dout : IN STD_LOGIC_VECTOR(8-1 DOWNTO 0);
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FIFO_DATA_rd_en : OUT STD_LOGIC;
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FIFO_DATA_empty : IN STD_LOGIC;
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FIFO_DATA_almost_empty : IN STD_LOGIC;
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--------------------------------------------
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----------------AXI4-Stream-----------------
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-- AXI4Stream Clock
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M_AXIS_ACLK : IN STD_LOGIC;
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-- AXI4Stream Reset
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M_AXIS_ARESETN : IN STD_LOGIC;
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-- Master Stream Ports. TVALID indicates that the master is driving a valid transfer, A transfer takes place when both TVALID and TREADY are asserted.
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M_AXIS_TVALID : OUT STD_LOGIC;
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-- TDATA is the primary payload that is used to provide the data that is passing across the interface from the master.
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M_AXIS_TDATA : OUT STD_LOGIC_VECTOR(C_M_AXIS_TDATA_WIDTH-1 DOWNTO 0);
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-- TREADY indicates that the slave can accept a transfer in the current cycle.
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M_AXIS_TREADY : IN STD_LOGIC
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--------------------------------------------
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);
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end component AXI4Stream_UART_v1_0_M00_AXIS_RX;
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component AXI4Stream_UART_v1_0_S00_AXIS_TX is
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generic (
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-- AXI4Stream sink: Data Width
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C_S_AXIS_TDATA_WIDTH : integer := 8
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);
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port (
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--------------FIFO_DATA-------------
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FIFO_DATA_rst : OUT STD_LOGIC;
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FIFO_DATA_clk : OUT STD_LOGIC;
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FIFO_DATA_din : OUT STD_LOGIC_VECTOR(C_S_AXIS_TDATA_WIDTH-1 DOWNTO 0);
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FIFO_DATA_wr_en : OUT STD_LOGIC;
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FIFO_DATA_full : IN STD_LOGIC;
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FIFO_DATA_almost_full : IN STD_LOGIC;
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--------------------------------------------
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----------------AXI4-Stream-----------------
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-- AXI4Stream sink: Clock
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S_AXIS_ACLK : IN STD_LOGIC;
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-- AXI4Stream sink: Reset
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S_AXIS_ARESETN : IN STD_LOGIC;
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-- Ready to accept data in
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S_AXIS_TREADY : OUT STD_LOGIC;
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-- Data in
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S_AXIS_TDATA : IN STD_LOGIC_VECTOR(C_S_AXIS_TDATA_WIDTH-1 DOWNTO 0);
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-- Data is in valid
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S_AXIS_TVALID : IN STD_LOGIC
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--------------------------------------------
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);
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end component AXI4Stream_UART_v1_0_S00_AXIS_TX;
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-----------------------------------------------------------------------------------------
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---------------------------------------SIGNALS-------------------------------------------
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-----------------FIFO_DATA_RX-----------------
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signal FIFO_DATA_RX_rst : STD_LOGIC;
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signal FIFO_DATA_RX_wr_clk : STD_LOGIC;
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signal FIFO_DATA_RX_rd_clk : STD_LOGIC;
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signal FIFO_DATA_RX_din : STD_LOGIC_VECTOR(7 DOWNTO 0);
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signal FIFO_DATA_RX_wr_en : STD_LOGIC;
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signal FIFO_DATA_RX_rd_en : STD_LOGIC;
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signal FIFO_DATA_RX_dout : STD_LOGIC_VECTOR(7 DOWNTO 0);
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signal FIFO_DATA_RX_full : STD_LOGIC;
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signal FIFO_DATA_RX_almost_full : STD_LOGIC;
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signal FIFO_DATA_RX_empty : STD_LOGIC;
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signal FIFO_DATA_RX_almost_empty : STD_LOGIC;
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----------------------------------------------
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-----------------FIFO_DATA_TX-----------------
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signal FIFO_DATA_TX_rst : STD_LOGIC;
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signal FIFO_DATA_TX_wr_clk : STD_LOGIC;
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signal FIFO_DATA_TX_rd_clk : STD_LOGIC;
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signal FIFO_DATA_TX_din : STD_LOGIC_VECTOR(7 DOWNTO 0);
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signal FIFO_DATA_TX_wr_en : STD_LOGIC;
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signal FIFO_DATA_TX_rd_en : STD_LOGIC;
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signal FIFO_DATA_TX_dout : STD_LOGIC_VECTOR(7 DOWNTO 0);
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signal FIFO_DATA_TX_full : STD_LOGIC;
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signal FIFO_DATA_TX_almost_full : STD_LOGIC;
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signal FIFO_DATA_TX_empty : STD_LOGIC;
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signal FIFO_DATA_TX_almost_empty : STD_LOGIC;
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----------------------------------------------
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-----------------------------------------------------------------------------------------
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begin
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-----------------------MODULE INSTANTIATION-------------------------
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AXI4Stream_UART_v1_0_S00_AXIS_TX_inst : AXI4Stream_UART_v1_0_S00_AXIS_TX
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generic map(
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-- AXI4Stream sink: Data Width
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C_S_AXIS_TDATA_WIDTH => C_S00_AXIS_TX_TDATA_WIDTH
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)
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port map(
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--------------FIFO_DATA-------------
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FIFO_DATA_rst => FIFO_DATA_TX_rst,
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FIFO_DATA_clk => FIFO_DATA_TX_wr_clk,
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FIFO_DATA_din => FIFO_DATA_TX_din,
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FIFO_DATA_wr_en => FIFO_DATA_TX_wr_en,
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FIFO_DATA_full => FIFO_DATA_TX_full,
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FIFO_DATA_almost_full => FIFO_DATA_TX_almost_full,
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--------------------------------------------
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----------------AXI4-Stream-----------------
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-- AXI4Stream sink: Clock
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S_AXIS_ACLK => s00_axis_tx_aclk,
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-- AXI4Stream sink: Reset
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S_AXIS_ARESETN => s00_axis_tx_aresetn,
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-- Ready to accept data in
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S_AXIS_TREADY => s00_axis_tx_tready,
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-- Data in
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S_AXIS_TDATA => s00_axis_tx_tdata,
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-- Data is in valid
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S_AXIS_TVALID => s00_axis_tx_tvalid
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--------------------------------------------
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);
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-- xpm_fifo_async: Asynchronous FIFO
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-- Xilinx Parameterized Macro, Version 2017.3
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FIFO_DATA_TX : xpm_fifo_async
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generic map (
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FIFO_MEMORY_TYPE => "block", --string; "auto", "block", "distributed", or "ultra";
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FIFO_WRITE_DEPTH => 2048, --positive integer;
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RELATED_CLOCKS => 0, --positive integer; 0 or 1;
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WRITE_DATA_WIDTH => 8, --positive integer;
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WR_DATA_COUNT_WIDTH => 1, --positive integer;
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READ_MODE => "fwft", --string; "std" or "fwft";
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FIFO_READ_LATENCY => 0, --positive integer;
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--FULL_RESET_VALUE => 0, --positive integer; 0 or 1;
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READ_DATA_WIDTH => 8, --positive integer;
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RD_DATA_COUNT_WIDTH => 1, --positive integer;
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CDC_SYNC_STAGES => 2, --positive integer;
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ECC_MODE => "no_ecc", --string; "no_ecc" or "en_ecc";
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--PROG_FULL_THRESH => 10, --positive integer
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--PROG_EMPTY_THRESH => 10, --positive integer
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--DOUT_RESET_VALUE => "0", --string
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WAKEUP_TIME => 0, --positive integer; 0 or 2;
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USE_ADV_FEATURES => "0808" --string; "0000" to "1F1F"; 0808 = almost_full and almost_empty
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)
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port map (
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wr_clk => FIFO_DATA_TX_wr_clk,
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wr_en => FIFO_DATA_TX_wr_en,
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din => FIFO_DATA_TX_din,
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full => FIFO_DATA_TX_full,
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overflow => open,
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wr_rst_busy => open,
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sleep => '0',
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rst => FIFO_DATA_TX_rst,
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rd_clk => FIFO_DATA_TX_rd_clk,
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rd_en => FIFO_DATA_TX_rd_en,
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dout => FIFO_DATA_TX_dout,
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empty => FIFO_DATA_TX_empty,
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underflow => open,
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rd_rst_busy => open,
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injectsbiterr => '0',
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injectdbiterr => '0',
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almost_full => FIFO_DATA_TX_almost_full,
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almost_empty => FIFO_DATA_TX_almost_empty
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);
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UART_Manager_inst : UART_Manager
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Generic map(
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UART_BAUD_RATE => UART_BAUD_RATE,
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UART_CLOCK_FREQUENCY => UART_CLOCK_FREQUENCY
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)
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Port map(
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---------Global---------
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clk_uart => clk_uart,
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reset => rst,
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------------------------
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---------Connessioni comunicazione UART-----------
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UART_TX => UART_TX,
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UART_RX => UART_RX,
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---------------------------------------------------
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------------FIFO_DATA_RX (8bit)-------------
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FIFO_DATA_RX_rst => FIFO_DATA_RX_rst,
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FIFO_DATA_RX_clk => FIFO_DATA_RX_wr_clk,
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FIFO_DATA_RX_din => FIFO_DATA_RX_din,
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FIFO_DATA_RX_wr_en => FIFO_DATA_RX_wr_en,
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FIFO_DATA_RX_full => FIFO_DATA_RX_full,
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FIFO_DATA_RX_almost_full => FIFO_DATA_RX_almost_full,
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--------------------------------------------
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------------FIFO_DATA_TX (8bit)-------------
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FIFO_DATA_TX_clk => FIFO_DATA_TX_rd_clk,
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FIFO_DATA_TX_dout => FIFO_DATA_TX_dout,
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FIFO_DATA_TX_rd_en => FIFO_DATA_TX_rd_en,
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FIFO_DATA_TX_empty => FIFO_DATA_TX_empty,
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FIFO_DATA_TX_almost_empty => FIFO_DATA_TX_almost_empty
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--------------------------------------------
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);
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-- xpm_fifo_async: Asynchronous FIFO
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-- Xilinx Parameterized Macro, Version 2017.3
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FIFO_DATA_RX : xpm_fifo_async
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generic map (
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FIFO_MEMORY_TYPE => "block", --string; "auto", "block", "distributed", or "ultra";
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FIFO_WRITE_DEPTH => 2048, --positive integer;
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RELATED_CLOCKS => 0, --positive integer; 0 or 1;
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WRITE_DATA_WIDTH => 8, --positive integer;
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WR_DATA_COUNT_WIDTH => 1, --positive integer;
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READ_MODE => "fwft", --string; "std" or "fwft";
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FIFO_READ_LATENCY => 0, --positive integer;
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--FULL_RESET_VALUE => 0, --positive integer; 0 or 1;
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READ_DATA_WIDTH => 8, --positive integer;
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RD_DATA_COUNT_WIDTH => 1, --positive integer;
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CDC_SYNC_STAGES => 2, --positive integer;
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ECC_MODE => "no_ecc", --string; "no_ecc" or "en_ecc";
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--PROG_FULL_THRESH => 10, --positive integer
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--PROG_EMPTY_THRESH => 10, --positive integer
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--DOUT_RESET_VALUE => "0", --string
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WAKEUP_TIME => 0, --positive integer; 0 or 2;
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USE_ADV_FEATURES => "0808" --string; "0000" to "1F1F"; 0808 = almost_full and almost_empty
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)
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port map (
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wr_clk => FIFO_DATA_RX_wr_clk,
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wr_en => FIFO_DATA_RX_wr_en,
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din => FIFO_DATA_RX_din,
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full => FIFO_DATA_RX_full,
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overflow => open,
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wr_rst_busy => open,
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sleep => '0',
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rst => FIFO_DATA_RX_rst,
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rd_clk => FIFO_DATA_RX_rd_clk,
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rd_en => FIFO_DATA_RX_rd_en,
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dout => FIFO_DATA_RX_dout,
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empty => FIFO_DATA_RX_empty,
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underflow => open,
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rd_rst_busy => open,
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injectsbiterr => '0',
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injectdbiterr => '0',
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almost_full => FIFO_DATA_RX_almost_full,
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almost_empty => FIFO_DATA_RX_almost_empty
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);
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AXI4Stream_UART_v1_0_M00_AXIS_RX_inst : AXI4Stream_UART_v1_0_M00_AXIS_RX
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generic map(
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-- Width of S_AXIS address bus. The slave accepts the read and write addresses of width C_M_AXIS_TDATA_WIDTH.
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C_M_AXIS_TDATA_WIDTH => C_M00_AXIS_RX_TDATA_WIDTH
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)
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port map(
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--------------FIFO_DATA (8bit)--------------
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FIFO_DATA_clk => FIFO_DATA_RX_rd_clk,
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FIFO_DATA_dout => FIFO_DATA_RX_dout,
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FIFO_DATA_rd_en => FIFO_DATA_RX_rd_en,
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FIFO_DATA_empty => FIFO_DATA_RX_empty,
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FIFO_DATA_almost_empty => FIFO_DATA_RX_almost_empty,
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--------------------------------------------
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----------------AXI4-Stream-----------------
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-- AXI4Stream Clock
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M_AXIS_ACLK => m00_axis_rx_aclk,
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-- AXI4Stream Reset
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M_AXIS_ARESETN => m00_axis_rx_aresetn,
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-- Master Stream Ports. TVALID indicates that the master is driving a valid transfer, A transfer takes place when both TVALID and TREADY are asserted.
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M_AXIS_TVALID => m00_axis_rx_tvalid,
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-- TDATA is the primary payload that is used to provide the data that is passing across the interface from the master.
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M_AXIS_TDATA => m00_axis_rx_tdata,
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-- TREADY indicates that the slave can accept a transfer in the current cycle.
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M_AXIS_TREADY => m00_axis_rx_tready
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--------------------------------------------
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);
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--------------------------------------------------------------------
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end arch_imp;
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