142 lines
4.4 KiB
VHDL
142 lines
4.4 KiB
VHDL
-- filepath: c:\DESD\LAB3\sim\tb_moving_average.vhd
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LIBRARY ieee;
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USE ieee.std_logic_1164.ALL;
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USE ieee.numeric_std.ALL;
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ENTITY tb_moving_average IS
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END tb_moving_average;
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ARCHITECTURE sim OF tb_moving_average IS
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CONSTANT TDATA_WIDTH : INTEGER := 24;
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CONSTANT FILTER_ORDER_PWR : INTEGER := 5;
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SIGNAL aclk : STD_LOGIC := '0';
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SIGNAL aresetn : STD_LOGIC := '0';
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SIGNAL s_axis_tvalid : STD_LOGIC := '0';
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SIGNAL s_axis_tdata : STD_LOGIC_VECTOR(TDATA_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
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SIGNAL s_axis_tlast : STD_LOGIC := '0';
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SIGNAL s_axis_tready : STD_LOGIC;
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SIGNAL m_axis_tvalid : STD_LOGIC;
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SIGNAL m_axis_tdata : STD_LOGIC_VECTOR(TDATA_WIDTH-1 DOWNTO 0);
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SIGNAL m_axis_tlast : STD_LOGIC;
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SIGNAL m_axis_tready : STD_LOGIC := '1';
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SIGNAL enable_filter : STD_LOGIC := '0';
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-- DUT
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COMPONENT moving_average_filter_en
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GENERIC (
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FILTER_ORDER_POWER : INTEGER := 5;
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TDATA_WIDTH : POSITIVE := 24
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);
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PORT (
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aclk : IN STD_LOGIC;
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aresetn : IN STD_LOGIC;
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s_axis_tvalid : IN STD_LOGIC;
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s_axis_tdata : IN STD_LOGIC_VECTOR(TDATA_WIDTH-1 DOWNTO 0);
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s_axis_tlast : IN STD_LOGIC;
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s_axis_tready : OUT STD_LOGIC;
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m_axis_tvalid : OUT STD_LOGIC;
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m_axis_tdata : OUT STD_LOGIC_VECTOR(TDATA_WIDTH-1 DOWNTO 0);
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m_axis_tlast : OUT STD_LOGIC;
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m_axis_tready : IN STD_LOGIC;
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enable_filter : IN STD_LOGIC
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);
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END COMPONENT;
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BEGIN
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-- Clock generation
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clk_proc : PROCESS
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BEGIN
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aclk <= '0';
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WAIT FOR 5 ns;
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aclk <= '1';
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WAIT FOR 5 ns;
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END PROCESS;
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-- DUT instantiation
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dut: moving_average_filter_en
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GENERIC MAP (
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FILTER_ORDER_POWER => FILTER_ORDER_PWR,
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TDATA_WIDTH => TDATA_WIDTH
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)
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PORT MAP (
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aclk => aclk,
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aresetn => aresetn,
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s_axis_tvalid => s_axis_tvalid,
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s_axis_tdata => s_axis_tdata,
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s_axis_tlast => s_axis_tlast,
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s_axis_tready => s_axis_tready,
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m_axis_tvalid => m_axis_tvalid,
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m_axis_tdata => m_axis_tdata,
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m_axis_tlast => m_axis_tlast,
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m_axis_tready => m_axis_tready,
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enable_filter => enable_filter
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);
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-- Stimulus process
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stim_proc : PROCESS
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BEGIN
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-- Reset
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aresetn <= '0';
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WAIT FOR 20 ns;
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aresetn <= '1';
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WAIT FOR 10 ns;
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-- Test All Pass (enable_filter = '0')
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enable_filter <= '0';
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FOR i IN 0 TO 7 LOOP
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-- SX sample
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s_axis_tdata <= std_logic_vector(to_signed(i*100, TDATA_WIDTH));
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s_axis_tvalid <= '1';
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s_axis_tlast <= '0';
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WAIT UNTIL rising_edge(aclk);
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WHILE s_axis_tready /= '1' LOOP
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WAIT UNTIL rising_edge(aclk);
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END LOOP;
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s_axis_tvalid <= '0';
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-- DX sample (tlast high)
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s_axis_tdata <= std_logic_vector(to_signed(i*100+50, TDATA_WIDTH));
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s_axis_tvalid <= '1';
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s_axis_tlast <= '1';
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WAIT UNTIL rising_edge(aclk);
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WHILE s_axis_tready /= '1' LOOP
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WAIT UNTIL rising_edge(aclk);
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END LOOP;
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s_axis_tvalid <= '0';
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END LOOP;
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-- Test Moving Average (enable_filter = '1')
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enable_filter <= '1';
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FOR i IN 0 TO 7 LOOP
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-- SX sample
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s_axis_tdata <= std_logic_vector(to_signed(i*100, TDATA_WIDTH));
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s_axis_tvalid <= '1';
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s_axis_tlast <= '0';
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WAIT UNTIL rising_edge(aclk);
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WHILE s_axis_tready /= '1' LOOP
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WAIT UNTIL rising_edge(aclk);
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END LOOP;
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s_axis_tvalid <= '0';
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-- DX sample (tlast high)
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s_axis_tdata <= std_logic_vector(to_signed(i*100+50, TDATA_WIDTH));
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s_axis_tvalid <= '1';
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s_axis_tlast <= '1';
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WAIT UNTIL rising_edge(aclk);
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WHILE s_axis_tready /= '1' LOOP
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WAIT UNTIL rising_edge(aclk);
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END LOOP;
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s_axis_tvalid <= '0';
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END LOOP;
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-- End simulation
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WAIT FOR 50 ns;
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END PROCESS;
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END sim; |