Cd16d
86bf16abaf
- Updated lab_3.bda to correct node connections and attributes. - Enhanced LFO.vhd with improved signal handling and clamping logic. - Modified all_pass_filter.vhd to ensure proper data transfer. - Adjusted balance_controller.vhd to incorporate reset logic in signal assignments. - Cleaned up effect_selector.vhd by removing unnecessary assignments. - Improved led_level_controller.vhd for better readability and functionality. - Refined moving_average_filter_en.vhd to streamline AXIS assignments. - Enhanced mute_controller.vhd for clearer data flow management. - Updated lab3.xpr to correct file paths and simulation settings.
144 lines
4.2 KiB
VHDL
144 lines
4.2 KiB
VHDL
--Copyright 1986-2020 Xilinx, Inc. All Rights Reserved.
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----------------------------------------------------------------------------------
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--Tool Version: Vivado v.2020.2 (win64) Build 3064766 Wed Nov 18 09:12:45 MST 2020
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--Date : Fri May 23 15:41:37 2025
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--Host : Davide-Samsung running 64-bit major release (build 9200)
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--Command : generate_target lab_3_wrapper.bd
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--Design : lab_3_wrapper
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--Purpose : IP block netlist
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----------------------------------------------------------------------------------
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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library UNISIM;
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use UNISIM.VCOMPONENTS.ALL;
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entity lab_3_wrapper is
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port (
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LED : out STD_LOGIC_VECTOR ( 15 downto 0 );
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SPI_M_0_io0_io : inout STD_LOGIC;
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SPI_M_0_io1_io : inout STD_LOGIC;
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SPI_M_0_sck_io : inout STD_LOGIC;
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SPI_M_0_ss_io : inout STD_LOGIC;
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effect : in STD_LOGIC;
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lfo_enable : in STD_LOGIC;
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reset : in STD_LOGIC;
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rx_lrck_0 : out STD_LOGIC;
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rx_mclk_0 : out STD_LOGIC;
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rx_sclk_0 : out STD_LOGIC;
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rx_sdin_0 : in STD_LOGIC;
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sys_clock : in STD_LOGIC;
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tx_lrck_0 : out STD_LOGIC;
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tx_mclk_0 : out STD_LOGIC;
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tx_sclk_0 : out STD_LOGIC;
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tx_sdout_0 : out STD_LOGIC
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);
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end lab_3_wrapper;
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architecture STRUCTURE of lab_3_wrapper is
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component lab_3 is
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port (
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sys_clock : in STD_LOGIC;
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reset : in STD_LOGIC;
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tx_lrck_0 : out STD_LOGIC;
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rx_sdin_0 : in STD_LOGIC;
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rx_sclk_0 : out STD_LOGIC;
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rx_lrck_0 : out STD_LOGIC;
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rx_mclk_0 : out STD_LOGIC;
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tx_sdout_0 : out STD_LOGIC;
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tx_sclk_0 : out STD_LOGIC;
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tx_mclk_0 : out STD_LOGIC;
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lfo_enable : in STD_LOGIC;
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effect : in STD_LOGIC;
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SPI_M_0_sck_t : out STD_LOGIC;
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SPI_M_0_io1_o : out STD_LOGIC;
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SPI_M_0_ss_t : out STD_LOGIC;
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SPI_M_0_io0_o : out STD_LOGIC;
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SPI_M_0_sck_i : in STD_LOGIC;
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SPI_M_0_ss_o : out STD_LOGIC;
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SPI_M_0_io0_t : out STD_LOGIC;
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SPI_M_0_io1_t : out STD_LOGIC;
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SPI_M_0_sck_o : out STD_LOGIC;
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SPI_M_0_ss_i : in STD_LOGIC;
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SPI_M_0_io1_i : in STD_LOGIC;
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SPI_M_0_io0_i : in STD_LOGIC;
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LED : out STD_LOGIC_VECTOR ( 15 downto 0 )
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);
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end component lab_3;
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component IOBUF is
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port (
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I : in STD_LOGIC;
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O : out STD_LOGIC;
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T : in STD_LOGIC;
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IO : inout STD_LOGIC
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);
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end component IOBUF;
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signal SPI_M_0_io0_i : STD_LOGIC;
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signal SPI_M_0_io0_o : STD_LOGIC;
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signal SPI_M_0_io0_t : STD_LOGIC;
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signal SPI_M_0_io1_i : STD_LOGIC;
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signal SPI_M_0_io1_o : STD_LOGIC;
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signal SPI_M_0_io1_t : STD_LOGIC;
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signal SPI_M_0_sck_i : STD_LOGIC;
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signal SPI_M_0_sck_o : STD_LOGIC;
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signal SPI_M_0_sck_t : STD_LOGIC;
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signal SPI_M_0_ss_i : STD_LOGIC;
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signal SPI_M_0_ss_o : STD_LOGIC;
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signal SPI_M_0_ss_t : STD_LOGIC;
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begin
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SPI_M_0_io0_iobuf: component IOBUF
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port map (
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I => SPI_M_0_io0_o,
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IO => SPI_M_0_io0_io,
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O => SPI_M_0_io0_i,
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T => SPI_M_0_io0_t
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);
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SPI_M_0_io1_iobuf: component IOBUF
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port map (
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I => SPI_M_0_io1_o,
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IO => SPI_M_0_io1_io,
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O => SPI_M_0_io1_i,
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T => SPI_M_0_io1_t
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);
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SPI_M_0_sck_iobuf: component IOBUF
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port map (
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I => SPI_M_0_sck_o,
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IO => SPI_M_0_sck_io,
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O => SPI_M_0_sck_i,
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T => SPI_M_0_sck_t
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);
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SPI_M_0_ss_iobuf: component IOBUF
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port map (
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I => SPI_M_0_ss_o,
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IO => SPI_M_0_ss_io,
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O => SPI_M_0_ss_i,
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T => SPI_M_0_ss_t
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);
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lab_3_i: component lab_3
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port map (
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LED(15 downto 0) => LED(15 downto 0),
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SPI_M_0_io0_i => SPI_M_0_io0_i,
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SPI_M_0_io0_o => SPI_M_0_io0_o,
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SPI_M_0_io0_t => SPI_M_0_io0_t,
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SPI_M_0_io1_i => SPI_M_0_io1_i,
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SPI_M_0_io1_o => SPI_M_0_io1_o,
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SPI_M_0_io1_t => SPI_M_0_io1_t,
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SPI_M_0_sck_i => SPI_M_0_sck_i,
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SPI_M_0_sck_o => SPI_M_0_sck_o,
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SPI_M_0_sck_t => SPI_M_0_sck_t,
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SPI_M_0_ss_i => SPI_M_0_ss_i,
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SPI_M_0_ss_o => SPI_M_0_ss_o,
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SPI_M_0_ss_t => SPI_M_0_ss_t,
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effect => effect,
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lfo_enable => lfo_enable,
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reset => reset,
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rx_lrck_0 => rx_lrck_0,
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rx_mclk_0 => rx_mclk_0,
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rx_sclk_0 => rx_sclk_0,
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rx_sdin_0 => rx_sdin_0,
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sys_clock => sys_clock,
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tx_lrck_0 => tx_lrck_0,
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tx_mclk_0 => tx_mclk_0,
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tx_sclk_0 => tx_sclk_0,
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tx_sdout_0 => tx_sdout_0
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);
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end STRUCTURE;
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