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Refactor and optimize various components in LAB3 design

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- Updated lab_3.bda to correct node connections and attributes.
- Enhanced LFO.vhd with improved signal handling and clamping logic.
- Modified all_pass_filter.vhd to ensure proper data transfer.
- Adjusted balance_controller.vhd to incorporate reset logic in signal assignments.
- Cleaned up effect_selector.vhd by removing unnecessary assignments.
- Improved led_level_controller.vhd for better readability and functionality.
- Refined moving_average_filter_en.vhd to streamline AXIS assignments.
- Enhanced mute_controller.vhd for clearer data flow management.
- Updated lab3.xpr to correct file paths and simulation settings.
This commit is contained in:
Davide Cavagnola
2025-05-23 15:53:03 +02:00
parent 6cb0e4095e
commit 86bf16abaf
12 changed files with 1085 additions and 1028 deletions
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64
LAB3/cons/io.xdc
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@@ -1,3 +1,21 @@
# pmod I2S2 connected to JB
set_property IOSTANDARD LVCMOS33 [get_ports rx_lrck_0]
set_property IOSTANDARD LVCMOS33 [get_ports rx_mclk_0]
set_property IOSTANDARD LVCMOS33 [get_ports rx_sclk_0]
set_property IOSTANDARD LVCMOS33 [get_ports rx_sdin_0]
set_property IOSTANDARD LVCMOS33 [get_ports tx_lrck_0]
set_property IOSTANDARD LVCMOS33 [get_ports tx_mclk_0]
set_property IOSTANDARD LVCMOS33 [get_ports tx_sclk_0]
set_property IOSTANDARD LVCMOS33 [get_ports tx_sdout_0]
set_property PACKAGE_PIN A14 [get_ports tx_mclk_0]
set_property PACKAGE_PIN A16 [get_ports tx_lrck_0]
set_property PACKAGE_PIN B15 [get_ports tx_sclk_0]
set_property PACKAGE_PIN B16 [get_ports tx_sdout_0]
set_property PACKAGE_PIN A15 [get_ports rx_mclk_0]
set_property PACKAGE_PIN A17 [get_ports rx_lrck_0]
set_property PACKAGE_PIN C15 [get_ports rx_sclk_0]
set_property PACKAGE_PIN C16 [get_ports rx_sdin_0]
# SPI connected to JA, top row
set_property PACKAGE_PIN J1 [get_ports SPI_M_0_ss_io]
set_property PACKAGE_PIN G2 [get_ports SPI_M_0_sck_io]
@@ -7,7 +25,45 @@ set_property IOSTANDARD LVCMOS33 [get_ports SPI_M_0_io0_io]
set_property IOSTANDARD LVCMOS33 [get_ports SPI_M_0_io1_io]
set_property IOSTANDARD LVCMOS33 [get_ports SPI_M_0_sck_io]
set_property IOSTANDARD LVCMOS33 [get_ports SPI_M_0_ss_io]
set_property OFFCHIP_TERM NONE [get_ports SPI_M_0_io0_io]
set_property OFFCHIP_TERM NONE [get_ports SPI_M_0_io1_io]
set_property OFFCHIP_TERM NONE [get_ports SPI_M_0_sck_io]
set_property OFFCHIP_TERM NONE [get_ports SPI_M_0_ss_io]
# Button
set_property IOSTANDARD LVCMOS33 [get_ports effect]
set_property PACKAGE_PIN T18 [get_ports effect]
# Switch
set_property IOSTANDARD LVCMOS33 [get_ports {lfo_enable}]
set_property PACKAGE_PIN V17 [get_ports {lfo_enable}]
# LEDs
set_property PACKAGE_PIN U16 [get_ports {LED[0]}]
set_property IOSTANDARD LVCMOS33 [get_ports {LED[0]}]
set_property PACKAGE_PIN E19 [get_ports {LED[1]}]
set_property IOSTANDARD LVCMOS33 [get_ports {LED[1]}]
set_property PACKAGE_PIN U19 [get_ports {LED[2]}]
set_property IOSTANDARD LVCMOS33 [get_ports {LED[2]}]
set_property PACKAGE_PIN V19 [get_ports {LED[3]}]
set_property IOSTANDARD LVCMOS33 [get_ports {LED[3]}]
set_property PACKAGE_PIN W18 [get_ports {LED[4]}]
set_property IOSTANDARD LVCMOS33 [get_ports {LED[4]}]
set_property PACKAGE_PIN U15 [get_ports {LED[5]}]
set_property IOSTANDARD LVCMOS33 [get_ports {LED[5]}]
set_property PACKAGE_PIN U14 [get_ports {LED[6]}]
set_property IOSTANDARD LVCMOS33 [get_ports {LED[6]}]
set_property PACKAGE_PIN V14 [get_ports {LED[7]}]
set_property IOSTANDARD LVCMOS33 [get_ports {LED[7]}]
set_property PACKAGE_PIN V13 [get_ports {LED[8]}]
set_property IOSTANDARD LVCMOS33 [get_ports {LED[8]}]
set_property PACKAGE_PIN V3 [get_ports {LED[9]}]
set_property IOSTANDARD LVCMOS33 [get_ports {LED[9]}]
set_property PACKAGE_PIN W3 [get_ports {LED[10]}]
set_property IOSTANDARD LVCMOS33 [get_ports {LED[10]}]
set_property PACKAGE_PIN U3 [get_ports {LED[11]}]
set_property IOSTANDARD LVCMOS33 [get_ports {LED[11]}]
set_property PACKAGE_PIN P3 [get_ports {LED[12]}]
set_property IOSTANDARD LVCMOS33 [get_ports {LED[12]}]
set_property PACKAGE_PIN N3 [get_ports {LED[13]}]
set_property IOSTANDARD LVCMOS33 [get_ports {LED[13]}]
set_property PACKAGE_PIN P1 [get_ports {LED[14]}]
set_property IOSTANDARD LVCMOS33 [get_ports {LED[14]}]
set_property PACKAGE_PIN L1 [get_ports {LED[15]}]
set_property IOSTANDARD LVCMOS33 [get_ports {LED[15]}]

6
LAB3/design/lab_3/hdl/lab_3_wrapper.vhd
View File

@@ -1,7 +1,7 @@
--Copyright 1986-2020 Xilinx, Inc. All Rights Reserved.
----------------------------------------------------------------------------------
--Tool Version: Vivado v.2020.2 (win64) Build 3064766 Wed Nov 18 09:12:45 MST 2020
--Date : Mon May 19 16:34:49 2025
--Date : Fri May 23 15:41:37 2025
--Host : Davide-Samsung running 64-bit major release (build 9200)
--Command : generate_target lab_3_wrapper.bd
--Design : lab_3_wrapper
@@ -48,7 +48,6 @@ architecture STRUCTURE of lab_3_wrapper is
tx_mclk_0 : out STD_LOGIC;
lfo_enable : in STD_LOGIC;
effect : in STD_LOGIC;
LED : out STD_LOGIC_VECTOR ( 15 downto 0 );
SPI_M_0_sck_t : out STD_LOGIC;
SPI_M_0_io1_o : out STD_LOGIC;
SPI_M_0_ss_t : out STD_LOGIC;
@@ -60,7 +59,8 @@ architecture STRUCTURE of lab_3_wrapper is
SPI_M_0_sck_o : out STD_LOGIC;
SPI_M_0_ss_i : in STD_LOGIC;
SPI_M_0_io1_i : in STD_LOGIC;
SPI_M_0_io0_i : in STD_LOGIC
SPI_M_0_io0_i : in STD_LOGIC;
LED : out STD_LOGIC_VECTOR ( 15 downto 0 )
);
end component lab_3;
component IOBUF is

1710
LAB3/design/lab_3/lab_3.bd
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File diff suppressed because it is too large Load Diff

12
LAB3/design/lab_3/lab_3.bda
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@@ -21,22 +21,22 @@
<key attr.name="vert_type" attr.type="string" for="node" id="VT"/>
<graph edgedefault="undirected" id="G" parse.edgeids="canonical" parse.nodeids="canonical" parse.order="nodesfirst">
<node id="n0">
<data key="VM">lab_3</data>
<data key="VT">BC</data>
</node>
<node id="n1">
<data key="TU">active</data>
<data key="VH">2</data>
<data key="VT">PM</data>
</node>
<node id="n1">
<data key="VM">lab_3</data>
<data key="VT">BC</data>
</node>
<node id="n2">
<data key="VH">2</data>
<data key="VM">lab_3</data>
<data key="VT">VR</data>
</node>
<edge id="e0" source="n1" target="n2">
<edge id="e0" source="n0" target="n2">
</edge>
<edge id="e1" source="n2" target="n0">
<edge id="e1" source="n2" target="n1">
</edge>
</graph>
</graphml>

50
LAB3/src/LFO.vhd
View File

@@ -37,22 +37,23 @@ ARCHITECTURE Behavioral OF LFO IS
CONSTANT LFO_COUNTER_BASE_PERIOD_US : INTEGER := 1000; -- 1ms
CONSTANT ADJUSTMENT_FACTOR : INTEGER := 90;
CONSTANT JSTK_CENTER_VALUE : INTEGER := 2 ** (JOYSTICK_LENGHT - 1);
CONSTANT LFO_COUNTER_BASE_CLK_CYCLES : INTEGER := LFO_COUNTER_BASE_PERIOD_US * 1000 / CLK_PERIOD_NS;
CONSTANT JSTK_CENTER_VALUE : INTEGER := 2 ** (JOYSTICK_LENGHT - 1); -- 512 for 10 bits
CONSTANT LFO_COUNTER_BASE_CLK_CYCLES : INTEGER := LFO_COUNTER_BASE_PERIOD_US * 1000 / CLK_PERIOD_NS; -- 1ms = 100_000 clk cycles
CONSTANT LFO_CLK_CYCLES_MIN : INTEGER := LFO_COUNTER_BASE_CLK_CYCLES - ADJUSTMENT_FACTOR * (2 ** (JOYSTICK_LENGHT - 1)); -- 53_920 clk cycles
CONSTANT LFO_CLK_CYCLES_MAX : INTEGER := LFO_COUNTER_BASE_CLK_CYCLES + ADJUSTMENT_FACTOR * (2 ** (JOYSTICK_LENGHT - 1) - 1); -- 145_990 clk cycles
SIGNAL step_clk_cycles : INTEGER := LFO_COUNTER_BASE_CLK_CYCLES;
SIGNAL step_counter : INTEGER RANGE 0 TO 2 ** TRIANGULAR_COUNTER_LENGHT - 1 := 0;
SIGNAL tri_counter : signed(TRIANGULAR_COUNTER_LENGHT - 1 DOWNTO 0) := (OTHERS => '0');
SIGNAL step_clk_cycles : INTEGER RANGE LFO_CLK_CYCLES_MIN TO LFO_CLK_CYCLES_MAX := LFO_COUNTER_BASE_CLK_CYCLES;
SIGNAL step_counter : INTEGER RANGE 0 TO LFO_CLK_CYCLES_MAX := 0;
SIGNAL tri_counter : SIGNED(TRIANGULAR_COUNTER_LENGHT - 1 DOWNTO 0) := (OTHERS => '0');
SIGNAL direction_up : STD_LOGIC := '1';
SIGNAL s_axis_tready_int : STD_LOGIC := '0';
SIGNAL m_axis_tvalid_int : STD_LOGIC := '0';
BEGIN
-- Output assignments
s_axis_tready <= s_axis_tready_int;
m_axis_tvalid <= m_axis_tvalid_int;
-- Assigning the output signals
m_axis_tvalid <= m_axis_tvalid_int;
s_axis_tready <= (m_axis_tready OR NOT m_axis_tvalid_int) AND aresetn;
-- Optimized single process for LFO step and triangular waveform generation
PROCESS (aclk)
@@ -60,24 +61,21 @@ BEGIN
IF rising_edge(aclk) THEN
IF aresetn = '0' THEN
step_clk_cycles <= LFO_COUNTER_BASE_CLK_CYCLES;
step_counter <= 0;
tri_counter <= (OTHERS => '0');
direction_up <= '1';
ELSE
-- Clamp step_clk_cycles to a minimum of 1 to avoid negative or zero values
IF (LFO_COUNTER_BASE_CLK_CYCLES - ADJUSTMENT_FACTOR * to_integer(JSTK_CENTER_VALUE - unsigned(lfo_period))) < 1 THEN
step_clk_cycles <= 1;
ELSE
step_clk_cycles <= LFO_COUNTER_BASE_CLK_CYCLES - ADJUSTMENT_FACTOR * to_integer(JSTK_CENTER_VALUE - unsigned(lfo_period));
END IF;
-- Set the step_clk_cycles based on the joystick input
step_clk_cycles <= LFO_COUNTER_BASE_CLK_CYCLES - ADJUSTMENT_FACTOR * (JSTK_CENTER_VALUE - to_integer(unsigned(lfo_period)));
IF lfo_enable = '1' THEN
IF step_counter >= step_clk_cycles THEN
step_counter <= 0;
IF tri_counter = 2 ** TRIANGULAR_COUNTER_LENGHT - 2 THEN
IF tri_counter = (2 ** TRIANGULAR_COUNTER_LENGHT) - 2 THEN
direction_up <= '0';
ELSIF tri_counter = 1 THEN
@@ -107,14 +105,12 @@ BEGIN
END PROCESS;
-- Handshake logic for the AXIS interface
PROCESS (aclk)
AXIS: PROCESS (aclk)
BEGIN
IF rising_edge(aclk) THEN
IF aresetn = '0' THEN
s_axis_tready_int <= '0';
m_axis_tvalid_int <= '0';
m_axis_tdata <= (OTHERS => '0');
m_axis_tlast <= '0';
ELSE
@@ -123,12 +119,15 @@ BEGIN
m_axis_tvalid_int <= '0';
END IF;
IF s_axis_tvalid = '1' AND (m_axis_tvalid_int = '0' OR m_axis_tready = '1') THEN
IF s_axis_tvalid = '1' AND m_axis_tready = '1' THEN
IF lfo_enable = '1' THEN
m_axis_tdata <= STD_LOGIC_VECTOR(
resize(
signed(s_axis_tdata) * tri_counter,
m_axis_tdata'LENGTH
shift_right(
signed(s_axis_tdata) * tri_counter,
TRIANGULAR_COUNTER_LENGHT
),
CHANNEL_LENGHT
)
);
@@ -136,19 +135,16 @@ BEGIN
m_axis_tdata <= s_axis_tdata;
END IF;
s_axis_tready_int <= '1';
m_axis_tvalid_int <= '1';
m_axis_tlast <= s_axis_tlast;
ELSE
s_axis_tready_int <= '0';
END IF;
END IF;
END IF;
END PROCESS;
END PROCESS AXIS;
END ARCHITECTURE Behavioral;

3
LAB3/src/all_pass_filter.vhd
View File

@@ -52,8 +52,9 @@ BEGIN
-- Handle data transfer
IF s_axis_tvalid = '1' AND m_axis_tready = '1' THEN
m_axis_tvalid_int <= '1';
m_axis_tdata <= s_axis_tdata;
m_axis_tvalid_int <= '1';
m_axis_tlast <= s_axis_tlast;
END IF;

2
LAB3/src/balance_controller.vhd
View File

@@ -40,7 +40,7 @@ ARCHITECTURE Behavioral OF balance_controller IS
BEGIN
-- Assigning the output signals
m_axis_tvalid <= m_axis_tvalid_int;
s_axis_tready <= m_axis_tready OR NOT m_axis_tvalid_int;
s_axis_tready <= (m_axis_tready OR NOT m_axis_tvalid_int) AND aresetn;
-- Balance to exp process to avoid changing the balance value when multiplying it for the sample data
BALANCE_CALC : PROCESS (aclk)

1
LAB3/src/effect_selector.vhd
View File

@@ -42,7 +42,6 @@ BEGIN
ELSE
-- volume/balance control
volume <= jstck_y;
lfo_period <= (OTHERS => '0');
END IF;

183
LAB3/src/led_level_controller.vhd
View File

@@ -1,121 +1,122 @@
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.NUMERIC_STD.ALL;
entity led_level_controller is
generic(
NUM_LEDS : positive := 16;
CHANNEL_LENGHT : positive := 24;
refresh_time_ms: positive :=1;
clock_period_ns: positive :=10
ENTITY led_level_controller IS
GENERIC (
NUM_LEDS : POSITIVE := 16;
CHANNEL_LENGHT : POSITIVE := 24;
refresh_time_ms : POSITIVE := 1;
clock_period_ns : POSITIVE := 10
);
Port (
aclk : in std_logic;
aresetn : in std_logic;
led : out std_logic_vector(NUM_LEDS-1 downto 0);
PORT (
s_axis_tvalid : in std_logic;
s_axis_tdata : in std_logic_vector(CHANNEL_LENGHT-1 downto 0);
s_axis_tlast : in std_logic;
s_axis_tready : out std_logic
aclk : IN STD_LOGIC;
aresetn : IN STD_LOGIC;
led : OUT STD_LOGIC_VECTOR(NUM_LEDS - 1 DOWNTO 0);
s_axis_tvalid : IN STD_LOGIC;
s_axis_tdata : IN STD_LOGIC_VECTOR(CHANNEL_LENGHT - 1 DOWNTO 0);
s_axis_tlast : IN STD_LOGIC;
s_axis_tready : OUT STD_LOGIC
);
end led_level_controller;
END led_level_controller;
architecture Behavioral of led_level_controller is
constant REFRESH_CYCLES : natural := (refresh_time_ms * 1_000_000) / clock_period_ns;
ARCHITECTURE Behavioral OF led_level_controller IS
CONSTANT REFRESH_CYCLES : NATURAL := (refresh_time_ms * 1_000_000) / clock_period_ns;
signal volume_value : signed(CHANNEL_LENGHT-1 downto 0) := (others => '0');
signal abs_audio_left : unsigned(CHANNEL_LENGHT-2 downto 0) := (others => '0');
signal abs_audio_right : unsigned(CHANNEL_LENGHT-2 downto 0) := (others => '0');
signal leds_int : std_logic_vector(NUM_LEDS-1 downto 0) := (others => '0');
signal led_update : std_logic := '0';
signal refresh_counter : natural range 0 to REFRESH_CYCLES-1 := 0;
SIGNAL volume_value : signed(CHANNEL_LENGHT - 1 DOWNTO 0) := (OTHERS => '0');
SIGNAL abs_audio_left : unsigned(CHANNEL_LENGHT - 2 DOWNTO 0) := (OTHERS => '0');
SIGNAL abs_audio_right : unsigned(CHANNEL_LENGHT - 2 DOWNTO 0) := (OTHERS => '0');
SIGNAL leds_int : STD_LOGIC_VECTOR(NUM_LEDS - 1 DOWNTO 0) := (OTHERS => '0');
SIGNAL led_update : STD_LOGIC := '0';
SIGNAL refresh_counter : NATURAL RANGE 0 TO REFRESH_CYCLES - 1 := 0;
begin
BEGIN
led <= leds_int;
s_axis_tready <= '1';
-- Registrazione del valore audio assoluto
process(aclk)
variable sdata_signed : signed(CHANNEL_LENGHT-1 downto 0);
variable abs_value : unsigned(CHANNEL_LENGHT-1 downto 0);
begin
if rising_edge(aclk) then
if aresetn = '0' then
volume_value <= (others => '0');
abs_audio_left <= (others => '0');
abs_audio_right<= (others => '0');
elsif s_axis_tvalid = '1' then
-- Registering the absolute audio value
PROCESS (aclk)
VARIABLE sdata_signed : signed(CHANNEL_LENGHT - 1 DOWNTO 0);
VARIABLE abs_value : unsigned(CHANNEL_LENGHT - 1 DOWNTO 0);
BEGIN
IF rising_edge(aclk) THEN
IF aresetn = '0' THEN
volume_value <= (OTHERS => '0');
abs_audio_left <= (OTHERS => '0');
abs_audio_right <= (OTHERS => '0');
ELSIF s_axis_tvalid = '1' THEN
sdata_signed := signed(s_axis_tdata);
volume_value <= sdata_signed;
-- Calcolo valore assoluto
if sdata_signed(CHANNEL_LENGHT-1) = '1' then
-- Absolute value calculation
IF sdata_signed(CHANNEL_LENGHT - 1) = '1' THEN
abs_value := unsigned(-sdata_signed);
else
ELSE
abs_value := unsigned(sdata_signed);
end if;
-- Assegna al canale corretto
if s_axis_tlast = '1' then -- Canale sinistro
abs_audio_left <= abs_value(CHANNEL_LENGHT-2 downto 0);
else -- Canale destro
abs_audio_right <= abs_value(CHANNEL_LENGHT-2 downto 0);
end if;
end if;
end if;
end process;
END IF;
-- Assign to the correct channel
IF s_axis_tlast = '1' THEN -- Left channel
abs_audio_left <= abs_value(CHANNEL_LENGHT - 2 DOWNTO 0);
ELSE -- Right channel
abs_audio_right <= abs_value(CHANNEL_LENGHT - 2 DOWNTO 0);
END IF;
END IF;
END IF;
END PROCESS;
-- Contatore di refresh
process(aclk)
begin
if rising_edge(aclk) then
if aresetn = '0' then
-- Refresh counter
PROCESS (aclk)
BEGIN
IF rising_edge(aclk) THEN
IF aresetn = '0' THEN
refresh_counter <= 0;
led_update <= '0';
elsif refresh_counter = REFRESH_CYCLES-1 then
ELSIF refresh_counter = REFRESH_CYCLES - 1 THEN
refresh_counter <= 0;
led_update <= '1';
else
ELSE
refresh_counter <= refresh_counter + 1;
led_update <= '0';
end if;
end if;
end process;
END IF;
END IF;
END PROCESS;
-- Scaling lineare e aggiornamento LED
process(aclk)
variable leds_on : natural range 0 to NUM_LEDS;
variable temp_led_level : integer range 0 to NUM_LEDS;
variable abs_audio_sum : unsigned(CHANNEL_LENGHT-1 downto 0);
begin
if rising_edge(aclk) then
if aresetn = '0' then
leds_int <= (others => '0');
elsif led_update = '1' then
-- Linear scaling and LED update
PROCESS (aclk)
VARIABLE leds_on : NATURAL RANGE 0 TO NUM_LEDS;
VARIABLE temp_led_level : INTEGER RANGE 0 TO NUM_LEDS;
VARIABLE abs_audio_sum : unsigned(CHANNEL_LENGHT - 1 DOWNTO 0);
BEGIN
IF rising_edge(aclk) THEN
IF aresetn = '0' THEN
leds_int <= (OTHERS => '0');
ELSIF led_update = '1' THEN
abs_audio_sum := resize(abs_audio_left, CHANNEL_LENGHT) + resize(abs_audio_right, CHANNEL_LENGHT);
if (abs_audio_left = 0 and abs_audio_right = 0) then
IF (abs_audio_left = 0 AND abs_audio_right = 0) THEN
temp_led_level := 0;
else
-- Scaling automatico: puoi regolare la costante di shift per la sensibilit<69>
temp_led_level := 1 + to_integer(shift_right(abs_audio_sum, CHANNEL_LENGHT-4));
end if;
ELSE
-- Automatic scaling
-- Sensitivity can be adjusted by changing the shift constant
temp_led_level := 1 + to_integer(shift_right(abs_audio_sum, CHANNEL_LENGHT - 4));
END IF;
-- Limita al massimo numero di LED
if temp_led_level > NUM_LEDS then
-- Limit to the maximum number of LEDs
IF temp_led_level > NUM_LEDS THEN
leds_on := NUM_LEDS;
else
ELSE
leds_on := temp_led_level;
end if;
END IF;
-- Aggiorna i LED
leds_int <= (others => '0');
if leds_on > 0 then
leds_int(leds_on-1 downto 0) <= (others => '1');
end if;
end if;
end if;
end process;
end Behavioral;
-- Update the LEDs
leds_int <= (OTHERS => '0');
IF leds_on > 0 THEN
leds_int(leds_on - 1 DOWNTO 0) <= (OTHERS => '1');
END IF;
END IF;
END IF;
END PROCESS;
END Behavioral;

1
LAB3/src/moving_average_filter_en.vhd
View File

@@ -141,6 +141,7 @@ BEGIN
-- Main AXIS assignments based on enable_filter
s_axis_tready <= all_pass_s_tready WHEN enable_filter = '0' ELSE moving_avg_s_tready;
m_axis_tvalid <= all_pass_m_tvalid WHEN enable_filter = '0' ELSE moving_avg_m_tvalid;
m_axis_tdata <= all_pass_m_tdata WHEN enable_filter = '0' ELSE moving_avg_m_tdata;
m_axis_tlast <= all_pass_m_tlast WHEN enable_filter = '0' ELSE moving_avg_m_tlast;

29
LAB3/src/mute_controller.vhd
View File

@@ -25,37 +25,40 @@ ENTITY mute_controller IS
END mute_controller;
ARCHITECTURE Behavioral OF mute_controller IS
SIGNAL m_axis_tvalid_int : STD_LOGIC;
BEGIN
-- Assigning the output signals
m_axis_tvalid <= m_axis_tvalid_int;
s_axis_tready <= (m_axis_tready OR NOT m_axis_tvalid_int) AND aresetn;
PROCESS (aclk)
BEGIN
IF rising_edge(aclk) THEN
IF aresetn = '0' THEN
m_axis_tvalid <= '0';
m_axis_tdata <= (OTHERS => '0');
m_axis_tvalid_int <= '0';
m_axis_tlast <= '0';
s_axis_tready <= '0';
ELSE
IF s_axis_tvalid = '1' AND m_axis_tready = '1' THEN
-- Accept input data
s_axis_tready <= '1';
m_axis_tvalid <= '1';
m_axis_tlast <= s_axis_tlast;
-- Clear valid flag when master interface is ready
IF m_axis_tready = '1' THEN
m_axis_tvalid_int <= '0';
END IF;
-- Handle the data flow
IF s_axis_tvalid = '1' AND m_axis_tready = '1' THEN
IF mute = '1' THEN
m_axis_tdata <= (OTHERS => '0');
ELSE
m_axis_tdata <= s_axis_tdata;
END IF;
ELSE
-- Do not accept new data
s_axis_tready <= '0';
m_axis_tvalid <= '0';
m_axis_tlast <= '0';
m_axis_tvalid_int <= '1';
m_axis_tlast <= s_axis_tlast;
END IF;

52
LAB3/vivado/lab3/lab3.xpr
View File

@@ -55,13 +55,13 @@
<Option Name="WTVcsLaunchSim" Val="0"/>
<Option Name="WTRivieraLaunchSim" Val="0"/>
<Option Name="WTActivehdlLaunchSim" Val="0"/>
<Option Name="WTXSimExportSim" Val="3"/>
<Option Name="WTModelSimExportSim" Val="3"/>
<Option Name="WTQuestaExportSim" Val="3"/>
<Option Name="WTIesExportSim" Val="3"/>
<Option Name="WTVcsExportSim" Val="3"/>
<Option Name="WTRivieraExportSim" Val="3"/>
<Option Name="WTActivehdlExportSim" Val="3"/>
<Option Name="WTXSimExportSim" Val="4"/>
<Option Name="WTModelSimExportSim" Val="4"/>
<Option Name="WTQuestaExportSim" Val="4"/>
<Option Name="WTIesExportSim" Val="4"/>
<Option Name="WTVcsExportSim" Val="4"/>
<Option Name="WTRivieraExportSim" Val="4"/>
<Option Name="WTActivehdlExportSim" Val="4"/>
<Option Name="GenerateIPUpgradeLog" Val="TRUE"/>
<Option Name="XSimRadix" Val="hex"/>
<Option Name="XSimTimeUnit" Val="ns"/>
@@ -89,6 +89,24 @@
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PPRDIR/../../src/led_controller.vhd">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PPRDIR/../../src/mute_controller.vhd">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PPRDIR/../../src/digilent_jstk2.vhd">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PPRDIR/../../src/all_pass_filter.vhd">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
@@ -137,7 +155,7 @@
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PPRDIR/../../src/led_controller.vhd">
<File Path="$PPRDIR/../../src/LFO.vhd">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="simulation"/>
@@ -149,24 +167,6 @@
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PPRDIR/../../src/mute_controller.vhd">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PPRDIR/../../src/digilent_jstk2.vhd">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PPRDIR/../../src/LFO.vhd">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PPRDIR/../../design/lab_3/lab_3.bd">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>