Davide 8fd7db7575 Refactor diligent_jstk design files: update clock wizard paths, modify interface nets, enhance uart_viewer.py for real-time data visualization, and remove unused Vivado project zip file.

2025-05-16 22:49:31 +02:00

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diligent_jstk

Refactor diligent_jstk design files: update clock wizard paths, modify interface nets, enhance uart_viewer.py for real-time data visualization, and remove unused Vivado project zip file.

2025-05-16 22:49:31 +02:00

lab_3

Refactor lab_3.bda to update node IDs and edge connections; modify digilent_jstk2.vhd to increase packet delay and adjust state machine; enhance uart_viewer.py for real-time coordinate visualization using matplotlib; update diligent_jstk.xpr simulation settings and remove unused file sets; add new Vivado project zip files for diligent_jstk and lab3.

2025-05-16 16:43:45 +02:00

loopback_I2S

Add AXI4-Stream UART IP and associated files

2025-05-12 18:16:58 +02:00