Davide 8fd7db7575 Refactor diligent_jstk design files: update clock wizard paths, modify interface nets, enhance uart_viewer.py for real-time data visualization, and remove unused Vivado project zip file.

2025-05-16 22:49:31 +02:00

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hdl

Refactor diligent_jstk design files: update clock wizard paths, modify interface nets, enhance uart_viewer.py for real-time data visualization, and remove unused Vivado project zip file.

2025-05-16 22:49:31 +02:00

diligent_jstk.bd

Refactor diligent_jstk design files: update clock wizard paths, modify interface nets, enhance uart_viewer.py for real-time data visualization, and remove unused Vivado project zip file.

2025-05-16 22:49:31 +02:00

diligent_jstk.bda

Add AXI4-Stream UART IP and associated files

2025-05-12 18:16:58 +02:00