Davide 9828eed333 fix: Correct LFO step clock cycle calculations for accurate amplitude modulation

2025-06-01 01:03:19 +02:00

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cons

Refactor and optimize various components in LAB3 design

2025-05-23 15:53:03 +02:00

design

Update .gitignore, lab_3_wrapper.vhd, lab_3.bd, lab_3.bda, and digilent_jstk2.vhd for improved organization and functionality

2025-05-30 14:32:33 +02:00

ip

Add AXI4-Stream UART IP and associated files

2025-05-12 18:16:58 +02:00

sim

Update SPI clock frequency in testbench and enhance comments in effect selector for clarity on joystick mode switching

2025-05-28 19:28:14 +02:00

src

fix: Correct LFO step clock cycle calculations for accurate amplitude modulation

2025-06-01 01:03:19 +02:00

test

Refactor project structure and update dependencies

2025-05-30 14:14:25 +02:00

vivado

Remove unused files

2025-05-30 21:25:18 +02:00