Cd16d
60a8aa912d
- Created a new Block Design Archive (lab_3.bda) for LAB3, defining nodes and edges for the design. - Added a placeholder README file in the simulation directory. - Initialized a Vivado project file (lab3.xpr) with configuration settings and source files for synthesis and simulation. - Updated vhdl_ls.toml to include LAB3 source and simulation files for VHDL language server support.
3 lines
37 B
Markdown
3 lines
37 B
Markdown
# Placeholder
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This is a placeholder. |