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2025-03-18 00:08:53 +01:00
2025-03-18 00:08:53 +01:00
2025-03-18 00:08:53 +01:00
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Description
Digital Electronic System Design Laboratory
https://github.com/Cd16d/DESD
Readme 301 MiB
Languages
VHDL 86%
Tcl 9%
Python 2.7%
Verilog 2.2%
Makefile 0.1%