182 lines
3.9 KiB
VHDL
182 lines
3.9 KiB
VHDL
----------------------------------------------------------------------------------
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-- Company:
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-- Engineer:
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--
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-- Create Date: 07.03.2019 12:46:18
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-- Design Name:
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-- Module Name: tb_ShiftRegister_v0 - Behavioral
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-- Project Name:
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-- Target Devices:
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-- Tool Versions:
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-- Description:
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--
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-- Dependencies:
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--
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-- Revision:
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-- Revision 0.01 - File Created
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-- Additional Comments:
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--
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----------------------------------------------------------------------------------
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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-- Uncomment the following library declaration if using
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-- arithmetic functions with Signed or Unsigned values
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use IEEE.NUMERIC_STD.ALL;
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-- Uncomment the following library declaration if instantiating
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-- any Xilinx leaf cells in this code.
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--library UNISIM;
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--use UNISIM.VComponents.all;
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entity tb_ShiftRegister_v0 is
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end tb_ShiftRegister_v0;
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architecture Behavioral of tb_ShiftRegister_v0 is
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------------------------ Constant Declaration -------------------------
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-- Constant For Test Bench (TB) --
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constant RESET_ON : STD_LOGIC := '1';
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constant CLK_PERIOD : time := 10 ns;
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constant RESET_WND : time := 100 ns;
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----------------------------------
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----------------------------------------------------------------------
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----------------- Device Under Test (DUT) Declaration ----------------
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------------ DUT v0 --------------
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COMPONENT ShiftRegister_v0
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Port (
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---------- Reset/Clock ----------
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reset : IN STD_LOGIC;
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clk : IN STD_LOGIC;
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---------------------------------
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------------- Data --------------
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din : IN STD_LOGIC;
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dout : OUT STD_LOGIC
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---------------------------------
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);
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END COMPONENT;
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----------------------------------
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----------------------------------------------------------------------
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------------------------- Signal Declaration -------------------------
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---------- Reset/Clock ----------
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signal reset : STD_LOGIC := RESET_ON;
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signal clk : STD_LOGIC := '1';
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---------------------------------
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-------- ShiftRegister_v0 -------
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signal dut0_din : STD_LOGIC := '0';
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signal dut0_dout : STD_LOGIC;
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---------------------------------
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----------------------------------------------------------------------
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begin
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------------------- Device Under Test (DUT) Wrapper ------------------
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------------ DUT v0 --------------
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dut0_ShiftRegister_v0 : ShiftRegister_v0
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Port Map(
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---------- Reset/Clock ----------
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reset => reset,
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clk => clk,
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---------------------------------
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------------- Data --------------
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din => dut0_din,
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dout => dut0_dout
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---------------------------------
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);
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----------------------------------
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----------------------------------------------------------------------
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-------------------------- Signals Generation -------------------------
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------ TB Clk Generation -------
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clk <= not clk after CLK_PERIOD/2;
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---------------------------------
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----- TB Reset Generation ------
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reset_wave : process
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begin
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reset <= '1';
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wait for RESET_WND;
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reset <= '0';
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wait;
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end process;
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---------------------------------
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-- TB din pattern Generation ---
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dut0_din_pattern : process
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begin
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-- wait the reset window
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dut0_din <= '0';
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wait for RESET_WND;
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-- Start
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dut0_din <= '0';
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wait for CLK_PERIOD;
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dut0_din <= '1';
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wait for 4*CLK_PERIOD;
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dut0_din <= '0';
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wait for 8*CLK_PERIOD;
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-- Etc...
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-- Stop
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wait;
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end process;
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---------------------------------
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----------------------------------------------------------------------
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end Behavioral;
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