81 lines
2.1 KiB
VHDL
81 lines
2.1 KiB
VHDL
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-- Company:
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-- Engineer:
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--
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-- Create Date: 07.03.2025 15:23:11
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-- Design Name:
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-- Module Name: PulseWidthModulator - Behavioral
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-- Project Name:
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-- Target Devices:
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-- Tool Versions:
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-- Description:
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--
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-- Dependencies:
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--
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-- Revision:
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-- Revision 0.01 - File Created
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-- Additional Comments:
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--
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----------------------------------------------------------------------------------
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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-- Uncomment the following library declaration if using
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-- arithmetic functions with Signed or Unsigned values
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use IEEE.NUMERIC_STD.ALL;
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-- Uncomment the following library declaration if instantiating
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-- any Xilinx leaf cells in this code.
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--library UNISIM;
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--use UNISIM.VComponents.all;
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entity PulseWidthModulator is
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Generic(
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BIT_LENGTH : INTEGER RANGE 1 to 16 := 8
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);
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Port (
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reset : IN STD_LOGIC;
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clk : IN STD_LOGIC;
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Ton : IN std_logic_vector(BIT_LENGTH-1 downto 0);
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Period : IN std_logic_vector(BIT_LENGTH-1 downto 0);
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PWM : OUT std_logic
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);
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end PulseWidthModulator;
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architecture Behavioral of PulseWidthModulator is
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signal counter : unsigned(BIT_LENGTH-1 downto 0) := (others => '0');
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signal pwm_out : std_logic;
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begin
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process(clk, reset)
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begin
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if reset = '1' then
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counter <= (others => '0');
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pwm_out <= '0'; -- Assicura PWM spento al reset
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elsif rising_edge(clk) then
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if counter = unsigned(period) then
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counter <= (others => '0'); -- Reset counter
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else
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counter <= counter + 1; -- Incrementa il counter
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end if;
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-- Accendi il PWM all'inizio di ogni ciclo
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if counter = 0 then
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pwm_out <= '1';
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end if;
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-- Spegni il PWM quando il contatore raggiunge Ton
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if counter = unsigned(Ton) then
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pwm_out <= '0';
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end if;
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end if;
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end process;
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PWM <= pwm_out; -- Output PWM
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end Behavioral;
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