This repository contains VHDL projects and exercises from the Digital Electronic System Design Laboratory at Politecnico di Milano (Course Code: 054083). The course focuses on FPGA-based digital design using VHDL, simulation, synthesis, and implementation.

Tools & Hardware

Software: Xilinx Vivado 2020.2 (WebPack Edition)
Hardware: Digilent Basys 3 (Xilinx Artix-7 FPGA - XC7A35T-1CPG236C)

Course Goals

Develop practical skills for FPGA-based digital system design
Implement and test VHDL architectures using Vivado and Basys 3
Learn FPGA timing, power, I/O, and memory management

Languages

VHDL 86%

Tcl 9%

Python 2.7%

Verilog 2.2%

Makefile 0.1%

README.md Unescape Escape

VHDL Laboratory – Digital Electronic System Design

Overview

Tools & Hardware

Course Goals

README.md