Cd16d be88f69202 Refactor LFO, all_pass_filter, and moving_average_filter: enhance output assignments, improve data handling, and streamline signal processing logic for better performance and maintainability.

2025-05-18 00:36:30 +02:00

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cons

Add initial design files and project configuration for LAB3

2025-05-12 14:20:41 +02:00

design

Refactor diligent_jstk design files: update interface nets in diligent_jstk.bd, adjust UART interface in uart_viewer.py for enhanced data handling, and modify digilent_jstk2.vhd to remove unnecessary initialization.

2025-05-17 16:16:44 +02:00

ip

Add AXI4-Stream UART IP and associated files

2025-05-12 18:16:58 +02:00

sim

Update VHDL and Python files for improved functionality and performance

2025-05-15 16:46:09 +02:00

src

Refactor LFO, all_pass_filter, and moving_average_filter: enhance output assignments, improve data handling, and streamline signal processing logic for better performance and maintainability.

2025-05-18 00:36:30 +02:00

test

Refactor code structure for improved readability and maintainability

2025-05-17 20:03:03 +02:00

vivado

Remove unused Vivado project zip file

2025-05-17 22:04:44 +02:00