Cd16d 63aa004db9 Remove unused Vivado project zip file

2025-05-17 22:04:44 +02:00

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diligent_jstk

Refactor diligent_jstk design files: update interface nets in diligent_jstk.bd, adjust UART interface in uart_viewer.py for enhanced data handling, and modify digilent_jstk2.vhd to remove unnecessary initialization.

2025-05-17 16:16:44 +02:00

lab3

Remove unused Vivado project zip file

2025-05-17 22:04:44 +02:00

loopback_I2S

Add AXI4-Stream UART IP and associated files

2025-05-12 18:16:58 +02:00