Davide e21c00512f Update clk to 100MHz

2025-05-30 13:54:13 +02:00

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cons

Refactor and optimize various components in LAB3 design

2025-05-23 15:53:03 +02:00

design

Update clk to 100MHz

2025-05-30 13:54:13 +02:00

ip

Add AXI4-Stream UART IP and associated files

2025-05-12 18:16:58 +02:00

sim

Update SPI clock frequency in testbench and enhance comments in effect selector for clarity on joystick mode switching

2025-05-28 19:28:14 +02:00

src

Update SPI clock frequency in testbench and enhance comments in effect selector for clarity on joystick mode switching

2025-05-28 19:28:14 +02:00

test

Refactor code structure for improved readability and maintainability

2025-05-17 20:03:03 +02:00

vivado

Update clk to 100MHz

2025-05-30 13:54:13 +02:00