Files
DESD/LAB2/src/lab_2/lab_2.bd
Davide 4433b3f457 Add pak_depak design files and update project references
- Created new design file `pak_depak.bd` with components including `proc_sys_reset`, `clk_wiz`, `AXI4Stream_UART`, `depacketizer`, and `packetizer`.
- Added associated architecture file `pak_depak.bda` for design representation.
- Introduced UI configuration file `bd_c9b29a54.ui` for graphical representation of the design.
- Updated project file `lab2.xpr` to replace references to old source files with new ones.
- Added new project file `pak_depak.xpr` for the pak_depak design with necessary configurations and file sets.
2025-04-15 17:27:38 +02:00

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{
"design": {
"design_info": {
"boundary_crc": "0x880B1E867400A6BE",
"device": "xc7a35tcpg236-1",
"name": "lab_2",
"rev_ctrl_bd_flag": "RevCtrlBdOff",
"synth_flow_mode": "None",
"tool_version": "2020.2"
},
"design_tree": {
"bram_writer_0": "",
"led_blinker_0": "",
"led_blinker_1": "",
"led_blinker_2": "",
"system_ila_0": "",
"clk_wiz_0": "",
"proc_sys_reset_1": "",
"AXI4Stream_UART_0": "",
"img_conv_0": "",
"depacketizer_0": "",
"packetizer_0": "",
"rgb2gray_0": ""
},
"interface_ports": {
"usb_uart": {
"mode": "Master",
"vlnv": "xilinx.com:interface:uart_rtl:1.0"
}
},
"ports": {
"led_of": {
"direction": "O"
},
"led_ok": {
"direction": "O"
},
"led_uf": {
"direction": "O"
},
"sys_clock": {
"type": "clk",
"direction": "I",
"parameters": {
"FREQ_HZ": {
"value": "100000000"
},
"PHASE": {
"value": "0.000"
}
}
},
"reset": {
"type": "rst",
"direction": "I",
"parameters": {
"POLARITY": {
"value": "ACTIVE_HIGH"
}
}
}
},
"components": {
"bram_writer_0": {
"vlnv": "xilinx.com:module_ref:bram_writer:1.0",
"xci_name": "lab_2_bram_writer_0_0",
"xci_path": "ip\\lab_2_bram_writer_0_0\\lab_2_bram_writer_0_0.xci",
"inst_hier_path": "bram_writer_0",
"reference_info": {
"ref_type": "hdl",
"ref_name": "bram_writer",
"boundary_crc": "0x0"
},
"interface_ports": {
"s_axis": {
"mode": "Slave",
"vlnv": "xilinx.com:interface:axis_rtl:1.0",
"parameters": {
"TDATA_NUM_BYTES": {
"value": "1",
"value_src": "constant"
},
"TDEST_WIDTH": {
"value": "0",
"value_src": "constant"
},
"TID_WIDTH": {
"value": "0",
"value_src": "constant"
},
"TUSER_WIDTH": {
"value": "0",
"value_src": "constant"
},
"HAS_TREADY": {
"value": "1",
"value_src": "constant"
},
"HAS_TSTRB": {
"value": "0",
"value_src": "constant"
},
"HAS_TKEEP": {
"value": "0",
"value_src": "constant"
},
"HAS_TLAST": {
"value": "1",
"value_src": "constant"
},
"FREQ_HZ": {
"value": "100000000",
"value_src": "ip_prop"
},
"PHASE": {
"value": "0.0",
"value_src": "ip_prop"
},
"CLK_DOMAIN": {
"value": "/clk_wiz_0_clk_out1",
"value_src": "ip_prop"
}
},
"port_maps": {
"TDATA": {
"physical_name": "s_axis_tdata",
"direction": "I",
"left": "7",
"right": "0"
},
"TLAST": {
"physical_name": "s_axis_tlast",
"direction": "I"
},
"TVALID": {
"physical_name": "s_axis_tvalid",
"direction": "I"
},
"TREADY": {
"physical_name": "s_axis_tready",
"direction": "O"
}
}
}
},
"ports": {
"clk": {
"type": "clk",
"direction": "I",
"parameters": {
"ASSOCIATED_BUSIF": {
"value": "s_axis",
"value_src": "constant"
},
"ASSOCIATED_RESET": {
"value": "aresetn",
"value_src": "constant"
},
"FREQ_HZ": {
"value": "100000000",
"value_src": "ip_prop"
},
"PHASE": {
"value": "0.0",
"value_src": "ip_prop"
},
"CLK_DOMAIN": {
"value": "/clk_wiz_0_clk_out1",
"value_src": "ip_prop"
}
}
},
"aresetn": {
"type": "rst",
"direction": "I",
"parameters": {
"POLARITY": {
"value": "ACTIVE_LOW",
"value_src": "constant"
}
}
},
"conv_addr": {
"direction": "I",
"left": "15",
"right": "0"
},
"conv_data": {
"direction": "O",
"left": "6",
"right": "0"
},
"start_conv": {
"direction": "O"
},
"done_conv": {
"direction": "I"
},
"write_ok": {
"direction": "O"
},
"overflow": {
"direction": "O"
},
"underflow": {
"direction": "O"
}
}
},
"led_blinker_0": {
"vlnv": "xilinx.com:module_ref:led_blinker:1.0",
"xci_name": "lab_2_led_blinker_0_0",
"xci_path": "ip\\lab_2_led_blinker_0_0\\lab_2_led_blinker_0_0.xci",
"inst_hier_path": "led_blinker_0",
"reference_info": {
"ref_type": "hdl",
"ref_name": "led_blinker",
"boundary_crc": "0x0"
},
"ports": {
"clk": {
"type": "clk",
"direction": "I",
"parameters": {
"ASSOCIATED_RESET": {
"value": "aresetn",
"value_src": "constant"
},
"FREQ_HZ": {
"value": "100000000",
"value_src": "ip_prop"
},
"PHASE": {
"value": "0.0",
"value_src": "ip_prop"
},
"CLK_DOMAIN": {
"value": "/clk_wiz_0_clk_out1",
"value_src": "ip_prop"
}
}
},
"aresetn": {
"type": "rst",
"direction": "I",
"parameters": {
"POLARITY": {
"value": "ACTIVE_LOW",
"value_src": "constant"
}
}
},
"start_blink": {
"direction": "I"
},
"led": {
"direction": "O"
}
}
},
"led_blinker_1": {
"vlnv": "xilinx.com:module_ref:led_blinker:1.0",
"xci_name": "lab_2_led_blinker_1_0",
"xci_path": "ip\\lab_2_led_blinker_1_0\\lab_2_led_blinker_1_0.xci",
"inst_hier_path": "led_blinker_1",
"reference_info": {
"ref_type": "hdl",
"ref_name": "led_blinker",
"boundary_crc": "0x0"
},
"ports": {
"clk": {
"type": "clk",
"direction": "I",
"parameters": {
"ASSOCIATED_RESET": {
"value": "aresetn",
"value_src": "constant"
},
"FREQ_HZ": {
"value": "100000000",
"value_src": "ip_prop"
},
"PHASE": {
"value": "0.0",
"value_src": "ip_prop"
},
"CLK_DOMAIN": {
"value": "/clk_wiz_0_clk_out1",
"value_src": "ip_prop"
}
}
},
"aresetn": {
"type": "rst",
"direction": "I",
"parameters": {
"POLARITY": {
"value": "ACTIVE_LOW",
"value_src": "constant"
}
}
},
"start_blink": {
"direction": "I"
},
"led": {
"direction": "O"
}
}
},
"led_blinker_2": {
"vlnv": "xilinx.com:module_ref:led_blinker:1.0",
"xci_name": "lab_2_led_blinker_2_0",
"xci_path": "ip\\lab_2_led_blinker_2_0\\lab_2_led_blinker_2_0.xci",
"inst_hier_path": "led_blinker_2",
"reference_info": {
"ref_type": "hdl",
"ref_name": "led_blinker",
"boundary_crc": "0x0"
},
"ports": {
"clk": {
"type": "clk",
"direction": "I",
"parameters": {
"ASSOCIATED_RESET": {
"value": "aresetn",
"value_src": "constant"
},
"FREQ_HZ": {
"value": "100000000",
"value_src": "ip_prop"
},
"PHASE": {
"value": "0.0",
"value_src": "ip_prop"
},
"CLK_DOMAIN": {
"value": "/clk_wiz_0_clk_out1",
"value_src": "ip_prop"
}
}
},
"aresetn": {
"type": "rst",
"direction": "I",
"parameters": {
"POLARITY": {
"value": "ACTIVE_LOW",
"value_src": "constant"
}
}
},
"start_blink": {
"direction": "I"
},
"led": {
"direction": "O"
}
}
},
"system_ila_0": {
"vlnv": "xilinx.com:ip:system_ila:1.1",
"xci_name": "lab_2_system_ila_0_1",
"xci_path": "ip\\lab_2_system_ila_0_1\\lab_2_system_ila_0_1.xci",
"inst_hier_path": "system_ila_0",
"parameters": {
"C_MON_TYPE": {
"value": "MIX"
},
"C_NUM_MONITOR_SLOTS": {
"value": "3"
},
"C_NUM_OF_PROBES": {
"value": "4"
},
"C_SLOT": {
"value": "2"
},
"C_SLOT_0_INTF_TYPE": {
"value": "xilinx.com:interface:axis_rtl:1.0"
},
"C_SLOT_1_INTF_TYPE": {
"value": "xilinx.com:interface:axis_rtl:1.0"
},
"C_SLOT_2_INTF_TYPE": {
"value": "xilinx.com:interface:axis_rtl:1.0"
}
},
"interface_ports": {
"SLOT_0_AXIS": {
"mode": "Monitor",
"vlnv": "xilinx.com:interface:axis_rtl:1.0"
},
"SLOT_1_AXIS": {
"mode": "Monitor",
"vlnv": "xilinx.com:interface:axis_rtl:1.0"
},
"SLOT_2_AXIS": {
"mode": "Monitor",
"vlnv": "xilinx.com:interface:axis_rtl:1.0"
}
}
},
"clk_wiz_0": {
"vlnv": "xilinx.com:ip:clk_wiz:6.0",
"xci_name": "lab_2_clk_wiz_0_1",
"xci_path": "ip\\lab_2_clk_wiz_0_1\\lab_2_clk_wiz_0_1.xci",
"inst_hier_path": "clk_wiz_0",
"parameters": {
"CLK_IN1_BOARD_INTERFACE": {
"value": "sys_clock"
},
"RESET_BOARD_INTERFACE": {
"value": "reset"
},
"USE_BOARD_FLOW": {
"value": "true"
}
}
},
"proc_sys_reset_1": {
"vlnv": "xilinx.com:ip:proc_sys_reset:5.0",
"xci_name": "lab_2_proc_sys_reset_1_1",
"xci_path": "ip\\lab_2_proc_sys_reset_1_1\\lab_2_proc_sys_reset_1_1.xci",
"inst_hier_path": "proc_sys_reset_1",
"parameters": {
"RESET_BOARD_INTERFACE": {
"value": "reset"
},
"USE_BOARD_FLOW": {
"value": "true"
}
}
},
"AXI4Stream_UART_0": {
"vlnv": "DigiLAB:ip:AXI4Stream_UART:1.1",
"xci_name": "lab_2_AXI4Stream_UART_0_2",
"xci_path": "ip\\lab_2_AXI4Stream_UART_0_2\\lab_2_AXI4Stream_UART_0_2.xci",
"inst_hier_path": "AXI4Stream_UART_0",
"parameters": {
"UART_BOARD_INTERFACE": {
"value": "usb_uart"
},
"USE_BOARD_FLOW": {
"value": "true"
}
}
},
"img_conv_0": {
"vlnv": "xilinx.com:module_ref:img_conv:1.0",
"xci_name": "lab_2_img_conv_0_0",
"xci_path": "ip\\lab_2_img_conv_0_0\\lab_2_img_conv_0_0.xci",
"inst_hier_path": "img_conv_0",
"reference_info": {
"ref_type": "hdl",
"ref_name": "img_conv",
"boundary_crc": "0x0"
},
"interface_ports": {
"m_axis": {
"mode": "Master",
"vlnv": "xilinx.com:interface:axis_rtl:1.0",
"parameters": {
"TDATA_NUM_BYTES": {
"value": "1",
"value_src": "constant"
},
"TDEST_WIDTH": {
"value": "0",
"value_src": "constant"
},
"TID_WIDTH": {
"value": "0",
"value_src": "constant"
},
"TUSER_WIDTH": {
"value": "0",
"value_src": "constant"
},
"HAS_TREADY": {
"value": "1",
"value_src": "constant"
},
"HAS_TSTRB": {
"value": "0",
"value_src": "constant"
},
"HAS_TKEEP": {
"value": "0",
"value_src": "constant"
},
"HAS_TLAST": {
"value": "1",
"value_src": "constant"
}
},
"port_maps": {
"TDATA": {
"physical_name": "m_axis_tdata",
"direction": "O",
"left": "7",
"right": "0"
},
"TLAST": {
"physical_name": "m_axis_tlast",
"direction": "O"
},
"TVALID": {
"physical_name": "m_axis_tvalid",
"direction": "O"
},
"TREADY": {
"physical_name": "m_axis_tready",
"direction": "I"
}
}
}
},
"ports": {
"clk": {
"type": "clk",
"direction": "I",
"parameters": {
"ASSOCIATED_BUSIF": {
"value": "m_axis",
"value_src": "constant"
},
"ASSOCIATED_RESET": {
"value": "aresetn",
"value_src": "constant"
}
}
},
"aresetn": {
"type": "rst",
"direction": "I",
"parameters": {
"POLARITY": {
"value": "ACTIVE_LOW",
"value_src": "constant"
}
}
},
"conv_addr": {
"direction": "O",
"left": "15",
"right": "0"
},
"conv_data": {
"direction": "I",
"left": "6",
"right": "0"
},
"start_conv": {
"direction": "I"
},
"done_conv": {
"direction": "O"
}
}
},
"depacketizer_0": {
"vlnv": "xilinx.com:module_ref:depacketizer:1.0",
"xci_name": "lab_2_depacketizer_0_0",
"xci_path": "ip\\lab_2_depacketizer_0_0\\lab_2_depacketizer_0_0.xci",
"inst_hier_path": "depacketizer_0",
"reference_info": {
"ref_type": "hdl",
"ref_name": "depacketizer",
"boundary_crc": "0x0"
},
"interface_ports": {
"m_axis": {
"mode": "Master",
"vlnv": "xilinx.com:interface:axis_rtl:1.0",
"parameters": {
"TDATA_NUM_BYTES": {
"value": "1",
"value_src": "constant"
},
"TDEST_WIDTH": {
"value": "0",
"value_src": "constant"
},
"TID_WIDTH": {
"value": "0",
"value_src": "constant"
},
"TUSER_WIDTH": {
"value": "0",
"value_src": "constant"
},
"HAS_TREADY": {
"value": "1",
"value_src": "constant"
},
"HAS_TSTRB": {
"value": "0",
"value_src": "constant"
},
"HAS_TKEEP": {
"value": "0",
"value_src": "constant"
},
"HAS_TLAST": {
"value": "1",
"value_src": "constant"
}
},
"port_maps": {
"TDATA": {
"physical_name": "m_axis_tdata",
"direction": "O",
"left": "7",
"right": "0"
},
"TLAST": {
"physical_name": "m_axis_tlast",
"direction": "O"
},
"TVALID": {
"physical_name": "m_axis_tvalid",
"direction": "O"
},
"TREADY": {
"physical_name": "m_axis_tready",
"direction": "I"
}
}
},
"s_axis": {
"mode": "Slave",
"vlnv": "xilinx.com:interface:axis_rtl:1.0",
"parameters": {
"TDATA_NUM_BYTES": {
"value": "1",
"value_src": "constant"
},
"TDEST_WIDTH": {
"value": "0",
"value_src": "constant"
},
"TID_WIDTH": {
"value": "0",
"value_src": "constant"
},
"TUSER_WIDTH": {
"value": "0",
"value_src": "constant"
},
"HAS_TREADY": {
"value": "1",
"value_src": "constant"
},
"HAS_TSTRB": {
"value": "0",
"value_src": "constant"
},
"HAS_TKEEP": {
"value": "0",
"value_src": "constant"
},
"HAS_TLAST": {
"value": "0",
"value_src": "constant"
}
},
"port_maps": {
"TDATA": {
"physical_name": "s_axis_tdata",
"direction": "I",
"left": "7",
"right": "0"
},
"TVALID": {
"physical_name": "s_axis_tvalid",
"direction": "I"
},
"TREADY": {
"physical_name": "s_axis_tready",
"direction": "O"
}
}
}
},
"ports": {
"clk": {
"type": "clk",
"direction": "I",
"parameters": {
"ASSOCIATED_BUSIF": {
"value": "m_axis:s_axis",
"value_src": "constant"
},
"ASSOCIATED_RESET": {
"value": "aresetn",
"value_src": "constant"
}
}
},
"aresetn": {
"type": "rst",
"direction": "I",
"parameters": {
"POLARITY": {
"value": "ACTIVE_LOW",
"value_src": "constant"
}
}
}
}
},
"packetizer_0": {
"vlnv": "xilinx.com:module_ref:packetizer:1.0",
"xci_name": "lab_2_packetizer_0_0",
"xci_path": "ip\\lab_2_packetizer_0_0\\lab_2_packetizer_0_0.xci",
"inst_hier_path": "packetizer_0",
"reference_info": {
"ref_type": "hdl",
"ref_name": "packetizer",
"boundary_crc": "0x0"
},
"interface_ports": {
"m_axis": {
"mode": "Master",
"vlnv": "xilinx.com:interface:axis_rtl:1.0",
"parameters": {
"TDATA_NUM_BYTES": {
"value": "1",
"value_src": "constant"
},
"TDEST_WIDTH": {
"value": "0",
"value_src": "constant"
},
"TID_WIDTH": {
"value": "0",
"value_src": "constant"
},
"TUSER_WIDTH": {
"value": "0",
"value_src": "constant"
},
"HAS_TREADY": {
"value": "1",
"value_src": "constant"
},
"HAS_TSTRB": {
"value": "0",
"value_src": "constant"
},
"HAS_TKEEP": {
"value": "0",
"value_src": "constant"
},
"HAS_TLAST": {
"value": "1",
"value_src": "constant"
}
},
"port_maps": {
"TDATA": {
"physical_name": "m_axis_tdata",
"direction": "O",
"left": "7",
"right": "0"
},
"TLAST": {
"physical_name": "m_axis_tlast",
"direction": "O"
},
"TVALID": {
"physical_name": "m_axis_tvalid",
"direction": "O"
},
"TREADY": {
"physical_name": "m_axis_tready",
"direction": "I"
}
}
},
"s_axis": {
"mode": "Slave",
"vlnv": "xilinx.com:interface:axis_rtl:1.0",
"parameters": {
"TDATA_NUM_BYTES": {
"value": "1",
"value_src": "constant"
},
"TDEST_WIDTH": {
"value": "0",
"value_src": "constant"
},
"TID_WIDTH": {
"value": "0",
"value_src": "constant"
},
"TUSER_WIDTH": {
"value": "0",
"value_src": "constant"
},
"HAS_TREADY": {
"value": "1",
"value_src": "constant"
},
"HAS_TSTRB": {
"value": "0",
"value_src": "constant"
},
"HAS_TKEEP": {
"value": "0",
"value_src": "constant"
},
"HAS_TLAST": {
"value": "0",
"value_src": "constant"
}
},
"port_maps": {
"TDATA": {
"physical_name": "s_axis_tdata",
"direction": "I",
"left": "7",
"right": "0"
},
"TVALID": {
"physical_name": "s_axis_tvalid",
"direction": "I"
},
"TREADY": {
"physical_name": "s_axis_tready",
"direction": "O"
}
}
}
},
"ports": {
"clk": {
"type": "clk",
"direction": "I",
"parameters": {
"ASSOCIATED_BUSIF": {
"value": "m_axis:s_axis",
"value_src": "constant"
},
"ASSOCIATED_RESET": {
"value": "aresetn",
"value_src": "constant"
}
}
},
"aresetn": {
"type": "rst",
"direction": "I",
"parameters": {
"POLARITY": {
"value": "ACTIVE_LOW",
"value_src": "constant"
}
}
}
}
},
"rgb2gray_0": {
"vlnv": "xilinx.com:module_ref:rgb2gray:1.0",
"xci_name": "lab_2_rgb2gray_0_0",
"xci_path": "ip\\lab_2_rgb2gray_0_0\\lab_2_rgb2gray_0_0.xci",
"inst_hier_path": "rgb2gray_0",
"reference_info": {
"ref_type": "hdl",
"ref_name": "rgb2gray",
"boundary_crc": "0x0"
},
"interface_ports": {
"m_axis": {
"mode": "Master",
"vlnv": "xilinx.com:interface:axis_rtl:1.0",
"parameters": {
"TDATA_NUM_BYTES": {
"value": "1",
"value_src": "constant"
},
"TDEST_WIDTH": {
"value": "0",
"value_src": "constant"
},
"TID_WIDTH": {
"value": "0",
"value_src": "constant"
},
"TUSER_WIDTH": {
"value": "0",
"value_src": "constant"
},
"HAS_TREADY": {
"value": "1",
"value_src": "constant"
},
"HAS_TSTRB": {
"value": "0",
"value_src": "constant"
},
"HAS_TKEEP": {
"value": "0",
"value_src": "constant"
},
"HAS_TLAST": {
"value": "1",
"value_src": "constant"
}
},
"port_maps": {
"TDATA": {
"physical_name": "m_axis_tdata",
"direction": "O",
"left": "7",
"right": "0"
},
"TLAST": {
"physical_name": "m_axis_tlast",
"direction": "O"
},
"TVALID": {
"physical_name": "m_axis_tvalid",
"direction": "O"
},
"TREADY": {
"physical_name": "m_axis_tready",
"direction": "I"
}
}
},
"s_axis": {
"mode": "Slave",
"vlnv": "xilinx.com:interface:axis_rtl:1.0",
"parameters": {
"TDATA_NUM_BYTES": {
"value": "1",
"value_src": "constant"
},
"TDEST_WIDTH": {
"value": "0",
"value_src": "constant"
},
"TID_WIDTH": {
"value": "0",
"value_src": "constant"
},
"TUSER_WIDTH": {
"value": "0",
"value_src": "constant"
},
"HAS_TREADY": {
"value": "1",
"value_src": "constant"
},
"HAS_TSTRB": {
"value": "0",
"value_src": "constant"
},
"HAS_TKEEP": {
"value": "0",
"value_src": "constant"
},
"HAS_TLAST": {
"value": "1",
"value_src": "constant"
}
},
"port_maps": {
"TDATA": {
"physical_name": "s_axis_tdata",
"direction": "I",
"left": "7",
"right": "0"
},
"TLAST": {
"physical_name": "s_axis_tlast",
"direction": "I"
},
"TVALID": {
"physical_name": "s_axis_tvalid",
"direction": "I"
},
"TREADY": {
"physical_name": "s_axis_tready",
"direction": "O"
}
}
}
},
"ports": {
"clk": {
"type": "clk",
"direction": "I",
"parameters": {
"ASSOCIATED_BUSIF": {
"value": "m_axis:s_axis",
"value_src": "constant"
},
"ASSOCIATED_RESET": {
"value": "resetn",
"value_src": "constant"
}
}
},
"resetn": {
"type": "rst",
"direction": "I",
"parameters": {
"POLARITY": {
"value": "ACTIVE_LOW",
"value_src": "constant"
}
}
}
}
}
},
"interface_nets": {
"Conn": {
"interface_ports": [
"rgb2gray_0/s_axis",
"depacketizer_0/m_axis",
"system_ila_0/SLOT_0_AXIS"
]
},
"AXI4Stream_UART_0_UART": {
"interface_ports": [
"usb_uart",
"AXI4Stream_UART_0/UART"
]
},
"AXI4Stream_UART_0_M00_AXIS_RX": {
"interface_ports": [
"AXI4Stream_UART_0/M00_AXIS_RX",
"depacketizer_0/s_axis"
]
},
"packetizer_0_m_axis": {
"interface_ports": [
"packetizer_0/m_axis",
"AXI4Stream_UART_0/S00_AXIS_TX"
]
},
"rgb2gray_0_m_axis": {
"interface_ports": [
"rgb2gray_0/m_axis",
"bram_writer_0/s_axis",
"system_ila_0/SLOT_2_AXIS"
]
},
"img_conv_0_m_axis": {
"interface_ports": [
"img_conv_0/m_axis",
"packetizer_0/s_axis",
"system_ila_0/SLOT_1_AXIS"
]
}
},
"nets": {
"clk_wiz_0_clk_out1": {
"ports": [
"clk_wiz_0/clk_out1",
"led_blinker_0/clk",
"led_blinker_1/clk",
"led_blinker_2/clk",
"bram_writer_0/clk",
"system_ila_0/clk",
"proc_sys_reset_1/slowest_sync_clk",
"AXI4Stream_UART_0/clk_uart",
"AXI4Stream_UART_0/m00_axis_rx_aclk",
"AXI4Stream_UART_0/s00_axis_tx_aclk",
"img_conv_0/clk",
"depacketizer_0/clk",
"packetizer_0/clk",
"rgb2gray_0/clk"
]
},
"proc_sys_reset_0_peripheral_aresetn": {
"ports": [
"proc_sys_reset_1/peripheral_aresetn",
"led_blinker_0/aresetn",
"led_blinker_1/aresetn",
"led_blinker_2/aresetn",
"bram_writer_0/aresetn",
"system_ila_0/resetn",
"AXI4Stream_UART_0/m00_axis_rx_aresetn",
"AXI4Stream_UART_0/s00_axis_tx_aresetn",
"img_conv_0/aresetn",
"depacketizer_0/aresetn",
"packetizer_0/aresetn",
"rgb2gray_0/resetn"
]
},
"bram_writer_0_conv_data": {
"ports": [
"bram_writer_0/conv_data",
"system_ila_0/probe0",
"img_conv_0/conv_data"
]
},
"bram_writer_0_start_conv": {
"ports": [
"bram_writer_0/start_conv",
"system_ila_0/probe1",
"img_conv_0/start_conv"
]
},
"Net": {
"ports": [
"img_conv_0/conv_addr",
"system_ila_0/probe2",
"bram_writer_0/conv_addr"
]
},
"Net1": {
"ports": [
"img_conv_0/done_conv",
"system_ila_0/probe3",
"bram_writer_0/done_conv"
]
},
"bram_writer_0_write_ok": {
"ports": [
"bram_writer_0/write_ok",
"led_blinker_0/start_blink"
]
},
"bram_writer_0_overflow": {
"ports": [
"bram_writer_0/overflow",
"led_blinker_2/start_blink"
]
},
"bram_writer_0_underflow": {
"ports": [
"bram_writer_0/underflow",
"led_blinker_1/start_blink"
]
},
"led_blinker_0_led": {
"ports": [
"led_blinker_0/led",
"led_ok"
]
},
"led_blinker_1_led": {
"ports": [
"led_blinker_1/led",
"led_uf"
]
},
"led_blinker_2_led": {
"ports": [
"led_blinker_2/led",
"led_of"
]
},
"sys_clock_1": {
"ports": [
"sys_clock",
"clk_wiz_0/clk_in1"
]
},
"clk_wiz_0_locked": {
"ports": [
"clk_wiz_0/locked",
"proc_sys_reset_1/dcm_locked"
]
},
"reset_1": {
"ports": [
"reset",
"proc_sys_reset_1/ext_reset_in",
"clk_wiz_0/reset"
]
},
"proc_sys_reset_1_peripheral_reset": {
"ports": [
"proc_sys_reset_1/peripheral_reset",
"AXI4Stream_UART_0/rst"
]
}
}
}
}