Davide
f014f8c341
- Removed obsolete GraphML file `pak_depak.bda` and UI file `bd_c9b29a54.ui`. - Updated `rgb2gray.vhd` to improve signal handling and state machine logic. - Created new Vivado project files for `depacketizer_test`, including testbench configuration. - Adjusted `pak_depak.xpr` to disable the FIFO module and set the top module correctly. - Updated `rgb2grey_test.xpr` to modify simulation launch settings.
116 lines
3.5 KiB
VHDL
116 lines
3.5 KiB
VHDL
LIBRARY ieee;
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USE ieee.std_logic_1164.ALL;
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USE ieee.numeric_std.ALL;
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ENTITY packetizer IS
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GENERIC (
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HEADER : INTEGER := 16#FF#;
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FOOTER : INTEGER := 16#F1#
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);
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PORT (
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clk : IN STD_LOGIC;
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aresetn : IN STD_LOGIC;
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s_axis_tdata : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
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s_axis_tvalid : IN STD_LOGIC;
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s_axis_tready : OUT STD_LOGIC;
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s_axis_tlast : IN STD_LOGIC;
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m_axis_tdata : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
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m_axis_tvalid : OUT STD_LOGIC;
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m_axis_tready : IN STD_LOGIC
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);
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END ENTITY packetizer;
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ARCHITECTURE rtl OF packetizer IS
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TYPE state_type IS (SENDING_HEADER, STREAMING, SENDING_FOOTER);
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SIGNAL state : state_type := SENDING_HEADER;
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SIGNAL data_buffer : STD_LOGIC_VECTOR(7 DOWNTO 0);
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SIGNAL s_axis_tready_int : STD_LOGIC;
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SIGNAL m_axis_tvalid_int : STD_LOGIC;
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SIGNAL trigger : STD_LOGIC := '0';
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BEGIN
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s_axis_tready <= s_axis_tready_int;
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m_axis_tvalid <= m_axis_tvalid_int;
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PROCESS (clk)
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BEGIN
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IF rising_edge(clk) THEN
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IF aresetn = '0' THEN
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state <= SENDING_HEADER;
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data_buffer <= (OTHERS => '0');
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m_axis_tdata <= (OTHERS => '0');
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s_axis_tready_int <= '0';
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m_axis_tvalid_int <= '0';
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ELSE
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-- Input data - slave
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s_axis_tready_int <= m_axis_tready;
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IF s_axis_tvalid = '1' AND s_axis_tready_int = '1' THEN
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data_buffer <= s_axis_tdata;
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END IF;
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-- Output data - master
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IF m_axis_tready = '1' THEN
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m_axis_tvalid_int <= '0';
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END IF;
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IF trigger = '1' AND (m_axis_tvalid_int = '0' OR m_axis_tready = '1') THEN
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m_axis_tvalid_int <= '1';
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m_axis_tdata <= data_buffer;
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trigger <= '0';
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END IF;
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-- State machine for packetization
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CASE state IS
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WHEN SENDING_HEADER =>
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IF s_axis_tvalid = '1' AND s_axis_tready_int = '1' THEN
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m_axis_tdata <= STD_LOGIC_VECTOR(to_unsigned(HEADER, 8)); -- Prepare header
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m_axis_tvalid_int <= '1'; --Send header
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trigger <= '1';
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state <= STREAMING;
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END IF;
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WHEN STREAMING =>
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IF s_axis_tvalid = '1' AND s_axis_tready_int = '1' THEN
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IF s_axis_tlast = '1' THEN
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s_axis_tready_int <= '0'; -- Block the slave interface to avoid data loss
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state <= SENDING_FOOTER;
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END IF;
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trigger <= '1';
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END IF;
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WHEN SENDING_FOOTER =>
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IF m_axis_tvalid_int = '0' OR m_axis_tready = '1' THEN
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s_axis_tready_int <= '0'; -- Block the slave interface to avoid data loss
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data_buffer <= STD_LOGIC_VECTOR(to_unsigned(FOOTER, 8)); -- Send footer
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m_axis_tvalid_int <= '1';
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trigger <= '1';
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state <= SENDING_HEADER;
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END IF;
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END CASE;
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END IF;
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END IF;
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END PROCESS;
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END ARCHITECTURE rtl; |