Davide f363f09506 Implement finite state machine in bram_writer for improved data handling and convolution control

2025-04-16 13:02:48 +02:00

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cons

Reorder reset, sys_clock and USB UART ports in lab_2_wrapper and update synthesis flow mode in lab_2.bd

2025-04-09 11:40:21 +02:00

ip/AXI4-Stream_UART

Add new AXI4-Stream UART IP and update .gitignore for Lab2 files

2025-03-31 18:35:29 +02:00

sim

Refactor image processing components: update bit depth in rgb2gray and divider_by_3, enhance img_conv architecture, and adjust simulation settings

2025-04-11 18:06:02 +02:00

src

Implement finite state machine in bram_writer for improved data handling and convolution control

2025-04-16 13:02:48 +02:00

test

Add new AXI4-Stream UART IP and update .gitignore for Lab2 files

2025-03-31 18:35:29 +02:00

vivado

Add pak_depak design files and update project references

2025-04-15 17:27:38 +02:00