36 lines
1.4 KiB
Markdown
36 lines
1.4 KiB
Markdown
# AXI4-Stream SPI Master
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This module implements an SPI Master.
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This module is based on the "SPI Master Lightweight" module on OpenCores, freely
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downloadable from [here](https://opencores.org/projects/spi_master_lightweight),
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with minimal modifications to add AXI4-Stream interfaces and reset signal.
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The cs signal is automatically asserted half clock cycle (SCLK) before the first
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rising edge of SCLK (with CPOL=0 and CPHA=0) and deasserted half clock cycle
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(SCLK) after the last falling edge of SCLK (with CPOL=0 and CPHA=0).
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## Generics
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* c_clkfreq: aclk frequency (in Hz)
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* c_sclkfreq: desired sclk frequency (in Hz); must be <= c_clkfreq/8
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* c_cpol: SPI CPOL
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* c_cpha: SPI CPHA
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## Slave AXI4-Stream
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Data passed to this module through this interface are serialized and send
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through the MOSI port, MSbit first.
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The CS signal will go low at the beginning of the transfer and will stay low
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until this module has data to send. In other words, keep s_axis_tvalid high and
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keep sending data if you want an uninterrupted transfer with CS always low.
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## Master AXI4-Stream
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Data received by this module will be sent through this interface. Note that this
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interface lacks a tready signal.
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For how the SPI protocol works, data can be received only when data is
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transmitted by the master so, if you want to receive N bytes, you have to send
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N bytes (by writing on the Slave AXI4-Stream interface).
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