Add PulseWidthModulator and update KittCarPWM; adjust simulation launch time
This commit is contained in:
@@ -47,7 +47,7 @@
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<Option Name="IPStaticSourceDir" Val="$PIPUSERFILESDIR/ipstatic"/>
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<Option Name="IPStaticSourceDir" Val="$PIPUSERFILESDIR/ipstatic"/>
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<Option Name="EnableBDX" Val="FALSE"/>
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<Option Name="EnableBDX" Val="FALSE"/>
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<Option Name="DSABoardId" Val="basys3"/>
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<Option Name="DSABoardId" Val="basys3"/>
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<Option Name="WTXSimLaunchSim" Val="10"/>
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<Option Name="WTXSimLaunchSim" Val="12"/>
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<Option Name="WTModelSimLaunchSim" Val="0"/>
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<Option Name="WTModelSimLaunchSim" Val="0"/>
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<Option Name="WTQuestaLaunchSim" Val="0"/>
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<Option Name="WTQuestaLaunchSim" Val="0"/>
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<Option Name="WTIesLaunchSim" Val="0"/>
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<Option Name="WTIesLaunchSim" Val="0"/>
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@@ -1,12 +1,11 @@
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---------- DEFAULT LIBRARY ---------
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---------- DEFAULT LIBRARY ---------
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library IEEE;
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LIBRARY IEEE;
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use IEEE.STD_LOGIC_1164.all;
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USE IEEE.STD_LOGIC_1164.ALL;
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use IEEE.NUMERIC_STD.ALL;
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USE IEEE.NUMERIC_STD.ALL;
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------------------------------------
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------------------------------------
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entity KittCarPWM is
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ENTITY KittCarPWM IS
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Generic (
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GENERIC (
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CLK_PERIOD_NS : POSITIVE RANGE 1 TO 100 := 10; -- clk period in nanoseconds
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CLK_PERIOD_NS : POSITIVE RANGE 1 TO 100 := 10; -- clk period in nanoseconds
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MIN_KITT_CAR_STEP_MS : POSITIVE RANGE 1 TO 2000 := 1; -- Minimum step period in milliseconds (i.e., value in milliseconds of Delta_t)
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MIN_KITT_CAR_STEP_MS : POSITIVE RANGE 1 TO 2000 := 1; -- Minimum step period in milliseconds (i.e., value in milliseconds of Delta_t)
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@@ -15,7 +14,7 @@ entity KittCarPWM is
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TAIL_LENGTH : INTEGER RANGE 1 TO 16 := 4 -- Tail length
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TAIL_LENGTH : INTEGER RANGE 1 TO 16 := 4 -- Tail length
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);
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);
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Port (
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PORT (
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------- Reset/Clock --------
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------- Reset/Clock --------
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reset : IN STD_LOGIC;
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reset : IN STD_LOGIC;
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@@ -23,15 +22,112 @@ entity KittCarPWM is
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----------------------------
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----------------------------
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-------- LEDs/SWs ----------
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-------- LEDs/SWs ----------
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sw : IN STD_LOGIC_VECTOR(NUM_OF_SWS-1 downto 0); -- Switches avaiable on Basys3
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sw : IN STD_LOGIC_VECTOR(NUM_OF_SWS - 1 DOWNTO 0); -- Switches avaiable on Basys3
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leds : OUT STD_LOGIC_VECTOR(NUM_OF_LEDS-1 downto 0) -- LEDs avaiable on Basys3
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led : OUT STD_LOGIC_VECTOR(NUM_OF_LEDS - 1 DOWNTO 0) -- LEDs avaiable on Basys3
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----------------------------
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----------------------------
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);
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);
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end KittCarPWM;
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END KittCarPWM;
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architecture Behavioral of KittCarPWM is
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ARCHITECTURE Behavioral OF KittCarPWM IS
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COMPONENT PulseWidthModulator
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GENERIC (
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BIT_LENGTH : INTEGER RANGE 1 TO 16;
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T_ON_INIT : POSITIVE;
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PERIOD_INIT : POSITIVE;
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PWM_INIT : STD_LOGIC
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);
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PORT (
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reset : IN STD_LOGIC;
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clk : IN STD_LOGIC;
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begin
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Ton : IN STD_LOGIC_VECTOR(BIT_LENGTH - 1 DOWNTO 0);
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Period : IN STD_LOGIC_VECTOR(BIT_LENGTH - 1 DOWNTO 0);
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PWM : OUT STD_LOGIC
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);
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END COMPONENT;
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end Behavioral;
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TYPE led_reg IS ARRAY (TAIL_LENGTH - 1 DOWNTO 0) OF INTEGER RANGE 0 TO led'HIGH;
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CONSTANT MIN_KITT_CAR_STEP_NS : UNSIGNED(46 DOWNTO 0) := to_unsigned(MIN_KITT_CAR_STEP_MS * 1000000, 47);
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CONSTANT BIT_LENGTH : INTEGER RANGE 1 TO 16 := 8;
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SIGNAL leds_sr : led_reg := (OTHERS => 0);
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SIGNAL leds_pwm : STD_LOGIC_VECTOR(TAIL_LENGTH - 1 DOWNTO 0) := (OTHERS => '0');
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SIGNAL led_sig : STD_LOGIC_VECTOR(NUM_OF_LEDS - 1 DOWNTO 0) := (OTHERS => '0');
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SIGNAL n_period : UNSIGNED(NUM_OF_SWS DOWNTO 0) := to_unsigned(1, NUM_OF_SWS + 1);
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SIGNAL up : STD_LOGIC := '1';
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BEGIN
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-- Instantiate the PWM
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PWM : FOR i IN 1 TO TAIL_LENGTH GENERATE
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BEGIN
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PWM : PulseWidthModulator
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GENERIC MAP(
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BIT_LENGTH => BIT_LENGTH,
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T_ON_INIT => 64,
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PERIOD_INIT => 128,
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PWM_INIT => '0'
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)
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PORT MAP(
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reset => reset,
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clk => clk,
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Ton => STD_LOGIC_VECTOR(to_unsigned(i, BIT_LENGTH)),
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Period => STD_LOGIC_VECTOR(to_unsigned(TAIL_LENGTH - 1, BIT_LENGTH)),
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PWM => leds_pwm(i - 1)
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);
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END GENERATE;
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-- Sincronous logic
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PROCESS (clk, reset)
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VARIABLE counter : UNSIGNED(46 DOWNTO 0) := (OTHERS => '0');
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BEGIN
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IF reset = '1' THEN
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leds_sr <= (OTHERS => 0);
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led_sig <= (OTHERS => '0');
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counter := (OTHERS => '0');
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ELSIF rising_edge(clk) THEN
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-- Kitt logic
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IF leds_sr(TAIL_LENGTH - 1) = 15 THEN
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up <= '0';
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ELSIF leds_sr(TAIL_LENGTH - 1) = 0 THEN
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up <= '1';
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END IF;
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-- Increment the counter
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counter := counter + to_unsigned(CLK_PERIOD_NS, counter'LENGTH);
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-- Calculate the number of periods
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IF counter >= (MIN_KITT_CAR_STEP_NS * n_period) THEN
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-- Shift the leds
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IF up = '1' THEN
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leds_sr <= (leds_sr(TAIL_LENGTH - 1) + 1) & leds_sr(TAIL_LENGTH - 2 DOWNTO 0);
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ELSIF up = '0' THEN
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leds_sr <= (leds_sr(TAIL_LENGTH - 1) - 1) & leds_sr(TAIL_LENGTH - 2 DOWNTO 0);
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END IF;
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-- Reset leg_sig
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led_sig <= (OTHERS => '0');
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-- Assign the leds
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FOR i IN 0 TO TAIL_LENGTH - 1 LOOP
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led_sig(leds_sr(i)) <= leds_pwm(i);
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END LOOP;
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-- Reset the counter
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counter := (OTHERS => '0');
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END IF;
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END IF;
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END PROCESS;
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-- Handle the switch
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PROCESS (sw)
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BEGIN
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n_period <= unsigned('0' & sw) + 1;
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END PROCESS;
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led <= led_sig;
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END Behavioral;
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83
LAB1/src/PulseWidthModulator.vhd
Normal file
83
LAB1/src/PulseWidthModulator.vhd
Normal file
@@ -0,0 +1,83 @@
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----------------------------------------------------------------------------------
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-- Company:
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-- Engineer:
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--
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-- Create Date: 07.03.2025 15:23:11
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-- Design Name:
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-- Module Name: PulseWidthModulator - Behavioral
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-- Project Name:
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-- Target Devices:
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-- Tool Versions:
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-- Description:
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--
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-- Dependencies:
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--
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-- Revision:
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-- Revision 0.01 - File Created
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-- Additional Comments:
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--
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----------------------------------------------------------------------------------
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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-- Uncomment the following library declaration if using
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-- arithmetic functions with Signed or Unsigned values
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use IEEE.NUMERIC_STD.ALL;
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-- Uncomment the following library declaration if instantiating
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-- any Xilinx leaf cells in this code.
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--library UNISIM;
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--use UNISIM.VComponents.all;
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entity PulseWidthModulator is
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Generic(
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BIT_LENGTH : INTEGER RANGE 1 to 16 := 8;
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T_ON_INIT : POSITIVE := 64;
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PERIOD_INIT : POSITIVE := 128;
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PWM_INIT : STD_LOGIC := '0'
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);
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Port (
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reset : IN STD_LOGIC;
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clk : IN STD_LOGIC;
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Ton : IN std_logic_vector(BIT_LENGTH-1 downto 0);
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Period : IN std_logic_vector(BIT_LENGTH-1 downto 0);
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PWM : OUT std_logic
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);
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end PulseWidthModulator;
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architecture Behavioral of PulseWidthModulator is
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signal counter : unsigned(BIT_LENGTH-1 downto 0) := (others => '0');
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signal pwm_out : std_logic;
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begin
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process(clk, reset)
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begin
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if reset = '1' then
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counter <= (others => '0');
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pwm_out <= '0'; -- Assicura PWM spento al reset
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elsif rising_edge(clk) then
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if counter = unsigned(period) then
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counter <= (others => '0'); -- Reset counter
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else
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counter <= counter + 1; -- Incrementa il counter
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end if;
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-- Accendi il PWM all'inizio di ogni ciclo
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if counter = 0 then
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pwm_out <= '1';
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end if;
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-- Spegni il PWM quando il contatore raggiunge Ton
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if counter = unsigned(Ton) then
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pwm_out <= '0';
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end if;
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end if;
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end process;
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PWM <= pwm_out; -- Output PWM
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end Behavioral;
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213
LAB1/vivado/lab1_kit_car_pwm/lab1_kit_car_pwm.xpr
Normal file
213
LAB1/vivado/lab1_kit_car_pwm/lab1_kit_car_pwm.xpr
Normal file
@@ -0,0 +1,213 @@
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<?xml version="1.0" encoding="UTF-8"?>
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<!-- Product Version: Vivado v2020.2 (64-bit) -->
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<!-- -->
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<!-- Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. -->
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<Project Version="7" Minor="54" Path="C:/DESD/LAB1/vivado/lab1_kit_car_pwm/lab1_kit_car_pwm.xpr">
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<DefaultLaunch Dir="$PRUNDIR"/>
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<Configuration>
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<Option Name="Id" Val="197059de45624c67b2900cf4ced29fd2"/>
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<Option Name="Part" Val="xc7a35tcpg236-1"/>
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<Option Name="CompiledLibDir" Val="$PCACHEDIR/compile_simlib"/>
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<Option Name="CompiledLibDirXSim" Val=""/>
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<Option Name="CompiledLibDirModelSim" Val="$PCACHEDIR/compile_simlib/modelsim"/>
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<Option Name="CompiledLibDirQuesta" Val="$PCACHEDIR/compile_simlib/questa"/>
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<Option Name="CompiledLibDirIES" Val="$PCACHEDIR/compile_simlib/ies"/>
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<Option Name="CompiledLibDirXcelium" Val="$PCACHEDIR/compile_simlib/xcelium"/>
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<Option Name="CompiledLibDirVCS" Val="$PCACHEDIR/compile_simlib/vcs"/>
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<Option Name="CompiledLibDirRiviera" Val="$PCACHEDIR/compile_simlib/riviera"/>
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<Option Name="CompiledLibDirActivehdl" Val="$PCACHEDIR/compile_simlib/activehdl"/>
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<Option Name="SimulatorInstallDirModelSim" Val=""/>
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<Option Name="SimulatorInstallDirQuesta" Val=""/>
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<Option Name="SimulatorInstallDirIES" Val=""/>
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<Option Name="SimulatorInstallDirXcelium" Val=""/>
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<Option Name="SimulatorInstallDirVCS" Val=""/>
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<Option Name="SimulatorInstallDirRiviera" Val=""/>
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<Option Name="SimulatorInstallDirActiveHdl" Val=""/>
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<Option Name="SimulatorGccInstallDirModelSim" Val=""/>
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<Option Name="SimulatorGccInstallDirQuesta" Val=""/>
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<Option Name="SimulatorGccInstallDirIES" Val=""/>
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<Option Name="SimulatorGccInstallDirXcelium" Val=""/>
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<Option Name="SimulatorGccInstallDirVCS" Val=""/>
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<Option Name="SimulatorGccInstallDirRiviera" Val=""/>
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<Option Name="SimulatorGccInstallDirActiveHdl" Val=""/>
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<Option Name="TargetLanguage" Val="VHDL"/>
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<Option Name="BoardPart" Val=""/>
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<Option Name="BoardPartRepoPaths" Val="$PPRDIR/../../../../Users/david/AppData/Roaming/Xilinx/Vivado/2020.2/xhub/board_store/xilinx_board_store"/>
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<Option Name="ActiveSimSet" Val="sim_1"/>
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<Option Name="DefaultLib" Val="xil_defaultlib"/>
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<Option Name="ProjectType" Val="Default"/>
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<Option Name="IPOutputRepo" Val="$PCACHEDIR/ip"/>
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<Option Name="IPDefaultOutputPath" Val="$PGENDIR/sources_1"/>
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<Option Name="IPCachePermission" Val="read"/>
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<Option Name="IPCachePermission" Val="write"/>
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<Option Name="EnableCoreContainer" Val="FALSE"/>
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<Option Name="CreateRefXciForCoreContainers" Val="FALSE"/>
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<Option Name="IPUserFilesDir" Val="$PIPUSERFILESDIR"/>
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||||||
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<Option Name="IPStaticSourceDir" Val="$PIPUSERFILESDIR/ipstatic"/>
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<Option Name="EnableBDX" Val="FALSE"/>
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<Option Name="WTXSimLaunchSim" Val="0"/>
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||||||
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<Option Name="WTModelSimLaunchSim" Val="0"/>
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||||||
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<Option Name="WTQuestaLaunchSim" Val="0"/>
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<Option Name="WTIesLaunchSim" Val="0"/>
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||||||
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<Option Name="WTVcsLaunchSim" Val="0"/>
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||||||
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<Option Name="WTRivieraLaunchSim" Val="0"/>
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||||||
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<Option Name="WTActivehdlLaunchSim" Val="0"/>
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||||||
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<Option Name="WTXSimExportSim" Val="0"/>
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||||||
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<Option Name="WTModelSimExportSim" Val="0"/>
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||||||
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<Option Name="WTQuestaExportSim" Val="0"/>
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||||||
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<Option Name="WTIesExportSim" Val="0"/>
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||||||
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<Option Name="WTVcsExportSim" Val="0"/>
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||||||
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<Option Name="WTRivieraExportSim" Val="0"/>
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||||||
|
<Option Name="WTActivehdlExportSim" Val="0"/>
|
||||||
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<Option Name="GenerateIPUpgradeLog" Val="TRUE"/>
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||||||
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<Option Name="XSimRadix" Val="hex"/>
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||||||
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<Option Name="XSimTimeUnit" Val="ns"/>
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||||||
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<Option Name="XSimArrayDisplayLimit" Val="1024"/>
|
||||||
|
<Option Name="XSimTraceLimit" Val="65536"/>
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||||||
|
<Option Name="SimTypes" Val="rtl"/>
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||||||
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<Option Name="SimTypes" Val="bfm"/>
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||||||
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<Option Name="SimTypes" Val="tlm"/>
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||||||
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<Option Name="SimTypes" Val="tlm_dpi"/>
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||||||
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<Option Name="MEMEnableMemoryMapGeneration" Val="TRUE"/>
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||||||
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<Option Name="DcpsUptoDate" Val="TRUE"/>
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||||||
|
</Configuration>
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||||||
|
<FileSets Version="1" Minor="31">
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||||||
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<FileSet Name="sources_1" Type="DesignSrcs" RelSrcDir="$PSRCDIR/sources_1" RelGenDir="$PGENDIR/sources_1">
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||||||
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<Filter Type="Srcs"/>
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||||||
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<File Path="$PPRDIR/../../src/PulseWidthModulator.vhd">
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||||||
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<FileInfo>
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||||||
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<Attr Name="UsedIn" Val="synthesis"/>
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||||||
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<Attr Name="UsedIn" Val="simulation"/>
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||||||
|
</FileInfo>
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||||||
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</File>
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||||||
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<File Path="$PPRDIR/../../src/KittCarPWM.vhd">
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||||||
|
<FileInfo>
|
||||||
|
<Attr Name="UsedIn" Val="synthesis"/>
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||||||
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<Attr Name="UsedIn" Val="simulation"/>
|
||||||
|
</FileInfo>
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||||||
|
</File>
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||||||
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<Config>
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||||||
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<Option Name="DesignMode" Val="RTL"/>
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||||||
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<Option Name="TopModule" Val="KittCarPWM"/>
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||||||
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<Option Name="TopAutoSet" Val="TRUE"/>
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||||||
|
</Config>
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||||||
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</FileSet>
|
||||||
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<FileSet Name="constrs_1" Type="Constrs" RelSrcDir="$PSRCDIR/constrs_1" RelGenDir="$PGENDIR/constrs_1">
|
||||||
|
<Filter Type="Constrs"/>
|
||||||
|
<File Path="$PPRDIR/../../cons/basys3_master.xdc">
|
||||||
|
<FileInfo>
|
||||||
|
<Attr Name="UsedIn" Val="synthesis"/>
|
||||||
|
<Attr Name="UsedIn" Val="implementation"/>
|
||||||
|
</FileInfo>
|
||||||
|
</File>
|
||||||
|
<Config>
|
||||||
|
<Option Name="ConstrsType" Val="XDC"/>
|
||||||
|
</Config>
|
||||||
|
</FileSet>
|
||||||
|
<FileSet Name="sim_1" Type="SimulationSrcs" RelSrcDir="$PSRCDIR/sim_1" RelGenDir="$PGENDIR/sim_1">
|
||||||
|
<Config>
|
||||||
|
<Option Name="DesignMode" Val="RTL"/>
|
||||||
|
<Option Name="TopModule" Val="KittCarPWM"/>
|
||||||
|
<Option Name="TopLib" Val="xil_defaultlib"/>
|
||||||
|
<Option Name="TopAutoSet" Val="TRUE"/>
|
||||||
|
<Option Name="TransportPathDelay" Val="0"/>
|
||||||
|
<Option Name="TransportIntDelay" Val="0"/>
|
||||||
|
<Option Name="SelectedSimModel" Val="rtl"/>
|
||||||
|
<Option Name="PamDesignTestbench" Val=""/>
|
||||||
|
<Option Name="PamDutBypassFile" Val="xil_dut_bypass"/>
|
||||||
|
<Option Name="PamSignalDriverFile" Val="xil_bypass_driver"/>
|
||||||
|
<Option Name="PamPseudoTop" Val="pseudo_tb"/>
|
||||||
|
<Option Name="SrcSet" Val="sources_1"/>
|
||||||
|
</Config>
|
||||||
|
</FileSet>
|
||||||
|
<FileSet Name="utils_1" Type="Utils" RelSrcDir="$PSRCDIR/utils_1" RelGenDir="$PGENDIR/utils_1">
|
||||||
|
<Filter Type="Utils"/>
|
||||||
|
<Config>
|
||||||
|
<Option Name="TopAutoSet" Val="TRUE"/>
|
||||||
|
</Config>
|
||||||
|
</FileSet>
|
||||||
|
</FileSets>
|
||||||
|
<Simulators>
|
||||||
|
<Simulator Name="XSim">
|
||||||
|
<Option Name="Description" Val="Vivado Simulator"/>
|
||||||
|
<Option Name="CompiledLib" Val="0"/>
|
||||||
|
</Simulator>
|
||||||
|
<Simulator Name="ModelSim">
|
||||||
|
<Option Name="Description" Val="ModelSim Simulator"/>
|
||||||
|
</Simulator>
|
||||||
|
<Simulator Name="Questa">
|
||||||
|
<Option Name="Description" Val="Questa Advanced Simulator"/>
|
||||||
|
</Simulator>
|
||||||
|
<Simulator Name="Riviera">
|
||||||
|
<Option Name="Description" Val="Riviera-PRO Simulator"/>
|
||||||
|
</Simulator>
|
||||||
|
<Simulator Name="ActiveHDL">
|
||||||
|
<Option Name="Description" Val="Active-HDL Simulator"/>
|
||||||
|
</Simulator>
|
||||||
|
</Simulators>
|
||||||
|
<Runs Version="1" Minor="15">
|
||||||
|
<Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7a35tcpg236-1" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" Dir="$PRUNDIR/synth_1" IncludeInArchive="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/synth_1">
|
||||||
|
<Strategy Version="1" Minor="2">
|
||||||
|
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2020">
|
||||||
|
<Desc>Vivado Synthesis Defaults</Desc>
|
||||||
|
</StratHandle>
|
||||||
|
<Step Id="synth_design"/>
|
||||||
|
</Strategy>
|
||||||
|
<GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
|
||||||
|
<ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2020"/>
|
||||||
|
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
|
||||||
|
<RQSFiles/>
|
||||||
|
</Run>
|
||||||
|
<Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7a35tcpg236-1" ConstrsSet="constrs_1" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" Dir="$PRUNDIR/impl_1" SynthRun="synth_1" IncludeInArchive="true" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/impl_1">
|
||||||
|
<Strategy Version="1" Minor="2">
|
||||||
|
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2020">
|
||||||
|
<Desc>Default settings for Implementation.</Desc>
|
||||||
|
</StratHandle>
|
||||||
|
<Step Id="init_design"/>
|
||||||
|
<Step Id="opt_design"/>
|
||||||
|
<Step Id="power_opt_design"/>
|
||||||
|
<Step Id="place_design"/>
|
||||||
|
<Step Id="post_place_power_opt_design"/>
|
||||||
|
<Step Id="phys_opt_design"/>
|
||||||
|
<Step Id="route_design"/>
|
||||||
|
<Step Id="post_route_phys_opt_design"/>
|
||||||
|
<Step Id="write_bitstream"/>
|
||||||
|
</Strategy>
|
||||||
|
<GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
|
||||||
|
<ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2020"/>
|
||||||
|
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
|
||||||
|
<RQSFiles/>
|
||||||
|
</Run>
|
||||||
|
</Runs>
|
||||||
|
<Board/>
|
||||||
|
<DashboardSummary Version="1" Minor="0">
|
||||||
|
<Dashboards>
|
||||||
|
<Dashboard Name="default_dashboard">
|
||||||
|
<Gadgets>
|
||||||
|
<Gadget Name="drc_1" Type="drc" Version="1" Row="2" Column="0">
|
||||||
|
<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_drc_0 "/>
|
||||||
|
</Gadget>
|
||||||
|
<Gadget Name="methodology_1" Type="methodology" Version="1" Row="2" Column="1">
|
||||||
|
<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_methodology_0 "/>
|
||||||
|
</Gadget>
|
||||||
|
<Gadget Name="power_1" Type="power" Version="1" Row="1" Column="0">
|
||||||
|
<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_power_0 "/>
|
||||||
|
</Gadget>
|
||||||
|
<Gadget Name="timing_1" Type="timing" Version="1" Row="0" Column="1">
|
||||||
|
<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_timing_summary_0 "/>
|
||||||
|
</Gadget>
|
||||||
|
<Gadget Name="utilization_1" Type="utilization" Version="1" Row="0" Column="0">
|
||||||
|
<GadgetParam Name="REPORTS" Type="string_list" Value="synth_1#synth_1_synth_report_utilization_0 "/>
|
||||||
|
<GadgetParam Name="RUN.STEP" Type="string" Value="synth_design"/>
|
||||||
|
<GadgetParam Name="RUN.TYPE" Type="string" Value="synthesis"/>
|
||||||
|
</Gadget>
|
||||||
|
<Gadget Name="utilization_2" Type="utilization" Version="1" Row="1" Column="1">
|
||||||
|
<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_place_report_utilization_0 "/>
|
||||||
|
</Gadget>
|
||||||
|
</Gadgets>
|
||||||
|
</Dashboard>
|
||||||
|
<CurrentDashboard>default_dashboard</CurrentDashboard>
|
||||||
|
</Dashboards>
|
||||||
|
</DashboardSummary>
|
||||||
|
</Project>
|
||||||
Reference in New Issue
Block a user