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Add PulseWidthModulator and update KittCarPWM; adjust simulation launch time

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This commit is contained in:
Davide Cavagnola
2025-03-21 16:20:55 +01:00
parent 35426ab1cf
commit 038ea73291
4 changed files with 418 additions and 26 deletions
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2
LAB0/vivado/lab0_pulse_width_modulator/lab0_pulse_width_modulator.xpr
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@@ -47,7 +47,7 @@
<Option Name="IPStaticSourceDir" Val="$PIPUSERFILESDIR/ipstatic"/>
<Option Name="EnableBDX" Val="FALSE"/>
<Option Name="DSABoardId" Val="basys3"/>
<Option Name="WTXSimLaunchSim" Val="10"/>
<Option Name="WTXSimLaunchSim" Val="12"/>
<Option Name="WTModelSimLaunchSim" Val="0"/>
<Option Name="WTQuestaLaunchSim" Val="0"/>
<Option Name="WTIesLaunchSim" Val="0"/>

146
LAB1/src/KittCarPWM.vhd
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@@ -1,37 +1,133 @@
---------- DEFAULT LIBRARY ---------
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.ALL;
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.NUMERIC_STD.ALL;
------------------------------------
entity KittCarPWM is
Generic (
ENTITY KittCarPWM IS
GENERIC (
CLK_PERIOD_NS : POSITIVE RANGE 1 TO 100 := 10; -- clk period in nanoseconds
MIN_KITT_CAR_STEP_MS : POSITIVE RANGE 1 TO 2000 := 1; -- Minimum step period in milliseconds (i.e., value in milliseconds of Delta_t)
CLK_PERIOD_NS : POSITIVE RANGE 1 TO 100 := 10; -- clk period in nanoseconds
MIN_KITT_CAR_STEP_MS : POSITIVE RANGE 1 TO 2000 := 1; -- Minimum step period in milliseconds (i.e., value in milliseconds of Delta_t)
NUM_OF_SWS : INTEGER RANGE 1 TO 16 := 16; -- Number of input switches
NUM_OF_LEDS : INTEGER RANGE 1 TO 16 := 16; -- Number of output LEDs
NUM_OF_SWS : INTEGER RANGE 1 TO 16 := 16; -- Number of input switches
NUM_OF_LEDS : INTEGER RANGE 1 TO 16 := 16; -- Number of output LEDs
TAIL_LENGTH : INTEGER RANGE 1 TO 16 := 4 -- Tail length
);
PORT (
TAIL_LENGTH : INTEGER RANGE 1 TO 16 := 4 -- Tail length
);
Port (
------- Reset/Clock --------
reset : IN STD_LOGIC;
clk : IN STD_LOGIC;
----------------------------
------- Reset/Clock --------
reset : IN STD_LOGIC;
clk : IN STD_LOGIC;
----------------------------
-------- LEDs/SWs ----------
sw : IN STD_LOGIC_VECTOR(NUM_OF_SWS - 1 DOWNTO 0); -- Switches avaiable on Basys3
led : OUT STD_LOGIC_VECTOR(NUM_OF_LEDS - 1 DOWNTO 0) -- LEDs avaiable on Basys3
----------------------------
-------- LEDs/SWs ----------
sw : IN STD_LOGIC_VECTOR(NUM_OF_SWS-1 downto 0); -- Switches avaiable on Basys3
leds : OUT STD_LOGIC_VECTOR(NUM_OF_LEDS-1 downto 0) -- LEDs avaiable on Basys3
----------------------------
);
END KittCarPWM;
);
end KittCarPWM;
ARCHITECTURE Behavioral OF KittCarPWM IS
COMPONENT PulseWidthModulator
GENERIC (
BIT_LENGTH : INTEGER RANGE 1 TO 16;
T_ON_INIT : POSITIVE;
PERIOD_INIT : POSITIVE;
PWM_INIT : STD_LOGIC
);
PORT (
reset : IN STD_LOGIC;
clk : IN STD_LOGIC;
architecture Behavioral of KittCarPWM is
Ton : IN STD_LOGIC_VECTOR(BIT_LENGTH - 1 DOWNTO 0);
Period : IN STD_LOGIC_VECTOR(BIT_LENGTH - 1 DOWNTO 0);
PWM : OUT STD_LOGIC
);
END COMPONENT;
begin
TYPE led_reg IS ARRAY (TAIL_LENGTH - 1 DOWNTO 0) OF INTEGER RANGE 0 TO led'HIGH;
end Behavioral;
CONSTANT MIN_KITT_CAR_STEP_NS : UNSIGNED(46 DOWNTO 0) := to_unsigned(MIN_KITT_CAR_STEP_MS * 1000000, 47);
CONSTANT BIT_LENGTH : INTEGER RANGE 1 TO 16 := 8;
SIGNAL leds_sr : led_reg := (OTHERS => 0);
SIGNAL leds_pwm : STD_LOGIC_VECTOR(TAIL_LENGTH - 1 DOWNTO 0) := (OTHERS => '0');
SIGNAL led_sig : STD_LOGIC_VECTOR(NUM_OF_LEDS - 1 DOWNTO 0) := (OTHERS => '0');
SIGNAL n_period : UNSIGNED(NUM_OF_SWS DOWNTO 0) := to_unsigned(1, NUM_OF_SWS + 1);
SIGNAL up : STD_LOGIC := '1';
BEGIN
-- Instantiate the PWM
PWM : FOR i IN 1 TO TAIL_LENGTH GENERATE
BEGIN
PWM : PulseWidthModulator
GENERIC MAP(
BIT_LENGTH => BIT_LENGTH,
T_ON_INIT => 64,
PERIOD_INIT => 128,
PWM_INIT => '0'
)
PORT MAP(
reset => reset,
clk => clk,
Ton => STD_LOGIC_VECTOR(to_unsigned(i, BIT_LENGTH)),
Period => STD_LOGIC_VECTOR(to_unsigned(TAIL_LENGTH - 1, BIT_LENGTH)),
PWM => leds_pwm(i - 1)
);
END GENERATE;
-- Sincronous logic
PROCESS (clk, reset)
VARIABLE counter : UNSIGNED(46 DOWNTO 0) := (OTHERS => '0');
BEGIN
IF reset = '1' THEN
leds_sr <= (OTHERS => 0);
led_sig <= (OTHERS => '0');
counter := (OTHERS => '0');
ELSIF rising_edge(clk) THEN
-- Kitt logic
IF leds_sr(TAIL_LENGTH - 1) = 15 THEN
up <= '0';
ELSIF leds_sr(TAIL_LENGTH - 1) = 0 THEN
up <= '1';
END IF;
-- Increment the counter
counter := counter + to_unsigned(CLK_PERIOD_NS, counter'LENGTH);
-- Calculate the number of periods
IF counter >= (MIN_KITT_CAR_STEP_NS * n_period) THEN
-- Shift the leds
IF up = '1' THEN
leds_sr <= (leds_sr(TAIL_LENGTH - 1) + 1) & leds_sr(TAIL_LENGTH - 2 DOWNTO 0);
ELSIF up = '0' THEN
leds_sr <= (leds_sr(TAIL_LENGTH - 1) - 1) & leds_sr(TAIL_LENGTH - 2 DOWNTO 0);
END IF;
-- Reset leg_sig
led_sig <= (OTHERS => '0');
-- Assign the leds
FOR i IN 0 TO TAIL_LENGTH - 1 LOOP
led_sig(leds_sr(i)) <= leds_pwm(i);
END LOOP;
-- Reset the counter
counter := (OTHERS => '0');
END IF;
END IF;
END PROCESS;
-- Handle the switch
PROCESS (sw)
BEGIN
n_period <= unsigned('0' & sw) + 1;
END PROCESS;
led <= led_sig;
END Behavioral;

83
LAB1/src/PulseWidthModulator.vhd Normal file
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@@ -0,0 +1,83 @@
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 07.03.2025 15:23:11
-- Design Name:
-- Module Name: PulseWidthModulator - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity PulseWidthModulator is
Generic(
BIT_LENGTH : INTEGER RANGE 1 to 16 := 8;
T_ON_INIT : POSITIVE := 64;
PERIOD_INIT : POSITIVE := 128;
PWM_INIT : STD_LOGIC := '0'
);
Port (
reset : IN STD_LOGIC;
clk : IN STD_LOGIC;
Ton : IN std_logic_vector(BIT_LENGTH-1 downto 0);
Period : IN std_logic_vector(BIT_LENGTH-1 downto 0);
PWM : OUT std_logic
);
end PulseWidthModulator;
architecture Behavioral of PulseWidthModulator is
signal counter : unsigned(BIT_LENGTH-1 downto 0) := (others => '0');
signal pwm_out : std_logic;
begin
process(clk, reset)
begin
if reset = '1' then
counter <= (others => '0');
pwm_out <= '0'; -- Assicura PWM spento al reset
elsif rising_edge(clk) then
if counter = unsigned(period) then
counter <= (others => '0'); -- Reset counter
else
counter <= counter + 1; -- Incrementa il counter
end if;
-- Accendi il PWM all'inizio di ogni ciclo
if counter = 0 then
pwm_out <= '1';
end if;
-- Spegni il PWM quando il contatore raggiunge Ton
if counter = unsigned(Ton) then
pwm_out <= '0';
end if;
end if;
end process;
PWM <= pwm_out; -- Output PWM
end Behavioral;

213
LAB1/vivado/lab1_kit_car_pwm/lab1_kit_car_pwm.xpr Normal file
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@@ -0,0 +1,213 @@
<?xml version="1.0" encoding="UTF-8"?>
<!-- Product Version: Vivado v2020.2 (64-bit) -->
<!-- -->
<!-- Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. -->
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<DefaultLaunch Dir="$PRUNDIR"/>
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<Option Name="Part" Val="xc7a35tcpg236-1"/>
<Option Name="CompiledLibDir" Val="$PCACHEDIR/compile_simlib"/>
<Option Name="CompiledLibDirXSim" Val=""/>
<Option Name="CompiledLibDirModelSim" Val="$PCACHEDIR/compile_simlib/modelsim"/>
<Option Name="CompiledLibDirQuesta" Val="$PCACHEDIR/compile_simlib/questa"/>
<Option Name="CompiledLibDirIES" Val="$PCACHEDIR/compile_simlib/ies"/>
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<Option Name="CompiledLibDirRiviera" Val="$PCACHEDIR/compile_simlib/riviera"/>
<Option Name="CompiledLibDirActivehdl" Val="$PCACHEDIR/compile_simlib/activehdl"/>
<Option Name="SimulatorInstallDirModelSim" Val=""/>
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<Option Name="SimulatorGccInstallDirActiveHdl" Val=""/>
<Option Name="TargetLanguage" Val="VHDL"/>
<Option Name="BoardPart" Val=""/>
<Option Name="BoardPartRepoPaths" Val="$PPRDIR/../../../../Users/david/AppData/Roaming/Xilinx/Vivado/2020.2/xhub/board_store/xilinx_board_store"/>
<Option Name="ActiveSimSet" Val="sim_1"/>
<Option Name="DefaultLib" Val="xil_defaultlib"/>
<Option Name="ProjectType" Val="Default"/>
<Option Name="IPOutputRepo" Val="$PCACHEDIR/ip"/>
<Option Name="IPDefaultOutputPath" Val="$PGENDIR/sources_1"/>
<Option Name="IPCachePermission" Val="read"/>
<Option Name="IPCachePermission" Val="write"/>
<Option Name="EnableCoreContainer" Val="FALSE"/>
<Option Name="CreateRefXciForCoreContainers" Val="FALSE"/>
<Option Name="IPUserFilesDir" Val="$PIPUSERFILESDIR"/>
<Option Name="IPStaticSourceDir" Val="$PIPUSERFILESDIR/ipstatic"/>
<Option Name="EnableBDX" Val="FALSE"/>
<Option Name="WTXSimLaunchSim" Val="0"/>
<Option Name="WTModelSimLaunchSim" Val="0"/>
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<Option Name="WTIesLaunchSim" Val="0"/>
<Option Name="WTVcsLaunchSim" Val="0"/>
<Option Name="WTRivieraLaunchSim" Val="0"/>
<Option Name="WTActivehdlLaunchSim" Val="0"/>
<Option Name="WTXSimExportSim" Val="0"/>
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<Option Name="GenerateIPUpgradeLog" Val="TRUE"/>
<Option Name="XSimRadix" Val="hex"/>
<Option Name="XSimTimeUnit" Val="ns"/>
<Option Name="XSimArrayDisplayLimit" Val="1024"/>
<Option Name="XSimTraceLimit" Val="65536"/>
<Option Name="SimTypes" Val="rtl"/>
<Option Name="SimTypes" Val="bfm"/>
<Option Name="SimTypes" Val="tlm"/>
<Option Name="SimTypes" Val="tlm_dpi"/>
<Option Name="MEMEnableMemoryMapGeneration" Val="TRUE"/>
<Option Name="DcpsUptoDate" Val="TRUE"/>
</Configuration>
<FileSets Version="1" Minor="31">
<FileSet Name="sources_1" Type="DesignSrcs" RelSrcDir="$PSRCDIR/sources_1" RelGenDir="$PGENDIR/sources_1">
<Filter Type="Srcs"/>
<File Path="$PPRDIR/../../src/PulseWidthModulator.vhd">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PPRDIR/../../src/KittCarPWM.vhd">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<Config>
<Option Name="DesignMode" Val="RTL"/>
<Option Name="TopModule" Val="KittCarPWM"/>
<Option Name="TopAutoSet" Val="TRUE"/>
</Config>
</FileSet>
<FileSet Name="constrs_1" Type="Constrs" RelSrcDir="$PSRCDIR/constrs_1" RelGenDir="$PGENDIR/constrs_1">
<Filter Type="Constrs"/>
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</FileInfo>
</File>
<Config>
<Option Name="ConstrsType" Val="XDC"/>
</Config>
</FileSet>
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<Config>
<Option Name="DesignMode" Val="RTL"/>
<Option Name="TopModule" Val="KittCarPWM"/>
<Option Name="TopLib" Val="xil_defaultlib"/>
<Option Name="TopAutoSet" Val="TRUE"/>
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</Config>
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<Config>
<Option Name="TopAutoSet" Val="TRUE"/>
</Config>
</FileSet>
</FileSets>
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<Step Id="opt_design"/>
<Step Id="power_opt_design"/>
<Step Id="place_design"/>
<Step Id="post_place_power_opt_design"/>
<Step Id="phys_opt_design"/>
<Step Id="route_design"/>
<Step Id="post_route_phys_opt_design"/>
<Step Id="write_bitstream"/>
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<ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2020"/>
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<RQSFiles/>
</Run>
</Runs>
<Board/>
<DashboardSummary Version="1" Minor="0">
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<Dashboard Name="default_dashboard">
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</Gadget>
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</Gadget>
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</Gadget>
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</Project>