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Update .gitignore and enhance README.md; add new VHDL files for KittCarPWM, ShiftRegisters, and PulseWidthModulator

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This commit is contained in:
Davide Cavagnola
2025-03-20 15:05:27 +01:00
parent c29b83ba63
commit 163ad448f8
23 changed files with 669 additions and 279 deletions
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0
LAB1/basys3_master.xdc → LAB1/cons/basys3_master.xdc
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84
LAB1/lab1_kit_car/lab1_kit_car.srcs/sources_1/new/KittCar_v0.vhd
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@@ -1,84 +0,0 @@
-- File: KittCar_v0.vhd
-- Description: This file implements the KittCar entity
-- Known problem: The counter is not working properly
---------- DEFAULT LIBRARY ---------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.NUMERIC_STD.ALL;
------------------------------------
ENTITY KittCar IS
GENERIC (
CLK_PERIOD_NS : POSITIVE RANGE 1 TO 100 := 10; -- clk period in nanoseconds
MIN_KITT_CAR_STEP_MS : POSITIVE RANGE 1 TO 2000 := 1; -- Minimum step period in milliseconds (i.e., value in milliseconds of Delta_t)
NUM_OF_SWS : INTEGER RANGE 1 TO 16 := 16; -- Number of input switches
NUM_OF_LEDS : INTEGER RANGE 1 TO 16 := 16 -- Number of output LEDs
);
PORT (
------- Reset/Clock --------
reset : IN STD_LOGIC;
clk : IN STD_LOGIC;
----------------------------
-------- LEDs/SWs ----------
sw : IN STD_LOGIC_VECTOR(NUM_OF_SWS - 1 DOWNTO 0); -- Switches avaiable on Basys3
led : OUT STD_LOGIC_VECTOR(NUM_OF_LEDS - 1 DOWNTO 0) -- LEDs avaiable on Basys3
----------------------------
);
END KittCar;
ARCHITECTURE Behavioral OF KittCar IS
SIGNAL leds_sr : STD_LOGIC_VECTOR(led'RANGE) := (OTHERS => '0');
SIGNAL counter : UNSIGNED(47 DOWNTO 0) := (OTHERS => '0');
SIGNAL n_period : POSITIVE RANGE 1 TO 2 ** NUM_OF_SWS := 1;
BEGIN
PROCESS (clk, reset)
VARIABLE up : STD_LOGIC := '1';
BEGIN
-- up/down logic
IF leds_sr(NUM_OF_LEDS - 1) = '1' THEN
up := '0';
ELSIF leds_sr(0) = '1' THEN
up := '1';
END IF;
-- Reset the leds
IF unsigned(leds_sr) = 0 THEN
leds_sr <= (0 => '1', OTHERS => '0');
END IF;
IF reset = '1' THEN
leds_sr <= (OTHERS => '0');
up := '1';
counter <= (OTHERS => '0');
ELSIF rising_edge(clk) THEN
-- Calculate the number of periods
IF counter >= ((MIN_KITT_CAR_STEP_MS * 1000000) * n_period) THEN
counter <= (OTHERS => '0');
-- Shift the leds
IF up = '1' THEN
leds_sr <= leds_sr(NUM_OF_LEDS - 2 DOWNTO 0) & '0';
ELSIF up = '0' THEN
leds_sr <= '0' & leds_sr(NUM_OF_LEDS - 1 DOWNTO 1);
END IF;
ELSE
counter <= counter + to_unsigned(CLK_PERIOD_NS, counter'LENGTH);
END IF;
END IF;
END PROCESS;
PROCESS (sw)
BEGIN
n_period <= to_integer(unsigned(sw)) + 1;
END PROCESS;
led <= leds_sr;
END Behavioral;

94
LAB1/lab1_kit_car/lab1_kit_car.srcs/sources_1/new/KittCar_v2.vhd
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@@ -1,94 +0,0 @@
-- File: KittCar_v2.vhd
-- Description: Counter prescaler & unsigned n_period
-- Known problem: Not yet tested
---------- DEFAULT LIBRARY ---------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.NUMERIC_STD.ALL;
------------------------------------
ENTITY KittCar IS
GENERIC (
CLK_PERIOD_NS : POSITIVE RANGE 1 TO 100 := 10; -- clk period in nanoseconds
MIN_KITT_CAR_STEP_MS : POSITIVE RANGE 1 TO 2000 := 1; -- Minimum step period in milliseconds (i.e., value in milliseconds of Delta_t)
NUM_OF_SWS : INTEGER RANGE 1 TO 16 := 16; -- Number of input switches
NUM_OF_LEDS : INTEGER RANGE 1 TO 16 := 16 -- Number of output LEDs
);
PORT (
------- Reset/Clock --------
reset : IN STD_LOGIC;
clk : IN STD_LOGIC;
----------------------------
-------- LEDs/SWs ----------
sw : IN STD_LOGIC_VECTOR(NUM_OF_SWS - 1 DOWNTO 0); -- Switches avaiable on Basys3
led : OUT STD_LOGIC_VECTOR(NUM_OF_LEDS - 1 DOWNTO 0) -- LEDs avaiable on Basys3
----------------------------
);
END KittCar;
ARCHITECTURE Behavioral OF KittCar IS
SIGNAL leds_sr : STD_LOGIC_VECTOR(led'RANGE) := (OTHERS => '0');
SIGNAL n_period : UNSIGNED(sw'RANGE) := to_unsigned(1, sw'LENGTH);
SIGNAL up : STD_LOGIC := '1';
BEGIN
-- Sincronous logic
PROCESS (clk, reset)
VARIABLE counter_ns : UNSIGNED(19 DOWNTO 0) := (OTHERS => '0'); -- 20-bit counter for nanoseconds
VARIABLE counter_ms : UNSIGNED(26 DOWNTO 0) := (OTHERS => '0'); -- 27-bit counter for milliseconds
BEGIN
IF reset = '1' THEN
leds_sr <= (OTHERS => '0');
counter_ns := (OTHERS => '0');
counter_ms := (OTHERS => '0');
ELSIF rising_edge(clk) THEN
-- Kitt logic
IF unsigned(leds_sr) = 0 THEN
leds_sr(0) <= '1';
up <= '1';
ELSIF leds_sr(led'HIGH) = '1' THEN
up <= '0';
ELSIF leds_sr(led'LOW) = '1' THEN
up <= '1';
END IF;
-- Handle counters
counter_ns := counter_ns + to_unsigned(CLK_PERIOD_NS, counter_ns'LENGTH);
IF counter_ns >= to_unsigned(1000000, counter_ns'LENGTH) THEN
counter_ms := counter_ms + 1;
counter_ns := (OTHERS => '0');
END IF;
-- Calculate the number of periods
IF counter_ms >= to_unsigned(MIN_KITT_CAR_STEP_MS, counter_ms'LENGTH) * n_period THEN
-- Shift the leds
IF up = '1' THEN
leds_sr <= leds_sr(NUM_OF_LEDS - 2 DOWNTO 0) & '0';
ELSIF up = '0' THEN
leds_sr <= '0' & leds_sr(NUM_OF_LEDS - 1 DOWNTO 1);
END IF;
-- Reset the counter
counter_ms := (OTHERS => '0');
END IF;
END IF;
END PROCESS;
-- Handle the switch
PROCESS (sw)
BEGIN
n_period <= unsigned(sw) + 1;
END PROCESS;
led <= leds_sr;
END Behavioral;

0
LAB1/lab1_kit_car/lab1_kit_car.srcs/sources_1/new/KittCar_v1.vhd → LAB1/src/KittCar.vhd
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37
LAB1/src/KittCarPWM.vhd Normal file
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@@ -0,0 +1,37 @@
---------- DEFAULT LIBRARY ---------
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.ALL;
------------------------------------
entity KittCarPWM is
Generic (
CLK_PERIOD_NS : POSITIVE RANGE 1 TO 100 := 10; -- clk period in nanoseconds
MIN_KITT_CAR_STEP_MS : POSITIVE RANGE 1 TO 2000 := 1; -- Minimum step period in milliseconds (i.e., value in milliseconds of Delta_t)
NUM_OF_SWS : INTEGER RANGE 1 TO 16 := 16; -- Number of input switches
NUM_OF_LEDS : INTEGER RANGE 1 TO 16 := 16; -- Number of output LEDs
TAIL_LENGTH : INTEGER RANGE 1 TO 16 := 4 -- Tail length
);
Port (
------- Reset/Clock --------
reset : IN STD_LOGIC;
clk : IN STD_LOGIC;
----------------------------
-------- LEDs/SWs ----------
sw : IN STD_LOGIC_VECTOR(NUM_OF_SWS-1 downto 0); -- Switches avaiable on Basys3
leds : OUT STD_LOGIC_VECTOR(NUM_OF_LEDS-1 downto 0) -- LEDs avaiable on Basys3
----------------------------
);
end KittCarPWM;
architecture Behavioral of KittCarPWM is
begin
end Behavioral;

12
LAB1/lab1_kit_car/lab1_kit_car.xpr → LAB1/vivado/lab1_kit_car/lab1_kit_car.xpr
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@@ -3,7 +3,7 @@
<!-- -->
<!-- Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. -->
<Project Version="7" Minor="54" Path="C:/DESD/LAB1/lab1_kit_car/lab1_kit_car.xpr">
<Project Version="7" Minor="54" Path="C:/DESD/LAB1/vivado/lab1_kit_car/lab1_kit_car.xpr">
<DefaultLaunch Dir="$PRUNDIR"/>
<Configuration>
<Option Name="Id" Val="803666bc5e1744d3ae915c39740ba6f4"/>
@@ -33,7 +33,7 @@
<Option Name="SimulatorGccInstallDirActiveHdl" Val=""/>
<Option Name="TargetLanguage" Val="VHDL"/>
<Option Name="BoardPart" Val=""/>
<Option Name="BoardPartRepoPaths" Val="$PPRDIR/../../../Users/david/AppData/Roaming/Xilinx/Vivado/2020.2/xhub/board_store/xilinx_board_store"/>
<Option Name="BoardPartRepoPaths" Val="$PPRDIR/../../../../Users/david/AppData/Roaming/Xilinx/Vivado/2020.2/xhub/board_store/xilinx_board_store"/>
<Option Name="ActiveSimSet" Val="sim_1"/>
<Option Name="DefaultLib" Val="xil_defaultlib"/>
<Option Name="ProjectType" Val="Default"/>
@@ -75,7 +75,7 @@
<FileSets Version="1" Minor="31">
<FileSet Name="sources_1" Type="DesignSrcs" RelSrcDir="$PSRCDIR/sources_1" RelGenDir="$PGENDIR/sources_1">
<Filter Type="Srcs"/>
<File Path="$PSRCDIR/sources_1/new/KittCar_v2.vhd">
<File Path="$PPRDIR/../../src/KittCar.vhd">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="simulation"/>
@@ -89,7 +89,7 @@
</FileSet>
<FileSet Name="constrs_1" Type="Constrs" RelSrcDir="$PSRCDIR/constrs_1" RelGenDir="$PGENDIR/constrs_1">
<Filter Type="Constrs"/>
<File Path="$PPRDIR/../basys3_master.xdc">
<File Path="$PPRDIR/../../cons/basys3_master.xdc">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="implementation"/>
@@ -142,7 +142,7 @@
</Simulator>
</Simulators>
<Runs Version="1" Minor="15">
<Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7a35tcpg236-1" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" Dir="$PRUNDIR/synth_1" IncludeInArchive="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/synth_1">
<Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7a35tcpg236-1" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" Dir="$PRUNDIR/synth_1" IncludeInArchive="true" AutoIncrementalDir="$PPRDIR/../../lab1_kit_car/lab1_kit_car.srcs/utils_1/imports/synth_1">
<Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2020"/>
<Step Id="synth_design"/>
@@ -152,7 +152,7 @@
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
<RQSFiles/>
</Run>
<Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7a35tcpg236-1" ConstrsSet="constrs_1" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" Dir="$PRUNDIR/impl_1" SynthRun="synth_1" IncludeInArchive="true" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/impl_1">
<Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7a35tcpg236-1" ConstrsSet="constrs_1" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" Dir="$PRUNDIR/impl_1" SynthRun="synth_1" IncludeInArchive="true" GenFullBitstream="true" AutoIncrementalDir="$PPRDIR/../../lab1_kit_car/lab1_kit_car.srcs/utils_1/imports/impl_1">
<Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2020"/>
<Step Id="init_design"/>