Reorder reset, sys_clock and USB UART ports in lab_2_wrapper and update synthesis flow mode in lab_2.bd
This commit is contained in:
@@ -1,294 +0,0 @@
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## This file is a general .xdc for the Basys3 rev B board
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## To use it in a project:
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## - uncomment the lines corresponding to used pins
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## - rename the used ports (in each line, after get_ports) according to the top level signal names in the project
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## Clock signal
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#set_property PACKAGE_PIN W5 [get_ports clk]
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#set_property IOSTANDARD LVCMOS33 [get_ports clk]
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#create_clock -add -name sys_clk_pin -period 10.00 -waveform {0 5} [get_ports clk]
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## Switches
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#set_property PACKAGE_PIN V17 [get_ports {sw[0]}]
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#set_property IOSTANDARD LVCMOS33 [get_ports {sw[0]}]
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#set_property PACKAGE_PIN V16 [get_ports {sw[1]}]
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#set_property IOSTANDARD LVCMOS33 [get_ports {sw[1]}]
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#set_property PACKAGE_PIN W16 [get_ports {sw[2]}]
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#set_property IOSTANDARD LVCMOS33 [get_ports {sw[2]}]
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#set_property PACKAGE_PIN W17 [get_ports {sw[3]}]
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#set_property IOSTANDARD LVCMOS33 [get_ports {sw[3]}]
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#set_property PACKAGE_PIN W15 [get_ports {sw[4]}]
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#set_property IOSTANDARD LVCMOS33 [get_ports {sw[4]}]
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#set_property PACKAGE_PIN V15 [get_ports {sw[5]}]
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#set_property IOSTANDARD LVCMOS33 [get_ports {sw[5]}]
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#set_property PACKAGE_PIN W14 [get_ports {sw[6]}]
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#set_property IOSTANDARD LVCMOS33 [get_ports {sw[6]}]
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#set_property PACKAGE_PIN W13 [get_ports {sw[7]}]
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#set_property IOSTANDARD LVCMOS33 [get_ports {sw[7]}]
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#set_property PACKAGE_PIN V2 [get_ports {sw[8]}]
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#set_property IOSTANDARD LVCMOS33 [get_ports {sw[8]}]
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#set_property PACKAGE_PIN T3 [get_ports {sw[9]}]
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#set_property IOSTANDARD LVCMOS33 [get_ports {sw[9]}]
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#set_property PACKAGE_PIN T2 [get_ports {sw[10]}]
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#set_property IOSTANDARD LVCMOS33 [get_ports {sw[10]}]
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#set_property PACKAGE_PIN R3 [get_ports {sw[11]}]
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#set_property IOSTANDARD LVCMOS33 [get_ports {sw[11]}]
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#set_property PACKAGE_PIN W2 [get_ports {sw[12]}]
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#set_property IOSTANDARD LVCMOS33 [get_ports {sw[12]}]
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#set_property PACKAGE_PIN U1 [get_ports {sw[13]}]
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#set_property IOSTANDARD LVCMOS33 [get_ports {sw[13]}]
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#set_property PACKAGE_PIN T1 [get_ports {sw[14]}]
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#set_property IOSTANDARD LVCMOS33 [get_ports {sw[14]}]
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#set_property PACKAGE_PIN R2 [get_ports {sw[15]}]
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#set_property IOSTANDARD LVCMOS33 [get_ports {sw[15]}]
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## LEDs
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#set_property PACKAGE_PIN U16 [get_ports {led[0]}]
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#set_property IOSTANDARD LVCMOS33 [get_ports {led[0]}]
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#set_property PACKAGE_PIN E19 [get_ports {led[1]}]
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#set_property IOSTANDARD LVCMOS33 [get_ports {led[1]}]
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#set_property PACKAGE_PIN U19 [get_ports {led[2]}]
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#set_property IOSTANDARD LVCMOS33 [get_ports {led[2]}]
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#set_property PACKAGE_PIN V19 [get_ports {led[3]}]
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#set_property IOSTANDARD LVCMOS33 [get_ports {led[3]}]
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#set_property PACKAGE_PIN W18 [get_ports {led[4]}]
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#set_property IOSTANDARD LVCMOS33 [get_ports {led[4]}]
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#set_property PACKAGE_PIN U15 [get_ports {led[5]}]
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#set_property IOSTANDARD LVCMOS33 [get_ports {led[5]}]
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#set_property PACKAGE_PIN U14 [get_ports {led[6]}]
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#set_property IOSTANDARD LVCMOS33 [get_ports {led[6]}]
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#set_property PACKAGE_PIN V14 [get_ports {led[7]}]
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#set_property IOSTANDARD LVCMOS33 [get_ports {led[7]}]
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#set_property PACKAGE_PIN V13 [get_ports {led[8]}]
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#set_property IOSTANDARD LVCMOS33 [get_ports {led[8]}]
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#set_property PACKAGE_PIN V3 [get_ports {led[9]}]
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#set_property IOSTANDARD LVCMOS33 [get_ports {led[9]}]
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#set_property PACKAGE_PIN W3 [get_ports {led[10]}]
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#set_property IOSTANDARD LVCMOS33 [get_ports {led[10]}]
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#set_property PACKAGE_PIN U3 [get_ports {led[11]}]
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#set_property IOSTANDARD LVCMOS33 [get_ports {led[11]}]
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#set_property PACKAGE_PIN P3 [get_ports {led[12]}]
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#set_property IOSTANDARD LVCMOS33 [get_ports {led[12]}]
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#set_property PACKAGE_PIN N3 [get_ports {led[13]}]
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#set_property IOSTANDARD LVCMOS33 [get_ports {led[13]}]
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#set_property PACKAGE_PIN P1 [get_ports {led[14]}]
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#set_property IOSTANDARD LVCMOS33 [get_ports {led[14]}]
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#set_property PACKAGE_PIN L1 [get_ports {led[15]}]
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#set_property IOSTANDARD LVCMOS33 [get_ports {led[15]}]
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##7 segment display
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#set_property PACKAGE_PIN W7 [get_ports {seg[0]}]
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#set_property IOSTANDARD LVCMOS33 [get_ports {seg[0]}]
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#set_property PACKAGE_PIN W6 [get_ports {seg[1]}]
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#set_property IOSTANDARD LVCMOS33 [get_ports {seg[1]}]
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#set_property PACKAGE_PIN U8 [get_ports {seg[2]}]
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#set_property IOSTANDARD LVCMOS33 [get_ports {seg[2]}]
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#set_property PACKAGE_PIN V8 [get_ports {seg[3]}]
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#set_property IOSTANDARD LVCMOS33 [get_ports {seg[3]}]
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#set_property PACKAGE_PIN U5 [get_ports {seg[4]}]
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#set_property IOSTANDARD LVCMOS33 [get_ports {seg[4]}]
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#set_property PACKAGE_PIN V5 [get_ports {seg[5]}]
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#set_property IOSTANDARD LVCMOS33 [get_ports {seg[5]}]
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#set_property PACKAGE_PIN U7 [get_ports {seg[6]}]
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#set_property IOSTANDARD LVCMOS33 [get_ports {seg[6]}]
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#set_property PACKAGE_PIN V7 [get_ports dp]
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#set_property IOSTANDARD LVCMOS33 [get_ports dp]
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#set_property PACKAGE_PIN U2 [get_ports {an[0]}]
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#set_property IOSTANDARD LVCMOS33 [get_ports {an[0]}]
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#set_property PACKAGE_PIN U4 [get_ports {an[1]}]
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#set_property IOSTANDARD LVCMOS33 [get_ports {an[1]}]
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#set_property PACKAGE_PIN V4 [get_ports {an[2]}]
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#set_property IOSTANDARD LVCMOS33 [get_ports {an[2]}]
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#set_property PACKAGE_PIN W4 [get_ports {an[3]}]
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#set_property IOSTANDARD LVCMOS33 [get_ports {an[3]}]
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##Buttons
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#set_property PACKAGE_PIN U18 [get_ports btnC]
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#set_property IOSTANDARD LVCMOS33 [get_ports btnC]
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#set_property PACKAGE_PIN T18 [get_ports btnU]
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#set_property IOSTANDARD LVCMOS33 [get_ports btnU]
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#set_property PACKAGE_PIN W19 [get_ports btnL]
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#set_property IOSTANDARD LVCMOS33 [get_ports btnL]
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#set_property PACKAGE_PIN T17 [get_ports btnR]
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#set_property IOSTANDARD LVCMOS33 [get_ports btnR]
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#set_property PACKAGE_PIN U17 [get_ports btnD]
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#set_property IOSTANDARD LVCMOS33 [get_ports btnD]
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##Pmod Header JA
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##Sch name = JA1
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#set_property PACKAGE_PIN J1 [get_ports {JA[0]}]
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#set_property IOSTANDARD LVCMOS33 [get_ports {JA[0]}]
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##Sch name = JA2
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#set_property PACKAGE_PIN L2 [get_ports {JA[1]}]
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#set_property IOSTANDARD LVCMOS33 [get_ports {JA[1]}]
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##Sch name = JA3
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#set_property PACKAGE_PIN J2 [get_ports {JA[2]}]
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#set_property IOSTANDARD LVCMOS33 [get_ports {JA[2]}]
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##Sch name = JA4
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#set_property PACKAGE_PIN G2 [get_ports {JA[3]}]
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#set_property IOSTANDARD LVCMOS33 [get_ports {JA[3]}]
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##Sch name = JA7
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#set_property PACKAGE_PIN H1 [get_ports {JA[4]}]
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#set_property IOSTANDARD LVCMOS33 [get_ports {JA[4]}]
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##Sch name = JA8
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#set_property PACKAGE_PIN K2 [get_ports {JA[5]}]
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#set_property IOSTANDARD LVCMOS33 [get_ports {JA[5]}]
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##Sch name = JA9
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#set_property PACKAGE_PIN H2 [get_ports {JA[6]}]
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#set_property IOSTANDARD LVCMOS33 [get_ports {JA[6]}]
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##Sch name = JA10
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#set_property PACKAGE_PIN G3 [get_ports {JA[7]}]
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#set_property IOSTANDARD LVCMOS33 [get_ports {JA[7]}]
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##Pmod Header JB
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##Sch name = JB1
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#set_property PACKAGE_PIN A14 [get_ports {JB[0]}]
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#set_property IOSTANDARD LVCMOS33 [get_ports {JB[0]}]
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##Sch name = JB2
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#set_property PACKAGE_PIN A16 [get_ports {JB[1]}]
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#set_property IOSTANDARD LVCMOS33 [get_ports {JB[1]}]
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##Sch name = JB3
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#set_property PACKAGE_PIN B15 [get_ports {JB[2]}]
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#set_property IOSTANDARD LVCMOS33 [get_ports {JB[2]}]
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##Sch name = JB4
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#set_property PACKAGE_PIN B16 [get_ports {JB[3]}]
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#set_property IOSTANDARD LVCMOS33 [get_ports {JB[3]}]
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##Sch name = JB7
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#set_property PACKAGE_PIN A15 [get_ports {JB[4]}]
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#set_property IOSTANDARD LVCMOS33 [get_ports {JB[4]}]
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##Sch name = JB8
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#set_property PACKAGE_PIN A17 [get_ports {JB[5]}]
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#set_property IOSTANDARD LVCMOS33 [get_ports {JB[5]}]
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##Sch name = JB9
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#set_property PACKAGE_PIN C15 [get_ports {JB[6]}]
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#set_property IOSTANDARD LVCMOS33 [get_ports {JB[6]}]
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##Sch name = JB10
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#set_property PACKAGE_PIN C16 [get_ports {JB[7]}]
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#set_property IOSTANDARD LVCMOS33 [get_ports {JB[7]}]
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##Pmod Header JC
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##Sch name = JC1
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#set_property PACKAGE_PIN K17 [get_ports {JC[0]}]
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#set_property IOSTANDARD LVCMOS33 [get_ports {JC[0]}]
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##Sch name = JC2
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#set_property PACKAGE_PIN M18 [get_ports {JC[1]}]
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#set_property IOSTANDARD LVCMOS33 [get_ports {JC[1]}]
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##Sch name = JC3
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#set_property PACKAGE_PIN N17 [get_ports {JC[2]}]
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#set_property IOSTANDARD LVCMOS33 [get_ports {JC[2]}]
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##Sch name = JC4
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#set_property PACKAGE_PIN P18 [get_ports {JC[3]}]
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#set_property IOSTANDARD LVCMOS33 [get_ports {JC[3]}]
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##Sch name = JC7
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#set_property PACKAGE_PIN L17 [get_ports {JC[4]}]
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#set_property IOSTANDARD LVCMOS33 [get_ports {JC[4]}]
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##Sch name = JC8
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#set_property PACKAGE_PIN M19 [get_ports {JC[5]}]
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#set_property IOSTANDARD LVCMOS33 [get_ports {JC[5]}]
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##Sch name = JC9
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#set_property PACKAGE_PIN P17 [get_ports {JC[6]}]
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#set_property IOSTANDARD LVCMOS33 [get_ports {JC[6]}]
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##Sch name = JC10
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#set_property PACKAGE_PIN R18 [get_ports {JC[7]}]
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#set_property IOSTANDARD LVCMOS33 [get_ports {JC[7]}]
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##Pmod Header JXADC
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##Sch name = XA1_P
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#set_property PACKAGE_PIN J3 [get_ports {JXADC[0]}]
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#set_property IOSTANDARD LVCMOS33 [get_ports {JXADC[0]}]
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##Sch name = XA2_P
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#set_property PACKAGE_PIN L3 [get_ports {JXADC[1]}]
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#set_property IOSTANDARD LVCMOS33 [get_ports {JXADC[1]}]
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##Sch name = XA3_P
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#set_property PACKAGE_PIN M2 [get_ports {JXADC[2]}]
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#set_property IOSTANDARD LVCMOS33 [get_ports {JXADC[2]}]
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##Sch name = XA4_P
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#set_property PACKAGE_PIN N2 [get_ports {JXADC[3]}]
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#set_property IOSTANDARD LVCMOS33 [get_ports {JXADC[3]}]
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##Sch name = XA1_N
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#set_property PACKAGE_PIN K3 [get_ports {JXADC[4]}]
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#set_property IOSTANDARD LVCMOS33 [get_ports {JXADC[4]}]
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##Sch name = XA2_N
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#set_property PACKAGE_PIN M3 [get_ports {JXADC[5]}]
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#set_property IOSTANDARD LVCMOS33 [get_ports {JXADC[5]}]
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##Sch name = XA3_N
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#set_property PACKAGE_PIN M1 [get_ports {JXADC[6]}]
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#set_property IOSTANDARD LVCMOS33 [get_ports {JXADC[6]}]
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##Sch name = XA4_N
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#set_property PACKAGE_PIN N1 [get_ports {JXADC[7]}]
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#set_property IOSTANDARD LVCMOS33 [get_ports {JXADC[7]}]
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##VGA Connector
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#set_property PACKAGE_PIN G19 [get_ports {vgaRed[0]}]
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#set_property IOSTANDARD LVCMOS33 [get_ports {vgaRed[0]}]
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#set_property PACKAGE_PIN H19 [get_ports {vgaRed[1]}]
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#set_property IOSTANDARD LVCMOS33 [get_ports {vgaRed[1]}]
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#set_property PACKAGE_PIN J19 [get_ports {vgaRed[2]}]
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#set_property IOSTANDARD LVCMOS33 [get_ports {vgaRed[2]}]
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#set_property PACKAGE_PIN N19 [get_ports {vgaRed[3]}]
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#set_property IOSTANDARD LVCMOS33 [get_ports {vgaRed[3]}]
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#set_property PACKAGE_PIN N18 [get_ports {vgaBlue[0]}]
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#set_property IOSTANDARD LVCMOS33 [get_ports {vgaBlue[0]}]
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#set_property PACKAGE_PIN L18 [get_ports {vgaBlue[1]}]
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#set_property IOSTANDARD LVCMOS33 [get_ports {vgaBlue[1]}]
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#set_property PACKAGE_PIN K18 [get_ports {vgaBlue[2]}]
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#set_property IOSTANDARD LVCMOS33 [get_ports {vgaBlue[2]}]
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#set_property PACKAGE_PIN J18 [get_ports {vgaBlue[3]}]
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#set_property IOSTANDARD LVCMOS33 [get_ports {vgaBlue[3]}]
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#set_property PACKAGE_PIN J17 [get_ports {vgaGreen[0]}]
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#set_property IOSTANDARD LVCMOS33 [get_ports {vgaGreen[0]}]
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#set_property PACKAGE_PIN H17 [get_ports {vgaGreen[1]}]
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#set_property IOSTANDARD LVCMOS33 [get_ports {vgaGreen[1]}]
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#set_property PACKAGE_PIN G17 [get_ports {vgaGreen[2]}]
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#set_property IOSTANDARD LVCMOS33 [get_ports {vgaGreen[2]}]
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#set_property PACKAGE_PIN D17 [get_ports {vgaGreen[3]}]
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#set_property IOSTANDARD LVCMOS33 [get_ports {vgaGreen[3]}]
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#set_property PACKAGE_PIN P19 [get_ports Hsync]
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#set_property IOSTANDARD LVCMOS33 [get_ports Hsync]
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#set_property PACKAGE_PIN R19 [get_ports Vsync]
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#set_property IOSTANDARD LVCMOS33 [get_ports Vsync]
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##USB-RS232 Interface
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#set_property PACKAGE_PIN B18 [get_ports RsRx]
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#set_property IOSTANDARD LVCMOS33 [get_ports RsRx]
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#set_property PACKAGE_PIN A18 [get_ports RsTx]
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#set_property IOSTANDARD LVCMOS33 [get_ports RsTx]
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##USB HID (PS/2)
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#set_property PACKAGE_PIN C17 [get_ports PS2Clk]
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#set_property IOSTANDARD LVCMOS33 [get_ports PS2Clk]
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#set_property PULLUP true [get_ports PS2Clk]
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#set_property PACKAGE_PIN B17 [get_ports PS2Data]
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#set_property IOSTANDARD LVCMOS33 [get_ports PS2Data]
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#set_property PULLUP true [get_ports PS2Data]
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##Quad SPI Flash
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##Note that CCLK_0 cannot be placed in 7 series devices. You can access it using the
|
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##STARTUPE2 primitive.
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#set_property PACKAGE_PIN D18 [get_ports {QspiDB[0]}]
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#set_property IOSTANDARD LVCMOS33 [get_ports {QspiDB[0]}]
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#set_property PACKAGE_PIN D19 [get_ports {QspiDB[1]}]
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#set_property IOSTANDARD LVCMOS33 [get_ports {QspiDB[1]}]
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#set_property PACKAGE_PIN G18 [get_ports {QspiDB[2]}]
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#set_property IOSTANDARD LVCMOS33 [get_ports {QspiDB[2]}]
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#set_property PACKAGE_PIN F18 [get_ports {QspiDB[3]}]
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#set_property IOSTANDARD LVCMOS33 [get_ports {QspiDB[3]}]
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#set_property PACKAGE_PIN K19 [get_ports QspiCSn]
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#set_property IOSTANDARD LVCMOS33 [get_ports QspiCSn]
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@@ -1,7 +1,7 @@
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--Copyright 1986-2020 Xilinx, Inc. All Rights Reserved.
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----------------------------------------------------------------------------------
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--Tool Version: Vivado v.2020.2 (win64) Build 3064766 Wed Nov 18 09:12:45 MST 2020
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--Date : Mon Mar 31 15:19:19 2025
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--Date : Wed Apr 9 11:36:10 2025
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--Host : Davide-Samsung running 64-bit major release (build 9200)
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--Command : generate_target lab_2_wrapper.bd
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--Design : lab_2_wrapper
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@@ -26,11 +26,11 @@ end lab_2_wrapper;
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architecture STRUCTURE of lab_2_wrapper is
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component lab_2 is
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port (
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reset : in STD_LOGIC;
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||||
sys_clock : in STD_LOGIC;
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||||
led_of : out STD_LOGIC;
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led_ok : out STD_LOGIC;
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led_uf : out STD_LOGIC;
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sys_clock : in STD_LOGIC;
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reset : in STD_LOGIC;
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usb_uart_txd : out STD_LOGIC;
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usb_uart_rxd : in STD_LOGIC
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);
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||||
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@@ -5,7 +5,7 @@
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"device": "xc7a35tcpg236-1",
|
||||
"name": "lab_2",
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||||
"rev_ctrl_bd_flag": "RevCtrlBdOff",
|
||||
"synth_flow_mode": "Hierarchical",
|
||||
"synth_flow_mode": "None",
|
||||
"tool_version": "2020.2",
|
||||
"validated": "true"
|
||||
},
|
||||
@@ -18,10 +18,10 @@
|
||||
"img_conv_0": "",
|
||||
"led_blinker_1": "",
|
||||
"led_blinker_2": "",
|
||||
"system_ila_0": "",
|
||||
"clk_wiz_0": "",
|
||||
"proc_sys_reset_0": "",
|
||||
"AXI4Stream_UART_0": "",
|
||||
"system_ila_0": ""
|
||||
"proc_sys_reset_1": "",
|
||||
"AXI4Stream_UART_0": ""
|
||||
},
|
||||
"interface_ports": {
|
||||
"usb_uart": {
|
||||
@@ -30,18 +30,14 @@
|
||||
}
|
||||
},
|
||||
"ports": {
|
||||
"reset": {
|
||||
"type": "rst",
|
||||
"direction": "I",
|
||||
"parameters": {
|
||||
"INSERT_VIP": {
|
||||
"value": "0",
|
||||
"value_src": "default"
|
||||
},
|
||||
"POLARITY": {
|
||||
"value": "ACTIVE_HIGH"
|
||||
}
|
||||
}
|
||||
"led_of": {
|
||||
"direction": "O"
|
||||
},
|
||||
"led_ok": {
|
||||
"direction": "O"
|
||||
},
|
||||
"led_uf": {
|
||||
"direction": "O"
|
||||
},
|
||||
"sys_clock": {
|
||||
"type": "clk",
|
||||
@@ -63,19 +59,22 @@
|
||||
"value_src": "default"
|
||||
},
|
||||
"PHASE": {
|
||||
"value": "0.000",
|
||||
"value_src": "default"
|
||||
"value": "0.000"
|
||||
}
|
||||
}
|
||||
},
|
||||
"led_of": {
|
||||
"direction": "O"
|
||||
},
|
||||
"led_ok": {
|
||||
"direction": "O"
|
||||
},
|
||||
"led_uf": {
|
||||
"direction": "O"
|
||||
"reset": {
|
||||
"type": "rst",
|
||||
"direction": "I",
|
||||
"parameters": {
|
||||
"INSERT_VIP": {
|
||||
"value": "0",
|
||||
"value_src": "default"
|
||||
},
|
||||
"POLARITY": {
|
||||
"value": "ACTIVE_HIGH"
|
||||
}
|
||||
}
|
||||
}
|
||||
},
|
||||
"components": {
|
||||
@@ -1080,29 +1079,6 @@
|
||||
}
|
||||
}
|
||||
},
|
||||
"clk_wiz_0": {
|
||||
"vlnv": "xilinx.com:ip:clk_wiz:6.0",
|
||||
"xci_name": "lab_2_clk_wiz_0_0",
|
||||
"xci_path": "ip\\lab_2_clk_wiz_0_0\\lab_2_clk_wiz_0_0.xci",
|
||||
"inst_hier_path": "clk_wiz_0"
|
||||
},
|
||||
"proc_sys_reset_0": {
|
||||
"vlnv": "xilinx.com:ip:proc_sys_reset:5.0",
|
||||
"xci_name": "lab_2_proc_sys_reset_0_0",
|
||||
"xci_path": "ip\\lab_2_proc_sys_reset_0_0\\lab_2_proc_sys_reset_0_0.xci",
|
||||
"inst_hier_path": "proc_sys_reset_0",
|
||||
"parameters": {
|
||||
"C_AUX_RESET_HIGH": {
|
||||
"value": "0"
|
||||
}
|
||||
}
|
||||
},
|
||||
"AXI4Stream_UART_0": {
|
||||
"vlnv": "DigiLAB:ip:AXI4Stream_UART:1.1",
|
||||
"xci_name": "lab_2_AXI4Stream_UART_0_0",
|
||||
"xci_path": "ip\\lab_2_AXI4Stream_UART_0_0\\lab_2_AXI4Stream_UART_0_0.xci",
|
||||
"inst_hier_path": "AXI4Stream_UART_0"
|
||||
},
|
||||
"system_ila_0": {
|
||||
"vlnv": "xilinx.com:ip:system_ila:1.1",
|
||||
"xci_name": "lab_2_system_ila_0_1",
|
||||
@@ -1145,6 +1121,51 @@
|
||||
"vlnv": "xilinx.com:interface:axis_rtl:1.0"
|
||||
}
|
||||
}
|
||||
},
|
||||
"clk_wiz_0": {
|
||||
"vlnv": "xilinx.com:ip:clk_wiz:6.0",
|
||||
"xci_name": "lab_2_clk_wiz_0_1",
|
||||
"xci_path": "ip\\lab_2_clk_wiz_0_1\\lab_2_clk_wiz_0_1.xci",
|
||||
"inst_hier_path": "clk_wiz_0",
|
||||
"parameters": {
|
||||
"CLK_IN1_BOARD_INTERFACE": {
|
||||
"value": "sys_clock"
|
||||
},
|
||||
"RESET_BOARD_INTERFACE": {
|
||||
"value": "reset"
|
||||
},
|
||||
"USE_BOARD_FLOW": {
|
||||
"value": "true"
|
||||
}
|
||||
}
|
||||
},
|
||||
"proc_sys_reset_1": {
|
||||
"vlnv": "xilinx.com:ip:proc_sys_reset:5.0",
|
||||
"xci_name": "lab_2_proc_sys_reset_1_1",
|
||||
"xci_path": "ip\\lab_2_proc_sys_reset_1_1\\lab_2_proc_sys_reset_1_1.xci",
|
||||
"inst_hier_path": "proc_sys_reset_1",
|
||||
"parameters": {
|
||||
"RESET_BOARD_INTERFACE": {
|
||||
"value": "reset"
|
||||
},
|
||||
"USE_BOARD_FLOW": {
|
||||
"value": "true"
|
||||
}
|
||||
}
|
||||
},
|
||||
"AXI4Stream_UART_0": {
|
||||
"vlnv": "DigiLAB:ip:AXI4Stream_UART:1.1",
|
||||
"xci_name": "lab_2_AXI4Stream_UART_0_2",
|
||||
"xci_path": "ip\\lab_2_AXI4Stream_UART_0_2\\lab_2_AXI4Stream_UART_0_2.xci",
|
||||
"inst_hier_path": "AXI4Stream_UART_0",
|
||||
"parameters": {
|
||||
"UART_BOARD_INTERFACE": {
|
||||
"value": "usb_uart"
|
||||
},
|
||||
"USE_BOARD_FLOW": {
|
||||
"value": "true"
|
||||
}
|
||||
}
|
||||
}
|
||||
},
|
||||
"interface_nets": {
|
||||
@@ -1167,10 +1188,11 @@
|
||||
"system_ila_0/SLOT_0_AXIS"
|
||||
]
|
||||
},
|
||||
"AXI4Stream_UART_0_UART": {
|
||||
"rgb2gray_0_m_axis": {
|
||||
"interface_ports": [
|
||||
"usb_uart",
|
||||
"AXI4Stream_UART_0/UART"
|
||||
"rgb2gray_0/m_axis",
|
||||
"bram_writer_0/s_axis",
|
||||
"system_ila_0/SLOT_2_AXIS"
|
||||
]
|
||||
},
|
||||
"img_conv_0_m_axis": {
|
||||
@@ -1180,61 +1202,35 @@
|
||||
"system_ila_0/SLOT_1_AXIS"
|
||||
]
|
||||
},
|
||||
"rgb2gray_0_m_axis": {
|
||||
"AXI4Stream_UART_0_UART": {
|
||||
"interface_ports": [
|
||||
"rgb2gray_0/m_axis",
|
||||
"bram_writer_0/s_axis",
|
||||
"system_ila_0/SLOT_2_AXIS"
|
||||
"usb_uart",
|
||||
"AXI4Stream_UART_0/UART"
|
||||
]
|
||||
}
|
||||
},
|
||||
"nets": {
|
||||
"reset_1": {
|
||||
"ports": [
|
||||
"reset",
|
||||
"proc_sys_reset_0/ext_reset_in",
|
||||
"clk_wiz_0/reset"
|
||||
]
|
||||
},
|
||||
"sys_clock_1": {
|
||||
"ports": [
|
||||
"sys_clock",
|
||||
"clk_wiz_0/clk_in1"
|
||||
]
|
||||
},
|
||||
"clk_wiz_0_clk_out1": {
|
||||
"ports": [
|
||||
"clk_wiz_0/clk_out1",
|
||||
"proc_sys_reset_0/slowest_sync_clk",
|
||||
"img_conv_0/clk",
|
||||
"packetizer_0/clk",
|
||||
"AXI4Stream_UART_0/clk_uart",
|
||||
"AXI4Stream_UART_0/m00_axis_rx_aclk",
|
||||
"AXI4Stream_UART_0/s00_axis_tx_aclk",
|
||||
"depacketizer_0/clk",
|
||||
"rgb2gray_0/clk",
|
||||
"led_blinker_0/clk",
|
||||
"led_blinker_1/clk",
|
||||
"led_blinker_2/clk",
|
||||
"bram_writer_0/clk",
|
||||
"system_ila_0/clk"
|
||||
]
|
||||
},
|
||||
"clk_wiz_0_locked": {
|
||||
"ports": [
|
||||
"clk_wiz_0/locked",
|
||||
"proc_sys_reset_0/dcm_locked"
|
||||
]
|
||||
},
|
||||
"proc_sys_reset_0_peripheral_reset": {
|
||||
"ports": [
|
||||
"proc_sys_reset_0/peripheral_reset",
|
||||
"AXI4Stream_UART_0/rst"
|
||||
"system_ila_0/clk",
|
||||
"proc_sys_reset_1/slowest_sync_clk",
|
||||
"AXI4Stream_UART_0/clk_uart",
|
||||
"AXI4Stream_UART_0/m00_axis_rx_aclk",
|
||||
"AXI4Stream_UART_0/s00_axis_tx_aclk"
|
||||
]
|
||||
},
|
||||
"proc_sys_reset_0_peripheral_aresetn": {
|
||||
"ports": [
|
||||
"proc_sys_reset_0/peripheral_aresetn",
|
||||
"proc_sys_reset_1/peripheral_aresetn",
|
||||
"img_conv_0/aresetn",
|
||||
"packetizer_0/aresetn",
|
||||
"depacketizer_0/aresetn",
|
||||
@@ -1243,9 +1239,9 @@
|
||||
"led_blinker_1/aresetn",
|
||||
"led_blinker_2/aresetn",
|
||||
"bram_writer_0/aresetn",
|
||||
"system_ila_0/resetn",
|
||||
"AXI4Stream_UART_0/m00_axis_rx_aresetn",
|
||||
"AXI4Stream_UART_0/s00_axis_tx_aresetn",
|
||||
"system_ila_0/resetn"
|
||||
"AXI4Stream_UART_0/s00_axis_tx_aresetn"
|
||||
]
|
||||
},
|
||||
"bram_writer_0_conv_data": {
|
||||
@@ -1311,6 +1307,31 @@
|
||||
"led_blinker_2/led",
|
||||
"led_of"
|
||||
]
|
||||
},
|
||||
"sys_clock_1": {
|
||||
"ports": [
|
||||
"sys_clock",
|
||||
"clk_wiz_0/clk_in1"
|
||||
]
|
||||
},
|
||||
"clk_wiz_0_locked": {
|
||||
"ports": [
|
||||
"clk_wiz_0/locked",
|
||||
"proc_sys_reset_1/dcm_locked"
|
||||
]
|
||||
},
|
||||
"reset_1": {
|
||||
"ports": [
|
||||
"reset",
|
||||
"proc_sys_reset_1/ext_reset_in",
|
||||
"clk_wiz_0/reset"
|
||||
]
|
||||
},
|
||||
"proc_sys_reset_1_peripheral_reset": {
|
||||
"ports": [
|
||||
"proc_sys_reset_1/peripheral_reset",
|
||||
"AXI4Stream_UART_0/rst"
|
||||
]
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
@@ -32,7 +32,7 @@
|
||||
<Option Name="SimulatorGccInstallDirRiviera" Val=""/>
|
||||
<Option Name="SimulatorGccInstallDirActiveHdl" Val=""/>
|
||||
<Option Name="TargetLanguage" Val="VHDL"/>
|
||||
<Option Name="BoardPart" Val=""/>
|
||||
<Option Name="BoardPart" Val="digilentinc.com:basys3:part0:1.1"/>
|
||||
<Option Name="BoardPartRepoPaths" Val="$PPRDIR/../../../../Users/david/AppData/Roaming/Xilinx/Vivado/2020.2/xhub/board_store/xilinx_board_store"/>
|
||||
<Option Name="ActiveSimSet" Val="sim_1"/>
|
||||
<Option Name="DefaultLib" Val="xil_defaultlib"/>
|
||||
@@ -47,6 +47,7 @@
|
||||
<Option Name="IPUserFilesDir" Val="$PIPUSERFILESDIR"/>
|
||||
<Option Name="IPStaticSourceDir" Val="$PIPUSERFILESDIR/ipstatic"/>
|
||||
<Option Name="EnableBDX" Val="FALSE"/>
|
||||
<Option Name="DSABoardId" Val="basys3"/>
|
||||
<Option Name="WTXSimLaunchSim" Val="0"/>
|
||||
<Option Name="WTModelSimLaunchSim" Val="0"/>
|
||||
<Option Name="WTQuestaLaunchSim" Val="0"/>
|
||||
@@ -54,13 +55,13 @@
|
||||
<Option Name="WTVcsLaunchSim" Val="0"/>
|
||||
<Option Name="WTRivieraLaunchSim" Val="0"/>
|
||||
<Option Name="WTActivehdlLaunchSim" Val="0"/>
|
||||
<Option Name="WTXSimExportSim" Val="4"/>
|
||||
<Option Name="WTModelSimExportSim" Val="4"/>
|
||||
<Option Name="WTQuestaExportSim" Val="4"/>
|
||||
<Option Name="WTIesExportSim" Val="4"/>
|
||||
<Option Name="WTVcsExportSim" Val="4"/>
|
||||
<Option Name="WTRivieraExportSim" Val="4"/>
|
||||
<Option Name="WTActivehdlExportSim" Val="4"/>
|
||||
<Option Name="WTXSimExportSim" Val="5"/>
|
||||
<Option Name="WTModelSimExportSim" Val="5"/>
|
||||
<Option Name="WTQuestaExportSim" Val="5"/>
|
||||
<Option Name="WTIesExportSim" Val="5"/>
|
||||
<Option Name="WTVcsExportSim" Val="5"/>
|
||||
<Option Name="WTRivieraExportSim" Val="5"/>
|
||||
<Option Name="WTActivehdlExportSim" Val="5"/>
|
||||
<Option Name="GenerateIPUpgradeLog" Val="TRUE"/>
|
||||
<Option Name="XSimRadix" Val="hex"/>
|
||||
<Option Name="XSimTimeUnit" Val="ns"/>
|
||||
@@ -172,78 +173,6 @@
|
||||
<Option Name="TopAutoSet" Val="TRUE"/>
|
||||
</Config>
|
||||
</FileSet>
|
||||
<FileSet Name="lab_2_bram_writer_0_0" Type="BlockSrcs" RelSrcDir="$PSRCDIR/lab_2_bram_writer_0_0" RelGenDir="$PGENDIR/lab_2_bram_writer_0_0">
|
||||
<Config>
|
||||
<Option Name="TopModule" Val="lab_2_bram_writer_0_0"/>
|
||||
<Option Name="UseBlackboxStub" Val="1"/>
|
||||
</Config>
|
||||
</FileSet>
|
||||
<FileSet Name="lab_2_depacketizer_0_0" Type="BlockSrcs" RelSrcDir="$PSRCDIR/lab_2_depacketizer_0_0" RelGenDir="$PGENDIR/lab_2_depacketizer_0_0">
|
||||
<Config>
|
||||
<Option Name="TopModule" Val="lab_2_depacketizer_0_0"/>
|
||||
<Option Name="UseBlackboxStub" Val="1"/>
|
||||
</Config>
|
||||
</FileSet>
|
||||
<FileSet Name="lab_2_packetizer_0_0" Type="BlockSrcs" RelSrcDir="$PSRCDIR/lab_2_packetizer_0_0" RelGenDir="$PGENDIR/lab_2_packetizer_0_0">
|
||||
<Config>
|
||||
<Option Name="TopModule" Val="lab_2_packetizer_0_0"/>
|
||||
<Option Name="UseBlackboxStub" Val="1"/>
|
||||
</Config>
|
||||
</FileSet>
|
||||
<FileSet Name="lab_2_rgb2gray_0_0" Type="BlockSrcs" RelSrcDir="$PSRCDIR/lab_2_rgb2gray_0_0" RelGenDir="$PGENDIR/lab_2_rgb2gray_0_0">
|
||||
<Config>
|
||||
<Option Name="TopModule" Val="lab_2_rgb2gray_0_0"/>
|
||||
<Option Name="UseBlackboxStub" Val="1"/>
|
||||
</Config>
|
||||
</FileSet>
|
||||
<FileSet Name="lab_2_led_blinker_0_0" Type="BlockSrcs" RelSrcDir="$PSRCDIR/lab_2_led_blinker_0_0" RelGenDir="$PGENDIR/lab_2_led_blinker_0_0">
|
||||
<Config>
|
||||
<Option Name="TopModule" Val="lab_2_led_blinker_0_0"/>
|
||||
<Option Name="UseBlackboxStub" Val="1"/>
|
||||
</Config>
|
||||
</FileSet>
|
||||
<FileSet Name="lab_2_img_conv_0_0" Type="BlockSrcs" RelSrcDir="$PSRCDIR/lab_2_img_conv_0_0" RelGenDir="$PGENDIR/lab_2_img_conv_0_0">
|
||||
<Config>
|
||||
<Option Name="TopModule" Val="lab_2_img_conv_0_0"/>
|
||||
<Option Name="UseBlackboxStub" Val="1"/>
|
||||
</Config>
|
||||
</FileSet>
|
||||
<FileSet Name="lab_2_led_blinker_1_0" Type="BlockSrcs" RelSrcDir="$PSRCDIR/lab_2_led_blinker_1_0" RelGenDir="$PGENDIR/lab_2_led_blinker_1_0">
|
||||
<Config>
|
||||
<Option Name="TopModule" Val="lab_2_led_blinker_1_0"/>
|
||||
<Option Name="UseBlackboxStub" Val="1"/>
|
||||
</Config>
|
||||
</FileSet>
|
||||
<FileSet Name="lab_2_led_blinker_2_0" Type="BlockSrcs" RelSrcDir="$PSRCDIR/lab_2_led_blinker_2_0" RelGenDir="$PGENDIR/lab_2_led_blinker_2_0">
|
||||
<Config>
|
||||
<Option Name="TopModule" Val="lab_2_led_blinker_2_0"/>
|
||||
<Option Name="UseBlackboxStub" Val="1"/>
|
||||
</Config>
|
||||
</FileSet>
|
||||
<FileSet Name="lab_2_clk_wiz_0_0" Type="BlockSrcs" RelSrcDir="$PSRCDIR/lab_2_clk_wiz_0_0" RelGenDir="$PGENDIR/lab_2_clk_wiz_0_0">
|
||||
<Config>
|
||||
<Option Name="TopModule" Val="lab_2_clk_wiz_0_0"/>
|
||||
<Option Name="UseBlackboxStub" Val="1"/>
|
||||
</Config>
|
||||
</FileSet>
|
||||
<FileSet Name="lab_2_proc_sys_reset_0_0" Type="BlockSrcs" RelSrcDir="$PSRCDIR/lab_2_proc_sys_reset_0_0" RelGenDir="$PGENDIR/lab_2_proc_sys_reset_0_0">
|
||||
<Config>
|
||||
<Option Name="TopModule" Val="lab_2_proc_sys_reset_0_0"/>
|
||||
<Option Name="UseBlackboxStub" Val="1"/>
|
||||
</Config>
|
||||
</FileSet>
|
||||
<FileSet Name="lab_2_AXI4Stream_UART_0_0" Type="BlockSrcs" RelSrcDir="$PSRCDIR/lab_2_AXI4Stream_UART_0_0" RelGenDir="$PGENDIR/lab_2_AXI4Stream_UART_0_0">
|
||||
<Config>
|
||||
<Option Name="TopModule" Val="lab_2_AXI4Stream_UART_0_0"/>
|
||||
<Option Name="UseBlackboxStub" Val="1"/>
|
||||
</Config>
|
||||
</FileSet>
|
||||
<FileSet Name="lab_2_system_ila_0_1" Type="BlockSrcs" RelSrcDir="$PSRCDIR/lab_2_system_ila_0_1" RelGenDir="$PGENDIR/lab_2_system_ila_0_1">
|
||||
<Config>
|
||||
<Option Name="TopModule" Val="lab_2_system_ila_0_1"/>
|
||||
<Option Name="UseBlackboxStub" Val="1"/>
|
||||
</Config>
|
||||
</FileSet>
|
||||
</FileSets>
|
||||
<Simulators>
|
||||
<Simulator Name="XSim">
|
||||
@@ -266,340 +195,20 @@
|
||||
<Runs Version="1" Minor="15">
|
||||
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|
||||
<Run Id="lab_2_led_blinker_1_0_impl_1" Type="Ft2:EntireDesign" Part="xc7a35tcpg236-1" ConstrsSet="lab_2_led_blinker_1_0" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" SynthRun="lab_2_led_blinker_1_0_synth_1" IncludeInArchive="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/lab_2_led_blinker_1_0_impl_1">
|
||||
<Strategy Version="1" Minor="2">
|
||||
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2020"/>
|
||||
<Step Id="init_design"/>
|
||||
<Step Id="opt_design"/>
|
||||
<Step Id="power_opt_design"/>
|
||||
<Step Id="place_design"/>
|
||||
<Step Id="post_place_power_opt_design"/>
|
||||
<Step Id="phys_opt_design"/>
|
||||
<Step Id="route_design"/>
|
||||
<Step Id="post_route_phys_opt_design"/>
|
||||
<Step Id="write_bitstream"/>
|
||||
</Strategy>
|
||||
<ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2020"/>
|
||||
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
|
||||
<RQSFiles/>
|
||||
</Run>
|
||||
<Run Id="lab_2_led_blinker_2_0_impl_1" Type="Ft2:EntireDesign" Part="xc7a35tcpg236-1" ConstrsSet="lab_2_led_blinker_2_0" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" SynthRun="lab_2_led_blinker_2_0_synth_1" IncludeInArchive="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/lab_2_led_blinker_2_0_impl_1">
|
||||
<Strategy Version="1" Minor="2">
|
||||
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2020"/>
|
||||
<Step Id="init_design"/>
|
||||
<Step Id="opt_design"/>
|
||||
<Step Id="power_opt_design"/>
|
||||
<Step Id="place_design"/>
|
||||
<Step Id="post_place_power_opt_design"/>
|
||||
<Step Id="phys_opt_design"/>
|
||||
<Step Id="route_design"/>
|
||||
<Step Id="post_route_phys_opt_design"/>
|
||||
<Step Id="write_bitstream"/>
|
||||
</Strategy>
|
||||
<ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2020"/>
|
||||
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
|
||||
<RQSFiles/>
|
||||
</Run>
|
||||
<Run Id="lab_2_clk_wiz_0_0_impl_1" Type="Ft2:EntireDesign" Part="xc7a35tcpg236-1" ConstrsSet="lab_2_clk_wiz_0_0" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" SynthRun="lab_2_clk_wiz_0_0_synth_1" IncludeInArchive="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/lab_2_clk_wiz_0_0_impl_1">
|
||||
<Strategy Version="1" Minor="2">
|
||||
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2020"/>
|
||||
<Step Id="init_design"/>
|
||||
<Step Id="opt_design"/>
|
||||
<Step Id="power_opt_design"/>
|
||||
<Step Id="place_design"/>
|
||||
<Step Id="post_place_power_opt_design"/>
|
||||
<Step Id="phys_opt_design"/>
|
||||
<Step Id="route_design"/>
|
||||
<Step Id="post_route_phys_opt_design"/>
|
||||
<Step Id="write_bitstream"/>
|
||||
</Strategy>
|
||||
<ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2020"/>
|
||||
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
|
||||
<RQSFiles/>
|
||||
</Run>
|
||||
<Run Id="lab_2_proc_sys_reset_0_0_impl_1" Type="Ft2:EntireDesign" Part="xc7a35tcpg236-1" ConstrsSet="lab_2_proc_sys_reset_0_0" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" SynthRun="lab_2_proc_sys_reset_0_0_synth_1" IncludeInArchive="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/lab_2_proc_sys_reset_0_0_impl_1">
|
||||
<Strategy Version="1" Minor="2">
|
||||
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2020"/>
|
||||
<Step Id="init_design"/>
|
||||
<Step Id="opt_design"/>
|
||||
<Step Id="power_opt_design"/>
|
||||
<Step Id="place_design"/>
|
||||
<Step Id="post_place_power_opt_design"/>
|
||||
<Step Id="phys_opt_design"/>
|
||||
<Step Id="route_design"/>
|
||||
<Step Id="post_route_phys_opt_design"/>
|
||||
<Step Id="write_bitstream"/>
|
||||
</Strategy>
|
||||
<ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2020"/>
|
||||
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
|
||||
<RQSFiles/>
|
||||
</Run>
|
||||
<Run Id="lab_2_AXI4Stream_UART_0_0_impl_1" Type="Ft2:EntireDesign" Part="xc7a35tcpg236-1" ConstrsSet="lab_2_AXI4Stream_UART_0_0" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" SynthRun="lab_2_AXI4Stream_UART_0_0_synth_1" IncludeInArchive="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/lab_2_AXI4Stream_UART_0_0_impl_1">
|
||||
<Strategy Version="1" Minor="2">
|
||||
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2020"/>
|
||||
<Step Id="init_design"/>
|
||||
<Step Id="opt_design"/>
|
||||
<Step Id="power_opt_design"/>
|
||||
<Step Id="place_design"/>
|
||||
<Step Id="post_place_power_opt_design"/>
|
||||
<Step Id="phys_opt_design"/>
|
||||
<Step Id="route_design"/>
|
||||
<Step Id="post_route_phys_opt_design"/>
|
||||
<Step Id="write_bitstream"/>
|
||||
</Strategy>
|
||||
<ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2020"/>
|
||||
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
|
||||
<RQSFiles/>
|
||||
</Run>
|
||||
<Run Id="lab_2_system_ila_0_1_impl_1" Type="Ft2:EntireDesign" Part="xc7a35tcpg236-1" ConstrsSet="lab_2_system_ila_0_1" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" SynthRun="lab_2_system_ila_0_1_synth_1" IncludeInArchive="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/lab_2_system_ila_0_1_impl_1">
|
||||
<Strategy Version="1" Minor="2">
|
||||
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2020"/>
|
||||
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2020">
|
||||
<Desc>Default settings for Implementation.</Desc>
|
||||
</StratHandle>
|
||||
<Step Id="init_design"/>
|
||||
<Step Id="opt_design"/>
|
||||
<Step Id="power_opt_design"/>
|
||||
@@ -615,7 +224,9 @@
|
||||
<RQSFiles/>
|
||||
</Run>
|
||||
</Runs>
|
||||
<Board/>
|
||||
<Board>
|
||||
<Jumpers/>
|
||||
</Board>
|
||||
<DashboardSummary Version="1" Minor="0">
|
||||
<Dashboards>
|
||||
<Dashboard Name="default_dashboard">
|
||||
|
||||
Reference in New Issue
Block a user