Add lab_3_wrapper VHDL file and update project files for LAB3

LAB3/design/lab_3/hdl/lab_3_wrapper.vhd

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+--Copyright 1986-2020 Xilinx, Inc. All Rights Reserved.
+----------------------------------------------------------------------------------
+--Tool Version: Vivado v.2020.2 (win64) Build 3064766 Wed Nov 18 09:12:45 MST 2020
+--Date        : Mon May 12 14:54:08 2025
+--Host        : Davide-Samsung running 64-bit major release  (build 9200)
+--Command     : generate_target lab_3_wrapper.bd
+--Design      : lab_3_wrapper
+--Purpose     : IP block netlist
+----------------------------------------------------------------------------------
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+library UNISIM;
+use UNISIM.VCOMPONENTS.ALL;
+entity lab_3_wrapper is
+  port (
+    LED : out STD_LOGIC_VECTOR ( 15 downto 0 );
+    SPI_M_0_io0_io : inout STD_LOGIC;
+    SPI_M_0_io1_io : inout STD_LOGIC;
+    SPI_M_0_sck_io : inout STD_LOGIC;
+    SPI_M_0_ss_io : inout STD_LOGIC;
+    effect : in STD_LOGIC;
+    lfo_enable : in STD_LOGIC;
+    reset : in STD_LOGIC;
+    rx_lrck_0 : out STD_LOGIC;
+    rx_mclk_0 : out STD_LOGIC;
+    rx_sclk_0 : out STD_LOGIC;
+    rx_sdin_0 : in STD_LOGIC;
+    sys_clock : in STD_LOGIC;
+    tx_lrck_0 : out STD_LOGIC;
+    tx_mclk_0 : out STD_LOGIC;
+    tx_sclk_0 : out STD_LOGIC;
+    tx_sdout_0 : out STD_LOGIC
+  );
+end lab_3_wrapper;
+
+architecture STRUCTURE of lab_3_wrapper is
+  component lab_3 is
+  port (
+    sys_clock : in STD_LOGIC;
+    reset : in STD_LOGIC;
+    tx_lrck_0 : out STD_LOGIC;
+    rx_sdin_0 : in STD_LOGIC;
+    rx_sclk_0 : out STD_LOGIC;
+    rx_lrck_0 : out STD_LOGIC;
+    rx_mclk_0 : out STD_LOGIC;
+    tx_sdout_0 : out STD_LOGIC;
+    tx_sclk_0 : out STD_LOGIC;
+    tx_mclk_0 : out STD_LOGIC;
+    lfo_enable : in STD_LOGIC;
+    effect : in STD_LOGIC;
+    LED : out STD_LOGIC_VECTOR ( 15 downto 0 );
+    SPI_M_0_sck_t : out STD_LOGIC;
+    SPI_M_0_io1_o : out STD_LOGIC;
+    SPI_M_0_ss_t : out STD_LOGIC;
+    SPI_M_0_io0_o : out STD_LOGIC;
+    SPI_M_0_sck_i : in STD_LOGIC;
+    SPI_M_0_ss_o : out STD_LOGIC;
+    SPI_M_0_io0_t : out STD_LOGIC;
+    SPI_M_0_io1_t : out STD_LOGIC;
+    SPI_M_0_sck_o : out STD_LOGIC;
+    SPI_M_0_ss_i : in STD_LOGIC;
+    SPI_M_0_io1_i : in STD_LOGIC;
+    SPI_M_0_io0_i : in STD_LOGIC
+  );
+  end component lab_3;
+  component IOBUF is
+  port (
+    I : in STD_LOGIC;
+    O : out STD_LOGIC;
+    T : in STD_LOGIC;
+    IO : inout STD_LOGIC
+  );
+  end component IOBUF;
+  signal SPI_M_0_io0_i : STD_LOGIC;
+  signal SPI_M_0_io0_o : STD_LOGIC;
+  signal SPI_M_0_io0_t : STD_LOGIC;
+  signal SPI_M_0_io1_i : STD_LOGIC;
+  signal SPI_M_0_io1_o : STD_LOGIC;
+  signal SPI_M_0_io1_t : STD_LOGIC;
+  signal SPI_M_0_sck_i : STD_LOGIC;
+  signal SPI_M_0_sck_o : STD_LOGIC;
+  signal SPI_M_0_sck_t : STD_LOGIC;
+  signal SPI_M_0_ss_i : STD_LOGIC;
+  signal SPI_M_0_ss_o : STD_LOGIC;
+  signal SPI_M_0_ss_t : STD_LOGIC;
+begin
+SPI_M_0_io0_iobuf: component IOBUF
+     port map (
+      I => SPI_M_0_io0_o,
+      IO => SPI_M_0_io0_io,
+      O => SPI_M_0_io0_i,
+      T => SPI_M_0_io0_t
+    );
+SPI_M_0_io1_iobuf: component IOBUF
+     port map (
+      I => SPI_M_0_io1_o,
+      IO => SPI_M_0_io1_io,
+      O => SPI_M_0_io1_i,
+      T => SPI_M_0_io1_t
+    );
+SPI_M_0_sck_iobuf: component IOBUF
+     port map (
+      I => SPI_M_0_sck_o,
+      IO => SPI_M_0_sck_io,
+      O => SPI_M_0_sck_i,
+      T => SPI_M_0_sck_t
+    );
+SPI_M_0_ss_iobuf: component IOBUF
+     port map (
+      I => SPI_M_0_ss_o,
+      IO => SPI_M_0_ss_io,
+      O => SPI_M_0_ss_i,
+      T => SPI_M_0_ss_t
+    );
+lab_3_i: component lab_3
+     port map (
+      LED(15 downto 0) => LED(15 downto 0),
+      SPI_M_0_io0_i => SPI_M_0_io0_i,
+      SPI_M_0_io0_o => SPI_M_0_io0_o,
+      SPI_M_0_io0_t => SPI_M_0_io0_t,
+      SPI_M_0_io1_i => SPI_M_0_io1_i,
+      SPI_M_0_io1_o => SPI_M_0_io1_o,
+      SPI_M_0_io1_t => SPI_M_0_io1_t,
+      SPI_M_0_sck_i => SPI_M_0_sck_i,
+      SPI_M_0_sck_o => SPI_M_0_sck_o,
+      SPI_M_0_sck_t => SPI_M_0_sck_t,
+      SPI_M_0_ss_i => SPI_M_0_ss_i,
+      SPI_M_0_ss_o => SPI_M_0_ss_o,
+      SPI_M_0_ss_t => SPI_M_0_ss_t,
+      effect => effect,
+      lfo_enable => lfo_enable,
+      reset => reset,
+      rx_lrck_0 => rx_lrck_0,
+      rx_mclk_0 => rx_mclk_0,
+      rx_sclk_0 => rx_sclk_0,
+      rx_sdin_0 => rx_sdin_0,
+      sys_clock => sys_clock,
+      tx_lrck_0 => tx_lrck_0,
+      tx_mclk_0 => tx_mclk_0,
+      tx_sclk_0 => tx_sclk_0,
+      tx_sdout_0 => tx_sdout_0
+    );
+end STRUCTURE;