2
.gitignore
vendored
2
.gitignore
vendored
@@ -42,7 +42,6 @@
|
||||
*.qws
|
||||
*.wdf
|
||||
*.lpr
|
||||
*.xdc
|
||||
*.bxml
|
||||
|
||||
|
||||
@@ -76,6 +75,7 @@ vivado*.backup.log
|
||||
**/design/**/synth/
|
||||
**/design/**/ui/
|
||||
**/design/**/hw_handoff/
|
||||
**/design/**/*.xdc
|
||||
|
||||
# Other files
|
||||
**/test/*.zip
|
||||
@@ -1,8 +1,8 @@
|
||||
--Copyright 1986-2020 Xilinx, Inc. All Rights Reserved.
|
||||
----------------------------------------------------------------------------------
|
||||
--Tool Version: Vivado v.2020.2 (win64) Build 3064766 Wed Nov 18 09:12:45 MST 2020
|
||||
--Date : Fri Apr 25 22:08:38 2025
|
||||
--Host : DavideASUS running 64-bit major release (build 9200)
|
||||
--Date : Mon May 12 14:33:04 2025
|
||||
--Host : Davide-Samsung running 64-bit major release (build 9200)
|
||||
--Command : generate_target lab_2_wrapper.bd
|
||||
--Design : lab_2_wrapper
|
||||
--Purpose : IP block netlist
|
||||
|
||||
@@ -1176,11 +1176,11 @@
|
||||
"system_ila_0/SLOT_2_AXIS"
|
||||
]
|
||||
},
|
||||
"img_conv_0_m_axis": {
|
||||
"Conn": {
|
||||
"interface_ports": [
|
||||
"img_conv_0/m_axis",
|
||||
"packetizer_0/s_axis",
|
||||
"system_ila_0/SLOT_1_AXIS"
|
||||
"rgb2gray_0/s_axis",
|
||||
"depacketizer_0/m_axis",
|
||||
"system_ila_0/SLOT_0_AXIS"
|
||||
]
|
||||
},
|
||||
"AXI4Stream_UART_0_UART": {
|
||||
@@ -1201,11 +1201,11 @@
|
||||
"AXI4Stream_UART_0/S00_AXIS_TX"
|
||||
]
|
||||
},
|
||||
"Conn": {
|
||||
"img_conv_0_m_axis": {
|
||||
"interface_ports": [
|
||||
"rgb2gray_0/s_axis",
|
||||
"depacketizer_0/m_axis",
|
||||
"system_ila_0/SLOT_0_AXIS"
|
||||
"img_conv_0/m_axis",
|
||||
"packetizer_0/s_axis",
|
||||
"system_ila_0/SLOT_1_AXIS"
|
||||
]
|
||||
}
|
||||
},
|
||||
|
||||
@@ -21,22 +21,22 @@
|
||||
<key attr.name="vert_type" attr.type="string" for="node" id="VT"/>
|
||||
<graph edgedefault="undirected" id="G" parse.edgeids="canonical" parse.nodeids="canonical" parse.order="nodesfirst">
|
||||
<node id="n0">
|
||||
<data key="TU">active</data>
|
||||
<data key="VH">2</data>
|
||||
<data key="VT">PM</data>
|
||||
<data key="VM">lab_2</data>
|
||||
<data key="VT">VR</data>
|
||||
</node>
|
||||
<node id="n1">
|
||||
<data key="VM">lab_2</data>
|
||||
<data key="VT">BC</data>
|
||||
</node>
|
||||
<node id="n2">
|
||||
<data key="TU">active</data>
|
||||
<data key="VH">2</data>
|
||||
<data key="VM">lab_2</data>
|
||||
<data key="VT">VR</data>
|
||||
<data key="VT">PM</data>
|
||||
</node>
|
||||
<edge id="e0" source="n1" target="n2">
|
||||
<edge id="e0" source="n1" target="n0">
|
||||
</edge>
|
||||
<edge id="e1" source="n2" target="n0">
|
||||
<edge id="e1" source="n0" target="n2">
|
||||
</edge>
|
||||
</graph>
|
||||
</graphml>
|
||||
|
||||
@@ -55,13 +55,13 @@
|
||||
<Option Name="WTVcsLaunchSim" Val="0"/>
|
||||
<Option Name="WTRivieraLaunchSim" Val="0"/>
|
||||
<Option Name="WTActivehdlLaunchSim" Val="0"/>
|
||||
<Option Name="WTXSimExportSim" Val="6"/>
|
||||
<Option Name="WTModelSimExportSim" Val="6"/>
|
||||
<Option Name="WTQuestaExportSim" Val="6"/>
|
||||
<Option Name="WTIesExportSim" Val="6"/>
|
||||
<Option Name="WTVcsExportSim" Val="6"/>
|
||||
<Option Name="WTRivieraExportSim" Val="6"/>
|
||||
<Option Name="WTActivehdlExportSim" Val="6"/>
|
||||
<Option Name="WTXSimExportSim" Val="7"/>
|
||||
<Option Name="WTModelSimExportSim" Val="7"/>
|
||||
<Option Name="WTQuestaExportSim" Val="7"/>
|
||||
<Option Name="WTIesExportSim" Val="7"/>
|
||||
<Option Name="WTVcsExportSim" Val="7"/>
|
||||
<Option Name="WTRivieraExportSim" Val="7"/>
|
||||
<Option Name="WTActivehdlExportSim" Val="7"/>
|
||||
<Option Name="GenerateIPUpgradeLog" Val="TRUE"/>
|
||||
<Option Name="XSimRadix" Val="hex"/>
|
||||
<Option Name="XSimTimeUnit" Val="ns"/>
|
||||
@@ -203,17 +203,16 @@
|
||||
</Simulator>
|
||||
</Simulators>
|
||||
<Runs Version="1" Minor="15">
|
||||
<Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7a35tcpg236-1" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" Dir="$PRUNDIR/synth_1" IncludeInArchive="true" AutoIncrementalDir="$PPRDIR/../../lab2/lab2.srcs/utils_1/imports/synth_1">
|
||||
<Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7a35tcpg236-1" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" IncludeInArchive="true" AutoIncrementalDir="$PPRDIR/../../lab2/lab2.srcs/utils_1/imports/synth_1">
|
||||
<Strategy Version="1" Minor="2">
|
||||
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2020"/>
|
||||
<Step Id="synth_design"/>
|
||||
</Strategy>
|
||||
<GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
|
||||
<ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2020"/>
|
||||
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
|
||||
<RQSFiles/>
|
||||
</Run>
|
||||
<Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7a35tcpg236-1" ConstrsSet="constrs_1" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" Dir="$PRUNDIR/impl_1" SynthRun="synth_1" IncludeInArchive="true" GenFullBitstream="true" AutoIncrementalDir="$PPRDIR/../../lab2/lab2.srcs/utils_1/imports/impl_1">
|
||||
<Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7a35tcpg236-1" ConstrsSet="constrs_1" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" SynthRun="synth_1" IncludeInArchive="true" GenFullBitstream="true" AutoIncrementalDir="$PPRDIR/../../lab2/lab2.srcs/utils_1/imports/impl_1">
|
||||
<Strategy Version="1" Minor="2">
|
||||
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2020"/>
|
||||
<Step Id="init_design"/>
|
||||
@@ -226,7 +225,6 @@
|
||||
<Step Id="post_route_phys_opt_design"/>
|
||||
<Step Id="write_bitstream"/>
|
||||
</Strategy>
|
||||
<GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
|
||||
<ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2020"/>
|
||||
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
|
||||
<RQSFiles/>
|
||||
|
||||
13
LAB3/cons/io.xdc
Normal file
13
LAB3/cons/io.xdc
Normal file
@@ -0,0 +1,13 @@
|
||||
# SPI connected to JA, top row
|
||||
set_property PACKAGE_PIN J1 [get_ports SPI_M_0_ss_io]
|
||||
set_property PACKAGE_PIN G2 [get_ports SPI_M_0_sck_io]
|
||||
set_property PACKAGE_PIN L2 [get_ports SPI_M_0_io0_io]
|
||||
set_property PACKAGE_PIN J2 [get_ports SPI_M_0_io1_io]
|
||||
set_property IOSTANDARD LVCMOS33 [get_ports SPI_M_0_io0_io]
|
||||
set_property IOSTANDARD LVCMOS33 [get_ports SPI_M_0_io1_io]
|
||||
set_property IOSTANDARD LVCMOS33 [get_ports SPI_M_0_sck_io]
|
||||
set_property IOSTANDARD LVCMOS33 [get_ports SPI_M_0_ss_io]
|
||||
set_property OFFCHIP_TERM NONE [get_ports SPI_M_0_io0_io]
|
||||
set_property OFFCHIP_TERM NONE [get_ports SPI_M_0_io1_io]
|
||||
set_property OFFCHIP_TERM NONE [get_ports SPI_M_0_sck_io]
|
||||
set_property OFFCHIP_TERM NONE [get_ports SPI_M_0_ss_io]
|
||||
2104
LAB3/design/lab_3/lab_3.bd
Normal file
2104
LAB3/design/lab_3/lab_3.bd
Normal file
File diff suppressed because it is too large
Load Diff
42
LAB3/design/lab_3/lab_3.bda
Normal file
42
LAB3/design/lab_3/lab_3.bda
Normal file
@@ -0,0 +1,42 @@
|
||||
<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
|
||||
<graphml xmlns="http://graphml.graphdrawing.org/xmlns" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:schemaLocation="http://graphml.graphdrawing.org/xmlns http://graphml.graphdrawing.org/xmlns/1.0/graphml.xsd">
|
||||
<key attr.name="base_addr" attr.type="string" for="node" id="BA"/>
|
||||
<key attr.name="base_param" attr.type="string" for="node" id="BP"/>
|
||||
<key attr.name="edge_hid" attr.type="int" for="edge" id="EH"/>
|
||||
<key attr.name="high_addr" attr.type="string" for="node" id="HA"/>
|
||||
<key attr.name="high_param" attr.type="string" for="node" id="HP"/>
|
||||
<key attr.name="master_addrspace" attr.type="string" for="node" id="MA"/>
|
||||
<key attr.name="master_instance" attr.type="string" for="node" id="MX"/>
|
||||
<key attr.name="master_interface" attr.type="string" for="node" id="MI"/>
|
||||
<key attr.name="master_segment" attr.type="string" for="node" id="MS"/>
|
||||
<key attr.name="master_vlnv" attr.type="string" for="node" id="MV"/>
|
||||
<key attr.name="memory_type" attr.type="string" for="node" id="TM"/>
|
||||
<key attr.name="slave_instance" attr.type="string" for="node" id="SX"/>
|
||||
<key attr.name="slave_interface" attr.type="string" for="node" id="SI"/>
|
||||
<key attr.name="slave_segment" attr.type="string" for="node" id="SS"/>
|
||||
<key attr.name="slave_vlnv" attr.type="string" for="node" id="SV"/>
|
||||
<key attr.name="usage_type" attr.type="string" for="node" id="TU"/>
|
||||
<key attr.name="vert_hid" attr.type="int" for="node" id="VH"/>
|
||||
<key attr.name="vert_name" attr.type="string" for="node" id="VM"/>
|
||||
<key attr.name="vert_type" attr.type="string" for="node" id="VT"/>
|
||||
<graph edgedefault="undirected" id="G" parse.edgeids="canonical" parse.nodeids="canonical" parse.order="nodesfirst">
|
||||
<node id="n0">
|
||||
<data key="VH">2</data>
|
||||
<data key="VM">lab_3</data>
|
||||
<data key="VT">VR</data>
|
||||
</node>
|
||||
<node id="n1">
|
||||
<data key="TU">active</data>
|
||||
<data key="VH">2</data>
|
||||
<data key="VT">PM</data>
|
||||
</node>
|
||||
<node id="n2">
|
||||
<data key="VM">lab_3</data>
|
||||
<data key="VT">BC</data>
|
||||
</node>
|
||||
<edge id="e0" source="n2" target="n0">
|
||||
</edge>
|
||||
<edge id="e1" source="n0" target="n1">
|
||||
</edge>
|
||||
</graph>
|
||||
</graphml>
|
||||
685
LAB3/ip/axi4-stream-dual-i2s/component.xml
Normal file
685
LAB3/ip/axi4-stream-dual-i2s/component.xml
Normal file
@@ -0,0 +1,685 @@
|
||||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<spirit:component xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
|
||||
<spirit:vendor>DigiLAB</spirit:vendor>
|
||||
<spirit:library>ip</spirit:library>
|
||||
<spirit:name>axis_dual_i2s</spirit:name>
|
||||
<spirit:version>1.0</spirit:version>
|
||||
<spirit:busInterfaces>
|
||||
<spirit:busInterface>
|
||||
<spirit:name>m_axis</spirit:name>
|
||||
<spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="axis" spirit:version="1.0"/>
|
||||
<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="axis_rtl" spirit:version="1.0"/>
|
||||
<spirit:master/>
|
||||
<spirit:portMaps>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>TDATA</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>m_axis_tdata</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>TLAST</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>m_axis_tlast</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>TVALID</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>m_axis_tvalid</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>TREADY</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>m_axis_tready</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
</spirit:portMaps>
|
||||
</spirit:busInterface>
|
||||
<spirit:busInterface>
|
||||
<spirit:name>s_axis</spirit:name>
|
||||
<spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="axis" spirit:version="1.0"/>
|
||||
<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="axis_rtl" spirit:version="1.0"/>
|
||||
<spirit:slave/>
|
||||
<spirit:portMaps>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>TDATA</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>s_axis_tdata</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>TLAST</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>s_axis_tlast</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>TVALID</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>s_axis_tvalid</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>TREADY</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>s_axis_tready</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
</spirit:portMaps>
|
||||
</spirit:busInterface>
|
||||
<spirit:busInterface>
|
||||
<spirit:name>aresetn</spirit:name>
|
||||
<spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset" spirit:version="1.0"/>
|
||||
<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset_rtl" spirit:version="1.0"/>
|
||||
<spirit:slave/>
|
||||
<spirit:portMaps>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>RST</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>aresetn</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
</spirit:portMaps>
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>POLARITY</spirit:name>
|
||||
<spirit:value spirit:id="BUSIFPARAM_VALUE.ARESETN.POLARITY" spirit:choiceRef="choice_list_9d8b0d81">ACTIVE_LOW</spirit:value>
|
||||
</spirit:parameter>
|
||||
</spirit:parameters>
|
||||
</spirit:busInterface>
|
||||
<spirit:busInterface>
|
||||
<spirit:name>i2s_resetn</spirit:name>
|
||||
<spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset" spirit:version="1.0"/>
|
||||
<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset_rtl" spirit:version="1.0"/>
|
||||
<spirit:slave/>
|
||||
<spirit:portMaps>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>RST</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>i2s_resetn</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
</spirit:portMaps>
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>POLARITY</spirit:name>
|
||||
<spirit:value spirit:id="BUSIFPARAM_VALUE.I2S_RESETN.POLARITY" spirit:choiceRef="choice_list_9d8b0d81">ACTIVE_LOW</spirit:value>
|
||||
</spirit:parameter>
|
||||
</spirit:parameters>
|
||||
</spirit:busInterface>
|
||||
<spirit:busInterface>
|
||||
<spirit:name>aclk</spirit:name>
|
||||
<spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock" spirit:version="1.0"/>
|
||||
<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock_rtl" spirit:version="1.0"/>
|
||||
<spirit:slave/>
|
||||
<spirit:portMaps>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>CLK</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>aclk</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
</spirit:portMaps>
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>ASSOCIATED_BUSIF</spirit:name>
|
||||
<spirit:value spirit:id="BUSIFPARAM_VALUE.ACLK.ASSOCIATED_BUSIF">m_axis:s_axis</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>ASSOCIATED_RESET</spirit:name>
|
||||
<spirit:value spirit:id="BUSIFPARAM_VALUE.ACLK.ASSOCIATED_RESET">aresetn</spirit:value>
|
||||
</spirit:parameter>
|
||||
</spirit:parameters>
|
||||
</spirit:busInterface>
|
||||
<spirit:busInterface>
|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
<spirit:name>i2s_clk</spirit:name>
|
||||
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|
||||
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||||
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||||
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||||
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|
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|
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||||
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|
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|
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|
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|
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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||||
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||||
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||||
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||||
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||||
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|
||||
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||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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||||
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||||
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|
||||
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|
||||
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||||
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|
||||
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||||
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||||
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||||
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||||
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||||
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||||
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<spirit:userFileType>XGUI_VERSION_2</spirit:userFileType>
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||||
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||||
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||||
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||||
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|
||||
159
LAB3/ip/axi4-stream-dual-i2s/hdl/axis_dual_i2s.v
Normal file
159
LAB3/ip/axi4-stream-dual-i2s/hdl/axis_dual_i2s.v
Normal file
@@ -0,0 +1,159 @@
|
||||
`timescale 1ns / 1ps
|
||||
`default_nettype none
|
||||
//////////////////////////////////////////////////////////////////////////////////
|
||||
// Company: Digilent & Politecnico di Milano
|
||||
// Engineer: Arthur Brown, Nicola Corna, Fabio Garzetti, Nicola Lusardi
|
||||
//
|
||||
// Create Date: 14/05/2019
|
||||
// Module Name: axis_i2s
|
||||
// Description: AXI-Stream I2S controller
|
||||
// Generates clocks and select signals required to place each of the ICs on the Pmod I2S2 into slave mode.
|
||||
// Data is 24-bit, shifted one serial clock right from the LRCK boundaries.
|
||||
// This module only supports 44.1KHz sample rate, and expects the frequency of axis_clk to be approx 22.591MHz.
|
||||
// At the end of each I2S frame, a 2-word packet is made available on the AXIS master interface. Further packets will be discarded
|
||||
// until the current packet is accepted by an AXIS slave.
|
||||
// Whenever a 2-word packet is received on the AXIS slave interface, it is transmitted over the I2S interface on the next frame.
|
||||
// Each packet consists of two 3-byte words, starting with left audio channel data, followed by right channel data.
|
||||
//
|
||||
// Revision:
|
||||
// Revision 0.01 - File Created
|
||||
// Revision 0.02 - Use 24-bit interfaces
|
||||
// Additional Comments:
|
||||
//
|
||||
//////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
module axis_dual_i2s (
|
||||
input wire axis_clk, // require: approx 22.591MHz
|
||||
input wire axis_resetn,
|
||||
|
||||
input wire [23:0] tx_axis_s_data,
|
||||
input wire tx_axis_s_valid,
|
||||
output reg tx_axis_s_ready = 1'b0,
|
||||
input wire tx_axis_s_last,
|
||||
|
||||
output wire [23:0] rx_axis_m_data,
|
||||
output reg rx_axis_m_valid = 1'b0,
|
||||
input wire rx_axis_m_ready,
|
||||
output reg rx_axis_m_last = 1'b0,
|
||||
|
||||
output wire tx_mclk,
|
||||
output wire tx_lrck,
|
||||
output wire tx_sclk,
|
||||
output reg tx_sdout,
|
||||
output wire rx_mclk,
|
||||
output wire rx_lrck,
|
||||
output wire rx_sclk,
|
||||
input wire rx_sdin
|
||||
);
|
||||
reg [8:0] count = 9'd0;
|
||||
localparam EOF_COUNT = 9'd455; // end of full I2S frame
|
||||
|
||||
always@(posedge axis_clk)
|
||||
count <= count + 1;
|
||||
|
||||
wire lrck = count[8];
|
||||
wire sclk = count[2];
|
||||
wire mclk = axis_clk;
|
||||
assign tx_lrck = lrck;
|
||||
assign tx_sclk = sclk;
|
||||
assign tx_mclk = mclk;
|
||||
assign rx_lrck = lrck;
|
||||
assign rx_sclk = sclk;
|
||||
assign rx_mclk = mclk;
|
||||
|
||||
/* AXIS SLAVE CONTROLLER */
|
||||
reg [23:0] tx_data_l = 0;
|
||||
reg [23:0] tx_data_r = 0;
|
||||
|
||||
always@(posedge axis_clk)
|
||||
if (axis_resetn == 1'b0)
|
||||
tx_axis_s_ready <= 1'b0;
|
||||
else if (tx_axis_s_ready == 1'b1 && tx_axis_s_valid == 1'b1 && tx_axis_s_last == 1'b1) // end of packet, cannot accept data until current one has been transmitted
|
||||
tx_axis_s_ready <= 1'b0;
|
||||
else if (count == 9'b0) // beginning of I2S frame, in order to avoid tearing, cannot accept data until frame complete
|
||||
tx_axis_s_ready <= 1'b0;
|
||||
else if (count == EOF_COUNT) // end of I2S frame, can accept data
|
||||
tx_axis_s_ready <= 1'b1;
|
||||
|
||||
always@(posedge axis_clk)
|
||||
if (axis_resetn == 1'b0) begin
|
||||
tx_data_r <= 24'b0;
|
||||
tx_data_l <= 24'b0;
|
||||
end else if (tx_axis_s_valid == 1'b1 && tx_axis_s_ready == 1'b1)
|
||||
if (tx_axis_s_last == 1'b1)
|
||||
tx_data_r <= tx_axis_s_data;
|
||||
else
|
||||
tx_data_l <= tx_axis_s_data;
|
||||
|
||||
/* I2S TRANSMIT SHIFT REGISTERS */
|
||||
reg [23:0] tx_data_l_shift = 24'b0;
|
||||
reg [23:0] tx_data_r_shift = 24'b0;
|
||||
|
||||
always@(posedge axis_clk)
|
||||
if (count == 3'b000000111) begin
|
||||
tx_data_l_shift <= tx_data_l[23:0];
|
||||
tx_data_r_shift <= tx_data_r[23:0];
|
||||
end else if (count[2:0] == 3'b111 && count[7:3] >= 5'd1 && count[7:3] <= 5'd24) begin
|
||||
if (count[8] == 1'b1)
|
||||
tx_data_r_shift <= {tx_data_r_shift[22:0], 1'b0};
|
||||
else
|
||||
tx_data_l_shift <= {tx_data_l_shift[22:0], 1'b0};
|
||||
end
|
||||
|
||||
always@(count, tx_data_l_shift, tx_data_r_shift)
|
||||
if (count[7:3] <= 5'd24 && count[7:3] >= 4'd1)
|
||||
if (count[8] == 1'b1)
|
||||
tx_sdout = tx_data_r_shift[23];
|
||||
else
|
||||
tx_sdout = tx_data_l_shift[23];
|
||||
else
|
||||
tx_sdout = 1'b0;
|
||||
|
||||
/* SYNCHRONIZE DATA IN TO AXIS CLOCK DOMAIN */
|
||||
reg [2:0] din_sync_shift = 3'd0;
|
||||
wire din_sync = din_sync_shift[2];
|
||||
always@(posedge axis_clk)
|
||||
din_sync_shift <= {din_sync_shift[1:0], rx_sdin};
|
||||
|
||||
/* I2S RECEIVE SHIFT REGISTERS */
|
||||
reg [23:0] rx_data_l_shift = 24'b0;
|
||||
reg [23:0] rx_data_r_shift = 24'b0;
|
||||
always@(posedge axis_clk)
|
||||
if (count[2:0] == 3'b011 && count[7:3] <= 5'd24 && count[7:3] >= 5'd1)
|
||||
if (lrck == 1'b1)
|
||||
rx_data_r_shift <= {rx_data_r_shift, din_sync};
|
||||
else
|
||||
rx_data_l_shift <= {rx_data_l_shift, din_sync};
|
||||
|
||||
/* AXIS MASTER CONTROLLER */
|
||||
reg [23:0] rx_data_l = 24'b0;
|
||||
reg [23:0] rx_data_r = 24'b0;
|
||||
always@(posedge axis_clk)
|
||||
if (axis_resetn == 1'b0) begin
|
||||
rx_data_l <= 24'b0;
|
||||
rx_data_r <= 24'b0;
|
||||
end else if (count == EOF_COUNT && rx_axis_m_valid == 1'b0) begin
|
||||
rx_data_l <= {8'b0, rx_data_l_shift};
|
||||
rx_data_r <= {8'b0, rx_data_r_shift};
|
||||
end
|
||||
|
||||
assign rx_axis_m_data = (rx_axis_m_last == 1'b1) ? rx_data_r : rx_data_l;
|
||||
|
||||
always@(posedge axis_clk)
|
||||
if (axis_resetn == 1'b0)
|
||||
rx_axis_m_valid <= 1'b0;
|
||||
else if (count == EOF_COUNT && rx_axis_m_valid == 1'b0)
|
||||
rx_axis_m_valid <= 1'b1;
|
||||
else if (rx_axis_m_valid == 1'b1 && rx_axis_m_ready == 1'b1 && rx_axis_m_last == 1'b1)
|
||||
rx_axis_m_valid <= 1'b0;
|
||||
|
||||
always@(posedge axis_clk)
|
||||
if (axis_resetn == 1'b0)
|
||||
rx_axis_m_last <= 1'b0;
|
||||
else if (count == EOF_COUNT && rx_axis_m_valid == 1'b0)
|
||||
rx_axis_m_last <= 1'b0;
|
||||
else if (rx_axis_m_valid == 1'b1 && rx_axis_m_ready == 1'b1)
|
||||
rx_axis_m_last <= ~rx_axis_m_last;
|
||||
|
||||
|
||||
endmodule
|
||||
175
LAB3/ip/axi4-stream-dual-i2s/hdl/axis_dual_i2s_wrapper.v
Normal file
175
LAB3/ip/axi4-stream-dual-i2s/hdl/axis_dual_i2s_wrapper.v
Normal file
@@ -0,0 +1,175 @@
|
||||
`timescale 1ns / 1ps
|
||||
`default_nettype none
|
||||
|
||||
module axis_i2s_wrapper (
|
||||
input wire i2s_clk, // require: approx 22.591MHz
|
||||
input wire i2s_resetn,
|
||||
|
||||
input wire aclk,
|
||||
input wire aresetn,
|
||||
|
||||
input wire [23:0] s_axis_tdata,
|
||||
input wire s_axis_tvalid,
|
||||
output wire s_axis_tready,
|
||||
input wire s_axis_tlast,
|
||||
|
||||
output wire [23:0] m_axis_tdata,
|
||||
output wire m_axis_tvalid,
|
||||
input wire m_axis_tready,
|
||||
output wire m_axis_tlast,
|
||||
|
||||
output wire tx_mclk,
|
||||
output wire tx_lrck,
|
||||
output wire tx_sclk,
|
||||
output wire tx_sdout,
|
||||
output wire rx_mclk,
|
||||
output wire rx_lrck,
|
||||
output wire rx_sclk,
|
||||
input wire rx_sdin
|
||||
);
|
||||
|
||||
wire [23:0] tx_axis_s_data;
|
||||
wire tx_axis_s_valid;
|
||||
wire tx_axis_s_ready;
|
||||
wire tx_axis_s_last;
|
||||
|
||||
wire [23:0] rx_axis_m_data;
|
||||
wire rx_axis_m_valid;
|
||||
wire rx_axis_m_ready;
|
||||
wire rx_axis_m_last;
|
||||
|
||||
xpm_fifo_axis #(
|
||||
.CDC_SYNC_STAGES(2),
|
||||
.CLOCKING_MODE("independent_clock"),
|
||||
.ECC_MODE("no_ecc"),
|
||||
.FIFO_DEPTH(1024),
|
||||
.FIFO_MEMORY_TYPE("auto"),
|
||||
.PACKET_FIFO("false"),
|
||||
.PROG_EMPTY_THRESH(10),
|
||||
.PROG_FULL_THRESH(10),
|
||||
.RD_DATA_COUNT_WIDTH(1),
|
||||
.RELATED_CLOCKS(0),
|
||||
.SIM_ASSERT_CHK(1),
|
||||
.TDATA_WIDTH(24),
|
||||
.TDEST_WIDTH(1),
|
||||
.TID_WIDTH(1),
|
||||
.TUSER_WIDTH(1),
|
||||
.USE_ADV_FEATURES("0000"),
|
||||
.WR_DATA_COUNT_WIDTH(1)
|
||||
)
|
||||
rx_fifo (
|
||||
.s_aclk(aclk),
|
||||
.s_aresetn(aresetn),
|
||||
.s_axis_tvalid(s_axis_tvalid),
|
||||
.s_axis_tready(s_axis_tready),
|
||||
.s_axis_tdata(s_axis_tdata),
|
||||
.s_axis_tlast(s_axis_tlast),
|
||||
.s_axis_tdest(1'b0),
|
||||
.s_axis_tid(1'b0),
|
||||
.s_axis_tkeep(1'b111),
|
||||
.s_axis_tstrb(1'b111),
|
||||
.s_axis_tuser(1'b0),
|
||||
|
||||
.m_aclk(i2s_clk),
|
||||
.m_axis_tvalid(tx_axis_s_valid),
|
||||
.m_axis_tready(tx_axis_s_ready),
|
||||
.m_axis_tdata(tx_axis_s_data),
|
||||
.m_axis_tlast(tx_axis_s_last),
|
||||
.m_axis_tdest(),
|
||||
.m_axis_tid(),
|
||||
.m_axis_tkeep(),
|
||||
.m_axis_tstrb(),
|
||||
.m_axis_tuser(),
|
||||
|
||||
.almost_empty_axis(),
|
||||
.almost_full_axis(),
|
||||
.dbiterr_axis(),
|
||||
.prog_empty_axis(),
|
||||
.prog_full_axis(),
|
||||
.rd_data_count_axis(),
|
||||
.sbiterr_axis(),
|
||||
.wr_data_count_axis(),
|
||||
.injectdbiterr_axis(1'b0),
|
||||
.injectsbiterr_axis(1'b0)
|
||||
);
|
||||
|
||||
axis_dual_i2s axis_dual_i2s_inst (
|
||||
.axis_clk(i2s_clk),
|
||||
.axis_resetn(i2s_resetn),
|
||||
|
||||
.tx_axis_s_data(tx_axis_s_data),
|
||||
.tx_axis_s_valid(tx_axis_s_valid),
|
||||
.tx_axis_s_ready(tx_axis_s_ready),
|
||||
.tx_axis_s_last(tx_axis_s_last),
|
||||
|
||||
.rx_axis_m_data(rx_axis_m_data),
|
||||
.rx_axis_m_valid(rx_axis_m_valid),
|
||||
.rx_axis_m_ready(rx_axis_m_ready),
|
||||
.rx_axis_m_last(rx_axis_m_last),
|
||||
|
||||
.tx_mclk(tx_mclk),
|
||||
.tx_lrck(tx_lrck),
|
||||
.tx_sclk(tx_sclk),
|
||||
.tx_sdout(tx_sdout),
|
||||
.rx_mclk(rx_mclk),
|
||||
.rx_lrck(rx_lrck),
|
||||
.rx_sclk(rx_sclk),
|
||||
.rx_sdin(rx_sdin)
|
||||
);
|
||||
|
||||
xpm_fifo_axis #(
|
||||
.CDC_SYNC_STAGES(2),
|
||||
.CLOCKING_MODE("independent_clock"),
|
||||
.ECC_MODE("no_ecc"),
|
||||
.FIFO_DEPTH(1024),
|
||||
.FIFO_MEMORY_TYPE("auto"),
|
||||
.PACKET_FIFO("false"),
|
||||
.PROG_EMPTY_THRESH(10),
|
||||
.PROG_FULL_THRESH(10),
|
||||
.RD_DATA_COUNT_WIDTH(1),
|
||||
.RELATED_CLOCKS(0),
|
||||
.SIM_ASSERT_CHK(1),
|
||||
.TDATA_WIDTH(24),
|
||||
.TDEST_WIDTH(1),
|
||||
.TID_WIDTH(1),
|
||||
.TUSER_WIDTH(1),
|
||||
.USE_ADV_FEATURES("0000"),
|
||||
.WR_DATA_COUNT_WIDTH(1)
|
||||
)
|
||||
tx_fifo (
|
||||
.s_aclk(i2s_clk),
|
||||
.s_aresetn(i2s_resetn),
|
||||
.s_axis_tvalid(rx_axis_m_valid),
|
||||
.s_axis_tready(rx_axis_m_ready),
|
||||
.s_axis_tdata(rx_axis_m_data),
|
||||
.s_axis_tlast(rx_axis_m_last),
|
||||
.s_axis_tdest(1'b0),
|
||||
.s_axis_tid(1'b0),
|
||||
.s_axis_tkeep(1'b111),
|
||||
.s_axis_tstrb(1'b111),
|
||||
.s_axis_tuser(1'b0),
|
||||
|
||||
.m_aclk(aclk),
|
||||
.m_axis_tvalid(m_axis_tvalid),
|
||||
.m_axis_tready(m_axis_tready),
|
||||
.m_axis_tdata(m_axis_tdata),
|
||||
.m_axis_tlast(m_axis_tlast),
|
||||
.m_axis_tdest(),
|
||||
.m_axis_tid(),
|
||||
.m_axis_tkeep(),
|
||||
.m_axis_tstrb(),
|
||||
.m_axis_tuser(),
|
||||
|
||||
.almost_empty_axis(),
|
||||
.almost_full_axis(),
|
||||
.dbiterr_axis(),
|
||||
.prog_empty_axis(),
|
||||
.prog_full_axis(),
|
||||
.rd_data_count_axis(),
|
||||
.sbiterr_axis(),
|
||||
.wr_data_count_axis(),
|
||||
.injectdbiterr_axis(1'b0),
|
||||
.injectsbiterr_axis(1'b0)
|
||||
);
|
||||
|
||||
endmodule
|
||||
12
LAB3/ip/axi4-stream-dual-i2s/xgui/axis_dual_i2s_v1_0.tcl
Normal file
12
LAB3/ip/axi4-stream-dual-i2s/xgui/axis_dual_i2s_v1_0.tcl
Normal file
@@ -0,0 +1,12 @@
|
||||
# Definitional proc to organize widgets for parameters.
|
||||
proc init_gui { IPINST } {
|
||||
ipgui::add_param $IPINST -name "Component_Name"
|
||||
#Adding Page
|
||||
set Page_0 [ipgui::add_page $IPINST -name "Page 0"]
|
||||
ipgui::add_static_text $IPINST -name "Warnings" -parent ${Page_0} -text {The jumper on the board MUST BE in position SLV.
|
||||
The input clock axis_clk MUST BE 22.591 MHz.}
|
||||
|
||||
|
||||
}
|
||||
|
||||
|
||||
35
LAB3/ip/axi4-stream-spi-master/README.md
Normal file
35
LAB3/ip/axi4-stream-spi-master/README.md
Normal file
@@ -0,0 +1,35 @@
|
||||
# AXI4-Stream SPI Master
|
||||
|
||||
This module implements an SPI Master.
|
||||
|
||||
This module is based on the "SPI Master Lightweight" module on OpenCores, freely
|
||||
downloadable from [here](https://opencores.org/projects/spi_master_lightweight),
|
||||
with minimal modifications to add AXI4-Stream interfaces and reset signal.
|
||||
|
||||
The cs signal is automatically asserted half clock cycle (SCLK) before the first
|
||||
rising edge of SCLK (with CPOL=0 and CPHA=0) and deasserted half clock cycle
|
||||
(SCLK) after the last falling edge of SCLK (with CPOL=0 and CPHA=0).
|
||||
|
||||
## Generics
|
||||
* c_clkfreq: aclk frequency (in Hz)
|
||||
* c_sclkfreq: desired sclk frequency (in Hz); must be <= c_clkfreq/8
|
||||
* c_cpol: SPI CPOL
|
||||
* c_cpha: SPI CPHA
|
||||
|
||||
## Slave AXI4-Stream
|
||||
|
||||
Data passed to this module through this interface are serialized and send
|
||||
through the MOSI port, MSbit first.
|
||||
|
||||
The CS signal will go low at the beginning of the transfer and will stay low
|
||||
until this module has data to send. In other words, keep s_axis_tvalid high and
|
||||
keep sending data if you want an uninterrupted transfer with CS always low.
|
||||
|
||||
## Master AXI4-Stream
|
||||
|
||||
Data received by this module will be sent through this interface. Note that this
|
||||
interface lacks a tready signal.
|
||||
|
||||
For how the SPI protocol works, data can be received only when data is
|
||||
transmitted by the master so, if you want to receive N bytes, you have to send
|
||||
N bytes (by writing on the Slave AXI4-Stream interface).
|
||||
130
LAB3/ip/axi4-stream-spi-master/cocotb/.gitignore
vendored
Normal file
130
LAB3/ip/axi4-stream-spi-master/cocotb/.gitignore
vendored
Normal file
@@ -0,0 +1,130 @@
|
||||
# Byte-compiled / optimized / DLL files
|
||||
__pycache__/
|
||||
*.py[cod]
|
||||
*$py.class
|
||||
|
||||
# C extensions
|
||||
*.so
|
||||
|
||||
# Distribution / packaging
|
||||
.Python
|
||||
build/
|
||||
develop-eggs/
|
||||
dist/
|
||||
downloads/
|
||||
eggs/
|
||||
.eggs/
|
||||
lib/
|
||||
lib64/
|
||||
parts/
|
||||
sdist/
|
||||
var/
|
||||
wheels/
|
||||
pip-wheel-metadata/
|
||||
share/python-wheels/
|
||||
*.egg-info/
|
||||
.installed.cfg
|
||||
*.egg
|
||||
MANIFEST
|
||||
|
||||
# PyInstaller
|
||||
# Usually these files are written by a python script from a template
|
||||
# before PyInstaller builds the exe, so as to inject date/other infos into it.
|
||||
*.manifest
|
||||
*.spec
|
||||
|
||||
# Installer logs
|
||||
pip-log.txt
|
||||
pip-delete-this-directory.txt
|
||||
|
||||
# Unit test / coverage reports
|
||||
htmlcov/
|
||||
.tox/
|
||||
.nox/
|
||||
.coverage
|
||||
.coverage.*
|
||||
.cache
|
||||
nosetests.xml
|
||||
coverage.xml
|
||||
*.cover
|
||||
.hypothesis/
|
||||
.pytest_cache/
|
||||
|
||||
# Translations
|
||||
*.mo
|
||||
*.pot
|
||||
|
||||
# Django stuff:
|
||||
*.log
|
||||
local_settings.py
|
||||
db.sqlite3
|
||||
db.sqlite3-journal
|
||||
|
||||
# Flask stuff:
|
||||
instance/
|
||||
.webassets-cache
|
||||
|
||||
# Scrapy stuff:
|
||||
.scrapy
|
||||
|
||||
# Sphinx documentation
|
||||
docs/_build/
|
||||
|
||||
# PyBuilder
|
||||
target/
|
||||
|
||||
# Jupyter Notebook
|
||||
.ipynb_checkpoints
|
||||
|
||||
# IPython
|
||||
profile_default/
|
||||
ipython_config.py
|
||||
|
||||
# pyenv
|
||||
.python-version
|
||||
|
||||
# pipenv
|
||||
# According to pypa/pipenv#598, it is recommended to include Pipfile.lock in version control.
|
||||
# However, in case of collaboration, if having platform-specific dependencies or dependencies
|
||||
# having no cross-platform support, pipenv may install dependencies that don't work, or not
|
||||
# install all needed dependencies.
|
||||
#Pipfile.lock
|
||||
|
||||
# celery beat schedule file
|
||||
celerybeat-schedule
|
||||
|
||||
# SageMath parsed files
|
||||
*.sage.py
|
||||
|
||||
# Environments
|
||||
.env
|
||||
.venv
|
||||
env/
|
||||
venv/
|
||||
ENV/
|
||||
env.bak/
|
||||
venv.bak/
|
||||
|
||||
# Spyder project settings
|
||||
.spyderproject
|
||||
.spyproject
|
||||
|
||||
# Rope project settings
|
||||
.ropeproject
|
||||
|
||||
# mkdocs documentation
|
||||
/site
|
||||
|
||||
# mypy
|
||||
.mypy_cache/
|
||||
.dmypy.json
|
||||
dmypy.json
|
||||
|
||||
# Pyre type checker
|
||||
.pyre/
|
||||
|
||||
# Cocotb build folder
|
||||
build/
|
||||
|
||||
# Cocotb results
|
||||
results.xml
|
||||
20
LAB3/ip/axi4-stream-spi-master/cocotb/Makefile
Normal file
20
LAB3/ip/axi4-stream-spi-master/cocotb/Makefile
Normal file
@@ -0,0 +1,20 @@
|
||||
export PYTHON_BIN=python3
|
||||
|
||||
PWD := $(shell pwd)
|
||||
|
||||
SIM ?= ghdl
|
||||
SIM_ARGS ?= --wave=$(PWD)/build/waveform.ghw -gc_clkfreq=100000000 -gc_sclkfreq=10000000
|
||||
GHDL_ARGS ?= -fsynopsys
|
||||
|
||||
TOPLEVEL_LANG = vhdl
|
||||
|
||||
SIM_BUILD = $(PWD)/build
|
||||
MODULE = tester_axis_lw_spi_master
|
||||
TOPLEVEL = axis_lw_spi_master
|
||||
|
||||
HDL_DIR = $(PWD)/../hdl
|
||||
VHDL_SOURCES = \
|
||||
$(HDL_DIR)/spi_master_lightweight/rtl/lw_spi_master.vhd \
|
||||
$(HDL_DIR)/axis_lw_spi_master.vhd
|
||||
|
||||
include $(shell cocotb-config --makefiles)/Makefile.sim
|
||||
@@ -0,0 +1,82 @@
|
||||
#!/usr/bin/env python3
|
||||
|
||||
import secrets
|
||||
|
||||
import cocotb
|
||||
from cocotb.clock import Clock
|
||||
from cocotb.triggers import RisingEdge, ClockCycles
|
||||
from cocotbext.axi4stream.drivers import Axi4StreamMaster
|
||||
from cocotbext.axi4stream.monitors import Axi4Stream
|
||||
from cocotbext.spi import SpiSlaveBase, SpiSignals, SpiConfig
|
||||
|
||||
CLK_PERIOD = 10
|
||||
|
||||
|
||||
class SimpleSpiSlave(SpiSlaveBase):
|
||||
def __init__(self, signals, config, data):
|
||||
self._config = config
|
||||
self.content = 0
|
||||
self.data = data
|
||||
super().__init__(signals)
|
||||
|
||||
async def get_content(self):
|
||||
await self.idle.wait()
|
||||
return self.content
|
||||
|
||||
async def _transaction(self, frame_start, frame_end):
|
||||
await frame_start
|
||||
self.idle.clear()
|
||||
|
||||
self._miso.value = 1 if self.data[0] & 0x80 else 0
|
||||
self.content = int(await self._shift(len(self.data) * 8 - 1, tx_word=int.from_bytes(self.data, 'big')))
|
||||
await RisingEdge(self._sclk)
|
||||
self.content = self.content << 1 | int(self._mosi.value.integer)
|
||||
|
||||
await frame_end
|
||||
|
||||
|
||||
async def setup_dut(dut):
|
||||
cocotb.fork(Clock(dut.aclk, CLK_PERIOD, "ns").start())
|
||||
|
||||
|
||||
@cocotb.test()
|
||||
async def test_spi(dut, length=32):
|
||||
"""TODO"""
|
||||
|
||||
spi_signals = SpiSignals(
|
||||
sclk = dut.sclk,
|
||||
mosi = dut.mosi,
|
||||
miso = dut.miso,
|
||||
cs = dut.cs
|
||||
)
|
||||
|
||||
spi_config = SpiConfig(
|
||||
word_width = 8,
|
||||
cpol = False,
|
||||
cpha = False,
|
||||
data_output_idle = 0,
|
||||
msb_first = True
|
||||
)
|
||||
|
||||
mosi_tx = secrets.randbits(length * 8).to_bytes(length, 'little')
|
||||
miso_tx = secrets.randbits(length * 8).to_bytes(length, 'little')
|
||||
spi_slave = SimpleSpiSlave(spi_signals, spi_config, miso_tx)
|
||||
|
||||
miso_rx = bytearray()
|
||||
|
||||
axis_m = Axi4StreamMaster(dut, "s_axis", dut.aclk)
|
||||
axis_monitor = Axi4Stream(dut, "m_axis", dut.aclk, packets=False)
|
||||
axis_monitor.add_callback(lambda data: miso_rx.extend(data))
|
||||
|
||||
await setup_dut(dut)
|
||||
await ClockCycles(dut.aclk, 10)
|
||||
|
||||
await axis_m.write([b for b in mosi_tx])
|
||||
|
||||
mosi_rx = (await spi_slave.get_content()).to_bytes(length, 'big')
|
||||
|
||||
await ClockCycles(dut.aclk, 10)
|
||||
|
||||
assert mosi_tx == mosi_rx, "Received MOSI data does not match transmitted one"
|
||||
assert miso_tx == miso_rx, "Received MISO data does not match transmitted one"
|
||||
|
||||
53
LAB3/ip/axi4-stream-spi-master/cocotb/waveforms.gtkw
Normal file
53
LAB3/ip/axi4-stream-spi-master/cocotb/waveforms.gtkw
Normal file
@@ -0,0 +1,53 @@
|
||||
[*]
|
||||
[*] GTKWave Analyzer v3.3.104 (w)1999-2020 BSI
|
||||
[*] Fri Mar 25 16:24:27 2022
|
||||
[*]
|
||||
[dumpfile] "/home/nicola/Documents/Vivado/IPs/ip_repo/axi4-stream-spi-master/sim/build/waveform.ghw"
|
||||
[dumpfile_mtime] "Fri Mar 25 16:23:35 2022"
|
||||
[dumpfile_size] 3066
|
||||
[savefile] "/home/nicola/Documents/Vivado/IPs/ip_repo/axi4-stream-spi-master/sim/waveforms.gtkw"
|
||||
[timestart] 0
|
||||
[size] 1920 1001
|
||||
[pos] -27 -24
|
||||
*-27.176317 7190000000 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
|
||||
[treeopen] top.
|
||||
[treeopen] top.axis_lw_spi_master.
|
||||
[treeopen] top.axis_lw_spi_master.inst_lw_spi_master.
|
||||
[sst_width] 281
|
||||
[signals_width] 200
|
||||
[sst_expanded] 1
|
||||
[sst_vpaned_height] 285
|
||||
@28
|
||||
top.axis_lw_spi_master.clk
|
||||
@200
|
||||
-
|
||||
@28
|
||||
top.axis_lw_spi_master.s_axis_tvalid
|
||||
top.axis_lw_spi_master.s_axis_tready
|
||||
@22
|
||||
#{top.axis_lw_spi_master.s_axis_tdata[7:0]} top.axis_lw_spi_master.s_axis_tdata[7] top.axis_lw_spi_master.s_axis_tdata[6] top.axis_lw_spi_master.s_axis_tdata[5] top.axis_lw_spi_master.s_axis_tdata[4] top.axis_lw_spi_master.s_axis_tdata[3] top.axis_lw_spi_master.s_axis_tdata[2] top.axis_lw_spi_master.s_axis_tdata[1] top.axis_lw_spi_master.s_axis_tdata[0]
|
||||
@200
|
||||
-
|
||||
@28
|
||||
top.axis_lw_spi_master.m_axis_tvalid
|
||||
@22
|
||||
#{top.axis_lw_spi_master.m_axis_tdata[7:0]} top.axis_lw_spi_master.m_axis_tdata[7] top.axis_lw_spi_master.m_axis_tdata[6] top.axis_lw_spi_master.m_axis_tdata[5] top.axis_lw_spi_master.m_axis_tdata[4] top.axis_lw_spi_master.m_axis_tdata[3] top.axis_lw_spi_master.m_axis_tdata[2] top.axis_lw_spi_master.m_axis_tdata[1] top.axis_lw_spi_master.m_axis_tdata[0]
|
||||
@200
|
||||
-
|
||||
@28
|
||||
top.axis_lw_spi_master.inst_lw_spi_master.en_i
|
||||
@22
|
||||
#{top.axis_lw_spi_master.inst_lw_spi_master.mosi_data_i[7:0]} top.axis_lw_spi_master.inst_lw_spi_master.mosi_data_i[7] top.axis_lw_spi_master.inst_lw_spi_master.mosi_data_i[6] top.axis_lw_spi_master.inst_lw_spi_master.mosi_data_i[5] top.axis_lw_spi_master.inst_lw_spi_master.mosi_data_i[4] top.axis_lw_spi_master.inst_lw_spi_master.mosi_data_i[3] top.axis_lw_spi_master.inst_lw_spi_master.mosi_data_i[2] top.axis_lw_spi_master.inst_lw_spi_master.mosi_data_i[1] top.axis_lw_spi_master.inst_lw_spi_master.mosi_data_i[0]
|
||||
#{top.axis_lw_spi_master.inst_lw_spi_master.miso_data_o[7:0]} top.axis_lw_spi_master.inst_lw_spi_master.miso_data_o[7] top.axis_lw_spi_master.inst_lw_spi_master.miso_data_o[6] top.axis_lw_spi_master.inst_lw_spi_master.miso_data_o[5] top.axis_lw_spi_master.inst_lw_spi_master.miso_data_o[4] top.axis_lw_spi_master.inst_lw_spi_master.miso_data_o[3] top.axis_lw_spi_master.inst_lw_spi_master.miso_data_o[2] top.axis_lw_spi_master.inst_lw_spi_master.miso_data_o[1] top.axis_lw_spi_master.inst_lw_spi_master.miso_data_o[0]
|
||||
@28
|
||||
top.axis_lw_spi_master.inst_lw_spi_master.data_ready_o
|
||||
@200
|
||||
-
|
||||
@28
|
||||
top.axis_lw_spi_master.sclk
|
||||
top.axis_lw_spi_master.mosi
|
||||
top.axis_lw_spi_master.miso
|
||||
@29
|
||||
top.axis_lw_spi_master.cs
|
||||
[pattern_trace] 1
|
||||
[pattern_trace] 0
|
||||
761
LAB3/ip/axi4-stream-spi-master/component.xml
Normal file
761
LAB3/ip/axi4-stream-spi-master/component.xml
Normal file
@@ -0,0 +1,761 @@
|
||||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<spirit:component xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
|
||||
<spirit:vendor>DigiLAB</spirit:vendor>
|
||||
<spirit:library>ip</spirit:library>
|
||||
<spirit:name>axi4stream_spi_master</spirit:name>
|
||||
<spirit:version>1.0</spirit:version>
|
||||
<spirit:busInterfaces>
|
||||
<spirit:busInterface>
|
||||
<spirit:name>aclk</spirit:name>
|
||||
<spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock" spirit:version="1.0"/>
|
||||
<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock_rtl" spirit:version="1.0"/>
|
||||
<spirit:slave/>
|
||||
<spirit:portMaps>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>CLK</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>aclk</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
</spirit:portMaps>
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>ASSOCIATED_BUSIF</spirit:name>
|
||||
<spirit:value spirit:id="BUSIFPARAM_VALUE.ACLK.ASSOCIATED_BUSIF">S_AXIS:M_AXIS</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>ASSOCIATED_RESET</spirit:name>
|
||||
<spirit:value spirit:id="BUSIFPARAM_VALUE.ACLK.ASSOCIATED_RESET"/>
|
||||
</spirit:parameter>
|
||||
</spirit:parameters>
|
||||
</spirit:busInterface>
|
||||
<spirit:busInterface>
|
||||
<spirit:name>SPI_M</spirit:name>
|
||||
<spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="spi" spirit:version="1.0"/>
|
||||
<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="spi_rtl" spirit:version="1.0"/>
|
||||
<spirit:master/>
|
||||
<spirit:portMaps>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>SCK_T</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>sclk_t</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>IO1_O</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>miso_o</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>SS_T</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>cs_t</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>IO0_O</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>mosi_o</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>SCK_I</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>sclk_i</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>SS_O</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>cs_o</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>IO0_T</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>mosi_t</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>IO1_T</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>miso_t</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>SCK_O</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>sclk_o</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>SS_I</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>cs_i</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>IO1_I</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>miso_i</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>IO0_I</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>mosi_i</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
</spirit:portMaps>
|
||||
</spirit:busInterface>
|
||||
<spirit:busInterface>
|
||||
<spirit:name>S_AXIS</spirit:name>
|
||||
<spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="axis" spirit:version="1.0"/>
|
||||
<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="axis_rtl" spirit:version="1.0"/>
|
||||
<spirit:slave/>
|
||||
<spirit:portMaps>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>TDATA</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>s_axis_tdata</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>TVALID</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
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|
||||
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||||
<spirit:name>c_sclkfreq</spirit:name>
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||||
<spirit:displayName>C Sclkfreq</spirit:displayName>
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|
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||||
<xilinx:tag xilinx:name="ui.data.coregen.dd@38346929_ARCHIVE_LOCATION">/home/nicola/Documents/Vivado/IPs/ip_repo/axi4-stream-spi-master</xilinx:tag>
|
||||
<xilinx:tag xilinx:name="ui.data.coregen.dd@13994ae1_ARCHIVE_LOCATION">/home/nicola/Documents/Vivado/IPs/ip_repo/axi4-stream-spi-master</xilinx:tag>
|
||||
<xilinx:tag xilinx:name="ui.data.coregen.dd@2b5aa9df_ARCHIVE_LOCATION">/home/nicola/Documents/Vivado/IPs/ip_repo/axi4-stream-spi-master</xilinx:tag>
|
||||
<xilinx:tag xilinx:name="ui.data.coregen.dd@254f99cf_ARCHIVE_LOCATION">/home/nicola/Documents/Vivado/IPs/ip_repo/axi4-stream-spi-master</xilinx:tag>
|
||||
<xilinx:tag xilinx:name="ui.data.coregen.dd@5992ce27_ARCHIVE_LOCATION">/home/nicola/Documents/Vivado/IPs/ip_repo/axi4-stream-spi-master</xilinx:tag>
|
||||
<xilinx:tag xilinx:name="ui.data.coregen.dd@1d65a24d_ARCHIVE_LOCATION">/home/nicola/Documents/Vivado/IPs/ip_repo/axi4-stream-spi-master</xilinx:tag>
|
||||
<xilinx:tag xilinx:name="ui.data.coregen.dd@66fe833_ARCHIVE_LOCATION">/home/nicola/Documents/Vivado/IPs/ip_repo/axi4-stream-spi-master</xilinx:tag>
|
||||
<xilinx:tag xilinx:name="ui.data.coregen.dd@4e265a05_ARCHIVE_LOCATION">/home/nicola/Documents/Vivado/IPs/ip_repo/axi4-stream-spi-master</xilinx:tag>
|
||||
<xilinx:tag xilinx:name="ui.data.coregen.dd@7ea38f04_ARCHIVE_LOCATION">/home/nicola/Documents/Vivado/IPs/ip_repo/axi4-stream-spi-master</xilinx:tag>
|
||||
<xilinx:tag xilinx:name="ui.data.coregen.dd@5dea1411_ARCHIVE_LOCATION">/home/nicola/Documents/Vivado/IPs/ip_repo/axi4-stream-spi-master</xilinx:tag>
|
||||
</xilinx:tags>
|
||||
</xilinx:coreExtensions>
|
||||
<xilinx:packagingInfo>
|
||||
<xilinx:xilinxVersion>2020.2</xilinx:xilinxVersion>
|
||||
<xilinx:checksum xilinx:scope="busInterfaces" xilinx:value="e1253621"/>
|
||||
<xilinx:checksum xilinx:scope="fileGroups" xilinx:value="8b40e7f6"/>
|
||||
<xilinx:checksum xilinx:scope="ports" xilinx:value="c4276c6c"/>
|
||||
<xilinx:checksum xilinx:scope="hdlParameters" xilinx:value="f6029529"/>
|
||||
<xilinx:checksum xilinx:scope="parameters" xilinx:value="fa214c74"/>
|
||||
</xilinx:packagingInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:component>
|
||||
104
LAB3/ip/axi4-stream-spi-master/hdl/axis_lw_spi_master.vhd
Normal file
104
LAB3/ip/axi4-stream-spi-master/hdl/axis_lw_spi_master.vhd
Normal file
@@ -0,0 +1,104 @@
|
||||
library IEEE;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
|
||||
entity axis_lw_spi_master is
|
||||
generic (
|
||||
c_clkfreq : integer := 100_000_000;
|
||||
c_sclkfreq : integer := 1_000_000;
|
||||
c_cpol : std_logic := '0';
|
||||
c_cpha : std_logic := '0'
|
||||
);
|
||||
Port (
|
||||
aclk : in STD_LOGIC;
|
||||
aresetn : in STD_LOGIC;
|
||||
|
||||
s_axis_tvalid : in STD_LOGIC;
|
||||
s_axis_tdata : in STD_LOGIC_VECTOR(7 downto 0);
|
||||
s_axis_tready : out STD_LOGIC;
|
||||
|
||||
m_axis_tvalid : out STD_LOGIC;
|
||||
m_axis_tdata : out STD_LOGIC_VECTOR(7 downto 0);
|
||||
|
||||
cs : out STD_LOGIC;
|
||||
sclk : out STD_LOGIC;
|
||||
mosi : out STD_LOGIC;
|
||||
miso : in STD_LOGIC
|
||||
);
|
||||
end axis_lw_spi_master;
|
||||
|
||||
architecture Behavioral of axis_lw_spi_master is
|
||||
|
||||
component lw_spi_master is
|
||||
generic (
|
||||
c_clkfreq : integer := 50_000_000;
|
||||
c_sclkfreq : integer := 5_000_000;
|
||||
c_cpol : std_logic := '0';
|
||||
c_cpha : std_logic := '0'
|
||||
);
|
||||
Port (
|
||||
clk_i : in STD_LOGIC;
|
||||
rst_i : in STD_LOGIC;
|
||||
en_i : in STD_LOGIC;
|
||||
mosi_data_i : in STD_LOGIC_VECTOR (7 downto 0);
|
||||
miso_data_o : out STD_LOGIC_VECTOR (7 downto 0);
|
||||
data_ready_o : out STD_LOGIC;
|
||||
cs_o : out STD_LOGIC;
|
||||
sclk_o : out STD_LOGIC;
|
||||
mosi_o : out STD_LOGIC;
|
||||
miso_i : in STD_LOGIC
|
||||
);
|
||||
end component;
|
||||
|
||||
signal rst : std_logic;
|
||||
signal data_ready : std_logic;
|
||||
signal data_ready_reg : std_logic;
|
||||
signal new_data : std_logic;
|
||||
|
||||
begin
|
||||
|
||||
inst_lw_spi_master : lw_spi_master
|
||||
generic map (
|
||||
c_clkfreq => c_clkfreq,
|
||||
c_sclkfreq => c_sclkfreq,
|
||||
c_cpol => c_cpol,
|
||||
c_cpha => c_cpha
|
||||
)
|
||||
Port map (
|
||||
clk_i => aclk,
|
||||
rst_i => rst,
|
||||
en_i => s_axis_tvalid,
|
||||
mosi_data_i => s_axis_tdata,
|
||||
miso_data_o => m_axis_tdata,
|
||||
data_ready_o => data_ready,
|
||||
cs_o => cs,
|
||||
sclk_o => sclk,
|
||||
mosi_o => mosi,
|
||||
miso_i => miso
|
||||
);
|
||||
|
||||
rst <= not aresetn;
|
||||
s_axis_tready <= new_data;
|
||||
m_axis_tvalid <= new_data;
|
||||
|
||||
process (aclk)
|
||||
begin
|
||||
if rising_edge(aclk) then
|
||||
if aresetn = '0' then
|
||||
|
||||
new_data <= '0';
|
||||
|
||||
else
|
||||
|
||||
data_ready_reg <= data_ready;
|
||||
|
||||
if data_ready_reg = '0' and data_ready = '1' then
|
||||
new_data <= '1';
|
||||
else
|
||||
new_data <= '0';
|
||||
end if;
|
||||
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
end Behavioral;
|
||||
103
LAB3/ip/axi4-stream-spi-master/hdl/ipi_axis_lw_spi_master.vhd
Normal file
103
LAB3/ip/axi4-stream-spi-master/hdl/ipi_axis_lw_spi_master.vhd
Normal file
@@ -0,0 +1,103 @@
|
||||
library IEEE;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
use IEEE.NUMERIC_STD.ALL;
|
||||
|
||||
entity ipi_axis_lw_spi_master is
|
||||
generic (
|
||||
c_clkfreq : integer := 100_000_000;
|
||||
c_sclkfreq : integer := 1_000_000;
|
||||
c_cpol : integer range 0 to 1 := 0;
|
||||
c_cpha : integer range 0 to 1 := 0
|
||||
);
|
||||
Port (
|
||||
aclk : in STD_LOGIC;
|
||||
aresetn : in STD_LOGIC;
|
||||
|
||||
s_axis_tvalid : in STD_LOGIC;
|
||||
s_axis_tdata : in STD_LOGIC_VECTOR(7 downto 0);
|
||||
s_axis_tready : out STD_LOGIC;
|
||||
|
||||
m_axis_tvalid : out STD_LOGIC;
|
||||
m_axis_tdata : out STD_LOGIC_VECTOR(7 downto 0);
|
||||
|
||||
cs_i : in STD_LOGIC;
|
||||
cs_o : out STD_LOGIC;
|
||||
cs_t : out STD_LOGIC;
|
||||
|
||||
sclk_i : in STD_LOGIC;
|
||||
sclk_o : out STD_LOGIC;
|
||||
sclk_t : out STD_LOGIC;
|
||||
|
||||
mosi_i : in STD_LOGIC;
|
||||
mosi_o : out STD_LOGIC;
|
||||
mosi_t : out STD_LOGIC;
|
||||
|
||||
miso_i : in STD_LOGIC;
|
||||
miso_o : out STD_LOGIC;
|
||||
miso_t : out STD_LOGIC
|
||||
);
|
||||
end ipi_axis_lw_spi_master;
|
||||
|
||||
architecture Behavioral of ipi_axis_lw_spi_master is
|
||||
|
||||
component axis_lw_spi_master is
|
||||
generic (
|
||||
c_clkfreq : integer := 100_000_000;
|
||||
c_sclkfreq : integer := 1_000_000;
|
||||
c_cpol : std_logic := '0';
|
||||
c_cpha : std_logic := '0'
|
||||
);
|
||||
Port (
|
||||
aclk : in STD_LOGIC;
|
||||
aresetn : in STD_LOGIC;
|
||||
|
||||
s_axis_tvalid : in STD_LOGIC;
|
||||
s_axis_tdata : in STD_LOGIC_VECTOR(7 downto 0);
|
||||
s_axis_tready : out STD_LOGIC;
|
||||
|
||||
m_axis_tvalid : out STD_LOGIC;
|
||||
m_axis_tdata : out STD_LOGIC_VECTOR(7 downto 0);
|
||||
|
||||
cs : out STD_LOGIC;
|
||||
sclk : out STD_LOGIC;
|
||||
mosi : out STD_LOGIC;
|
||||
miso : in STD_LOGIC
|
||||
);
|
||||
end component;
|
||||
|
||||
constant C_CPOL_SLV : std_logic_vector := std_logic_vector(to_unsigned(c_cpol, 1));
|
||||
constant C_CPHA_SLV : std_logic_vector := std_logic_vector(to_unsigned(c_cpha, 1));
|
||||
|
||||
begin
|
||||
|
||||
inst_axis_lw_spi_master : axis_lw_spi_master
|
||||
generic map (
|
||||
c_clkfreq => c_clkfreq,
|
||||
c_sclkfreq => c_sclkfreq,
|
||||
c_cpol => C_CPOL_SLV(0),
|
||||
c_cpha => C_CPHA_SLV(0)
|
||||
)
|
||||
Port map (
|
||||
aclk => aclk,
|
||||
aresetn => aresetn,
|
||||
|
||||
s_axis_tvalid => s_axis_tvalid,
|
||||
s_axis_tdata => s_axis_tdata,
|
||||
s_axis_tready => s_axis_tready,
|
||||
|
||||
m_axis_tvalid => m_axis_tvalid,
|
||||
m_axis_tdata => m_axis_tdata,
|
||||
|
||||
cs => cs_o,
|
||||
sclk => sclk_o,
|
||||
mosi => mosi_o,
|
||||
miso => miso_i
|
||||
);
|
||||
|
||||
cs_t <= '0';
|
||||
sclk_t <= '0';
|
||||
mosi_t <= '0';
|
||||
miso_t <= '1';
|
||||
miso_o <= '0';
|
||||
|
||||
end Behavioral;
|
||||
@@ -0,0 +1,3 @@
|
||||
# SPI Master Lightweight
|
||||
|
||||
Taken from [OpenCores](https://opencores.org/projects/spi_master_lightweight).
|
||||
Binary file not shown.
@@ -0,0 +1,165 @@
|
||||
GNU LESSER GENERAL PUBLIC LICENSE
|
||||
Version 3, 29 June 2007
|
||||
|
||||
Copyright (C) 2007 Free Software Foundation, Inc. <http://fsf.org/>
|
||||
Everyone is permitted to copy and distribute verbatim copies
|
||||
of this license document, but changing it is not allowed.
|
||||
|
||||
|
||||
This version of the GNU Lesser General Public License incorporates
|
||||
the terms and conditions of version 3 of the GNU General Public
|
||||
License, supplemented by the additional permissions listed below.
|
||||
|
||||
0. Additional Definitions.
|
||||
|
||||
As used herein, "this License" refers to version 3 of the GNU Lesser
|
||||
General Public License, and the "GNU GPL" refers to version 3 of the GNU
|
||||
General Public License.
|
||||
|
||||
"The Library" refers to a covered work governed by this License,
|
||||
other than an Application or a Combined Work as defined below.
|
||||
|
||||
An "Application" is any work that makes use of an interface provided
|
||||
by the Library, but which is not otherwise based on the Library.
|
||||
Defining a subclass of a class defined by the Library is deemed a mode
|
||||
of using an interface provided by the Library.
|
||||
|
||||
A "Combined Work" is a work produced by combining or linking an
|
||||
Application with the Library. The particular version of the Library
|
||||
with which the Combined Work was made is also called the "Linked
|
||||
Version".
|
||||
|
||||
The "Minimal Corresponding Source" for a Combined Work means the
|
||||
Corresponding Source for the Combined Work, excluding any source code
|
||||
for portions of the Combined Work that, considered in isolation, are
|
||||
based on the Application, and not on the Linked Version.
|
||||
|
||||
The "Corresponding Application Code" for a Combined Work means the
|
||||
object code and/or source code for the Application, including any data
|
||||
and utility programs needed for reproducing the Combined Work from the
|
||||
Application, but excluding the System Libraries of the Combined Work.
|
||||
|
||||
1. Exception to Section 3 of the GNU GPL.
|
||||
|
||||
You may convey a covered work under sections 3 and 4 of this License
|
||||
without being bound by section 3 of the GNU GPL.
|
||||
|
||||
2. Conveying Modified Versions.
|
||||
|
||||
If you modify a copy of the Library, and, in your modifications, a
|
||||
facility refers to a function or data to be supplied by an Application
|
||||
that uses the facility (other than as an argument passed when the
|
||||
facility is invoked), then you may convey a copy of the modified
|
||||
version:
|
||||
|
||||
a) under this License, provided that you make a good faith effort to
|
||||
ensure that, in the event an Application does not supply the
|
||||
function or data, the facility still operates, and performs
|
||||
whatever part of its purpose remains meaningful, or
|
||||
|
||||
b) under the GNU GPL, with none of the additional permissions of
|
||||
this License applicable to that copy.
|
||||
|
||||
3. Object Code Incorporating Material from Library Header Files.
|
||||
|
||||
The object code form of an Application may incorporate material from
|
||||
a header file that is part of the Library. You may convey such object
|
||||
code under terms of your choice, provided that, if the incorporated
|
||||
material is not limited to numerical parameters, data structure
|
||||
layouts and accessors, or small macros, inline functions and templates
|
||||
(ten or fewer lines in length), you do both of the following:
|
||||
|
||||
a) Give prominent notice with each copy of the object code that the
|
||||
Library is used in it and that the Library and its use are
|
||||
covered by this License.
|
||||
|
||||
b) Accompany the object code with a copy of the GNU GPL and this license
|
||||
document.
|
||||
|
||||
4. Combined Works.
|
||||
|
||||
You may convey a Combined Work under terms of your choice that,
|
||||
taken together, effectively do not restrict modification of the
|
||||
portions of the Library contained in the Combined Work and reverse
|
||||
engineering for debugging such modifications, if you also do each of
|
||||
the following:
|
||||
|
||||
a) Give prominent notice with each copy of the Combined Work that
|
||||
the Library is used in it and that the Library and its use are
|
||||
covered by this License.
|
||||
|
||||
b) Accompany the Combined Work with a copy of the GNU GPL and this license
|
||||
document.
|
||||
|
||||
c) For a Combined Work that displays copyright notices during
|
||||
execution, include the copyright notice for the Library among
|
||||
these notices, as well as a reference directing the user to the
|
||||
copies of the GNU GPL and this license document.
|
||||
|
||||
d) Do one of the following:
|
||||
|
||||
0) Convey the Minimal Corresponding Source under the terms of this
|
||||
License, and the Corresponding Application Code in a form
|
||||
suitable for, and under terms that permit, the user to
|
||||
recombine or relink the Application with a modified version of
|
||||
the Linked Version to produce a modified Combined Work, in the
|
||||
manner specified by section 6 of the GNU GPL for conveying
|
||||
Corresponding Source.
|
||||
|
||||
1) Use a suitable shared library mechanism for linking with the
|
||||
Library. A suitable mechanism is one that (a) uses at run time
|
||||
a copy of the Library already present on the user's computer
|
||||
system, and (b) will operate properly with a modified version
|
||||
of the Library that is interface-compatible with the Linked
|
||||
Version.
|
||||
|
||||
e) Provide Installation Information, but only if you would otherwise
|
||||
be required to provide such information under section 6 of the
|
||||
GNU GPL, and only to the extent that such information is
|
||||
necessary to install and execute a modified version of the
|
||||
Combined Work produced by recombining or relinking the
|
||||
Application with a modified version of the Linked Version. (If
|
||||
you use option 4d0, the Installation Information must accompany
|
||||
the Minimal Corresponding Source and Corresponding Application
|
||||
Code. If you use option 4d1, you must provide the Installation
|
||||
Information in the manner specified by section 6 of the GNU GPL
|
||||
for conveying Corresponding Source.)
|
||||
|
||||
5. Combined Libraries.
|
||||
|
||||
You may place library facilities that are a work based on the
|
||||
Library side by side in a single library together with other library
|
||||
facilities that are not Applications and are not covered by this
|
||||
License, and convey such a combined library under terms of your
|
||||
choice, if you do both of the following:
|
||||
|
||||
a) Accompany the combined library with a copy of the same work based
|
||||
on the Library, uncombined with any other library facilities,
|
||||
conveyed under the terms of this License.
|
||||
|
||||
b) Give prominent notice with the combined library that part of it
|
||||
is a work based on the Library, and explaining where to find the
|
||||
accompanying uncombined form of the same work.
|
||||
|
||||
6. Revised Versions of the GNU Lesser General Public License.
|
||||
|
||||
The Free Software Foundation may publish revised and/or new versions
|
||||
of the GNU Lesser General Public License from time to time. Such new
|
||||
versions will be similar in spirit to the present version, but may
|
||||
differ in detail to address new problems or concerns.
|
||||
|
||||
Each version is given a distinguishing version number. If the
|
||||
Library as you received it specifies that a certain numbered version
|
||||
of the GNU Lesser General Public License "or any later version"
|
||||
applies to it, you have the option of following the terms and
|
||||
conditions either of that published version or of any later version
|
||||
published by the Free Software Foundation. If the Library as you
|
||||
received it does not specify a version number of the GNU Lesser
|
||||
General Public License, you may choose any version of the GNU Lesser
|
||||
General Public License ever published by the Free Software Foundation.
|
||||
|
||||
If the Library as you received it specifies that a proxy can decide
|
||||
whether future versions of the GNU Lesser General Public License shall
|
||||
apply, that proxy's public statement of acceptance of any version is
|
||||
permanent authorization for you to choose that version for the
|
||||
Library.
|
||||
@@ -0,0 +1,263 @@
|
||||
library IEEE;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
use IEEE.STD_LOGIC_UNSIGNED.ALL;
|
||||
|
||||
entity lw_spi_master is
|
||||
generic (
|
||||
c_clkfreq : integer := 50_000_000;
|
||||
c_sclkfreq : integer := 5_000_000;
|
||||
c_cpol : std_logic := '0';
|
||||
c_cpha : std_logic := '0'
|
||||
);
|
||||
Port (
|
||||
clk_i : in STD_LOGIC;
|
||||
rst_i : in STD_LOGIC;
|
||||
en_i : in STD_LOGIC;
|
||||
mosi_data_i : in STD_LOGIC_VECTOR (7 downto 0);
|
||||
miso_data_o : out STD_LOGIC_VECTOR (7 downto 0);
|
||||
data_ready_o : out STD_LOGIC;
|
||||
cs_o : out STD_LOGIC;
|
||||
sclk_o : out STD_LOGIC;
|
||||
mosi_o : out STD_LOGIC;
|
||||
miso_i : in STD_LOGIC
|
||||
);
|
||||
end lw_spi_master;
|
||||
|
||||
architecture Behavioral of lw_spi_master is
|
||||
|
||||
signal write_reg : std_logic_vector (7 downto 0) := (others => '0');
|
||||
signal read_reg : std_logic_vector (7 downto 0) := (others => '0');
|
||||
|
||||
signal sclk_en : std_logic := '0';
|
||||
signal sclk : std_logic := '0';
|
||||
signal sclk_prev : std_logic := '0';
|
||||
signal sclk_rise : std_logic := '0';
|
||||
signal sclk_fall : std_logic := '0';
|
||||
|
||||
signal pol_phase : std_logic_vector (1 downto 0) := (others => '0');
|
||||
signal mosi_en : std_logic := '0';
|
||||
signal miso_en : std_logic := '0';
|
||||
|
||||
constant c_edgecntrlimdiv2 : integer := c_clkfreq/(c_sclkfreq*2);
|
||||
signal edgecntr : integer range 0 to c_edgecntrlimdiv2 := 0;
|
||||
|
||||
signal cntr : integer range 0 to 15 := 0;
|
||||
|
||||
type states is (S_IDLE, S_TRANSFER);
|
||||
signal state : states := S_IDLE;
|
||||
|
||||
--------------------------------------------------------------------------------
|
||||
--------------------------------------------------------------------------------
|
||||
--------------------------------------------------------------------------------
|
||||
begin
|
||||
|
||||
pol_phase <= c_cpol & c_cpha;
|
||||
|
||||
P_SAMPLE_EN : process (pol_phase, sclk_fall, sclk_rise) begin
|
||||
|
||||
case pol_phase is
|
||||
|
||||
when "00" =>
|
||||
|
||||
mosi_en <= sclk_fall;
|
||||
miso_en <= sclk_rise;
|
||||
|
||||
when "01" =>
|
||||
|
||||
mosi_en <= sclk_rise;
|
||||
miso_en <= sclk_fall;
|
||||
|
||||
when "10" =>
|
||||
|
||||
mosi_en <= sclk_rise;
|
||||
miso_en <= sclk_fall;
|
||||
|
||||
when "11" =>
|
||||
|
||||
mosi_en <= sclk_fall;
|
||||
miso_en <= sclk_rise;
|
||||
|
||||
when others =>
|
||||
|
||||
end case;
|
||||
|
||||
end process;
|
||||
|
||||
P_RISEFALL_DETECT : process (sclk, sclk_prev) begin
|
||||
|
||||
if (sclk = '1' and sclk_prev = '0') then
|
||||
sclk_rise <= '1';
|
||||
else
|
||||
sclk_rise <= '0';
|
||||
end if;
|
||||
|
||||
if (sclk = '0' and sclk_prev = '1') then
|
||||
sclk_fall <= '1';
|
||||
else
|
||||
sclk_fall <= '0';
|
||||
end if;
|
||||
|
||||
end process;
|
||||
|
||||
|
||||
P_MAIN : process (clk_i) begin
|
||||
if (rising_edge(clk_i)) then
|
||||
|
||||
if rst_i = '1' then
|
||||
|
||||
cs_o <= '1';
|
||||
mosi_o <= '0';
|
||||
data_ready_o <= '0';
|
||||
sclk_en <= '0';
|
||||
|
||||
else
|
||||
sclk_prev <= sclk;
|
||||
|
||||
case state is
|
||||
|
||||
when S_IDLE =>
|
||||
|
||||
cs_o <= '1';
|
||||
mosi_o <= '0';
|
||||
data_ready_o <= '0';
|
||||
sclk_en <= '0';
|
||||
cntr <= 0;
|
||||
|
||||
if (c_cpol = '0') then
|
||||
sclk_o <= '0';
|
||||
else
|
||||
sclk_o <= '1';
|
||||
end if;
|
||||
|
||||
if (en_i = '1') then
|
||||
state <= S_TRANSFER;
|
||||
sclk_en <= '1';
|
||||
write_reg <= mosi_data_i;
|
||||
mosi_o <= mosi_data_i(7);
|
||||
read_reg <= x"00";
|
||||
end if;
|
||||
|
||||
when S_TRANSFER =>
|
||||
|
||||
cs_o <= '0';
|
||||
mosi_o <= write_reg(7);
|
||||
|
||||
|
||||
if (c_cpha = '1') then
|
||||
|
||||
if (cntr = 0) then
|
||||
sclk_o <= sclk;
|
||||
if (miso_en = '1') then
|
||||
read_reg(0) <= miso_i;
|
||||
read_reg(7 downto 1) <= read_reg(6 downto 0);
|
||||
cntr <= cntr + 1;
|
||||
end if;
|
||||
elsif (cntr = 8) then
|
||||
data_ready_o <= '1';
|
||||
miso_data_o <= read_reg;
|
||||
if (mosi_en = '1') then
|
||||
data_ready_o <= '0';
|
||||
if (en_i = '1') then
|
||||
write_reg <= mosi_data_i;
|
||||
mosi_o <= mosi_data_i(7);
|
||||
sclk_o <= sclk;
|
||||
cntr <= 0;
|
||||
else
|
||||
state <= S_IDLE;
|
||||
cs_o <= '1';
|
||||
end if;
|
||||
end if;
|
||||
elsif (cntr = 9) then
|
||||
if (miso_en = '1') then
|
||||
state <= S_IDLE;
|
||||
cs_o <= '1';
|
||||
end if;
|
||||
else
|
||||
sclk_o <= sclk;
|
||||
if (miso_en = '1') then
|
||||
read_reg(0) <= miso_i;
|
||||
read_reg(7 downto 1) <= read_reg(6 downto 0);
|
||||
cntr <= cntr + 1;
|
||||
end if;
|
||||
if (mosi_en = '1') then
|
||||
mosi_o <= write_reg(7);
|
||||
write_reg(7 downto 1) <= write_reg(6 downto 0);
|
||||
end if;
|
||||
end if;
|
||||
|
||||
else -- c_cpha = '0'
|
||||
|
||||
if (cntr = 0) then
|
||||
sclk_o <= sclk;
|
||||
if (miso_en = '1') then
|
||||
read_reg(0) <= miso_i;
|
||||
read_reg(7 downto 1) <= read_reg(6 downto 0);
|
||||
cntr <= cntr + 1;
|
||||
end if;
|
||||
elsif (cntr = 8) then
|
||||
|
||||
data_ready_o <= '1';
|
||||
miso_data_o <= read_reg;
|
||||
sclk_o <= sclk;
|
||||
if (mosi_en = '1') then
|
||||
data_ready_o <= '0';
|
||||
if (en_i = '1') then
|
||||
write_reg <= mosi_data_i;
|
||||
mosi_o <= mosi_data_i(7);
|
||||
cntr <= 0;
|
||||
else
|
||||
cntr <= cntr + 1;
|
||||
end if;
|
||||
if (miso_en = '1') then
|
||||
state <= S_IDLE;
|
||||
cs_o <= '1';
|
||||
end if;
|
||||
end if;
|
||||
elsif (cntr = 9) then
|
||||
if (miso_en = '1') then
|
||||
state <= S_IDLE;
|
||||
cs_o <= '1';
|
||||
end if;
|
||||
else
|
||||
sclk_o <= sclk;
|
||||
if (miso_en = '1') then
|
||||
read_reg(0) <= miso_i;
|
||||
read_reg(7 downto 1) <= read_reg(6 downto 0);
|
||||
cntr <= cntr + 1;
|
||||
end if;
|
||||
if (mosi_en = '1') then
|
||||
write_reg(7 downto 1) <= write_reg(6 downto 0);
|
||||
end if;
|
||||
end if;
|
||||
|
||||
end if;
|
||||
|
||||
end case;
|
||||
end if;
|
||||
|
||||
end if;
|
||||
end process;
|
||||
|
||||
P_SCLK_GEN : process (clk_i) begin
|
||||
if (rising_edge(clk_i)) then
|
||||
|
||||
if (sclk_en = '1') then
|
||||
if edgecntr = c_edgecntrlimdiv2-1 then
|
||||
sclk <= not sclk;
|
||||
edgecntr <= 0;
|
||||
else
|
||||
edgecntr <= edgecntr + 1;
|
||||
end if;
|
||||
else
|
||||
edgecntr <= 0;
|
||||
if (c_cpol = '0') then
|
||||
sclk <= '0';
|
||||
else
|
||||
sclk <= '1';
|
||||
end if;
|
||||
end if;
|
||||
|
||||
end if;
|
||||
end process;
|
||||
|
||||
end Behavioral;
|
||||
@@ -0,0 +1,315 @@
|
||||
--------------------------------------------------------------------------------
|
||||
-- AUTHOR: MEHMET BURAK AYKENAR
|
||||
-- CREATED: 09.12.2019
|
||||
-- REVISION DATE: 09.12.2019
|
||||
--
|
||||
--------------------------------------------------------------------------------
|
||||
-- DESCRIPTION:
|
||||
-- This module implements master part of SPI communication interface and can be used to any SPI slave IC.
|
||||
|
||||
-- In order to read from a slave IC, mosi_data_i input signal should be assigned to desired value and en_i signal should be high.
|
||||
-- In order to write to a slave IC, en_i input signal should be high.
|
||||
-- data_ready_o output signal has the logic high value for one clock cycle as read or/and write operation finished. miso_data_o output signal
|
||||
-- has the data read from slave IC.
|
||||
-- In order to read or/and write consecutively, en_i signal should be kept high. To end the transaction, en_i input signal should be assigned to zero
|
||||
-- when data_ready_o output signal gets high.
|
||||
--------------------------------------------------------------------------------
|
||||
-- Limitation/Assumption: In order to use this module properly, the ratio of (c_clkfreq / c_sclkFreq) should be equal to 8 or more.
|
||||
-- For higher SCLK frequencies are possible but more elaboration is needed.
|
||||
-- Notes: c_cpol and c_cpha parameters are clock polarity and clock phase, respectively.
|
||||
--------------------------------------------------------------------------------
|
||||
-- VHDL DIALECT: VHDL '93
|
||||
--
|
||||
--------------------------------------------------------------------------------
|
||||
-- PROJECT : General purpose
|
||||
-- BOARD : General purpose
|
||||
-- ENTITY : spi_master
|
||||
--------------------------------------------------------------------
|
||||
-- FILE : spi_master.vhd
|
||||
--------------------------------------------------------------------------------
|
||||
-- REVISION HISTORY:
|
||||
-- REVISION DATE AUTHOR COMMENT
|
||||
-- -------- ---------- ------------ -----------
|
||||
-- 1.0 19.12.2019 M.B.AYKENAR INITIAL REVISION
|
||||
--------------------------------------------------------------------------------
|
||||
|
||||
library IEEE;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
use IEEE.STD_LOGIC_UNSIGNED.ALL;
|
||||
|
||||
entity spi_master is
|
||||
generic (
|
||||
c_clkfreq : integer := 50_000_000;
|
||||
c_sclkfreq : integer := 1_000_000;
|
||||
c_cpol : std_logic := '0';
|
||||
c_cpha : std_logic := '0'
|
||||
);
|
||||
Port (
|
||||
clk_i : in STD_LOGIC;
|
||||
en_i : in STD_LOGIC;
|
||||
mosi_data_i : in STD_LOGIC_VECTOR (7 downto 0);
|
||||
miso_data_o : out STD_LOGIC_VECTOR (7 downto 0);
|
||||
data_ready_o : out STD_LOGIC;
|
||||
cs_o : out STD_LOGIC;
|
||||
sclk_o : out STD_LOGIC;
|
||||
mosi_o : out STD_LOGIC;
|
||||
miso_i : in STD_LOGIC
|
||||
);
|
||||
end spi_master;
|
||||
|
||||
architecture Behavioral of spi_master is
|
||||
|
||||
--------------------------------------------------------------------------------
|
||||
-- CONSTANTS
|
||||
constant c_edgecntrlimdiv2 : integer := c_clkfreq/(c_sclkfreq*2);
|
||||
|
||||
--------------------------------------------------------------------------------
|
||||
-- INTERNAL SIGNALS
|
||||
signal write_reg : std_logic_vector (7 downto 0) := (others => '0');
|
||||
signal read_reg : std_logic_vector (7 downto 0) := (others => '0');
|
||||
|
||||
signal sclk_en : std_logic := '0';
|
||||
signal sclk : std_logic := '0';
|
||||
signal sclk_prev : std_logic := '0';
|
||||
signal sclk_rise : std_logic := '0';
|
||||
signal sclk_fall : std_logic := '0';
|
||||
|
||||
signal pol_phase : std_logic_vector (1 downto 0) := (others => '0');
|
||||
signal mosi_en : std_logic := '0';
|
||||
signal miso_en : std_logic := '0';
|
||||
signal once : std_logic := '0';
|
||||
|
||||
signal edgecntr : integer range 0 to c_edgecntrlimdiv2 := 0;
|
||||
|
||||
signal cntr : integer range 0 to 15 := 0;
|
||||
|
||||
--------------------------------------------------------------------------------
|
||||
-- STATE DEFINITIONS
|
||||
type states is (S_IDLE, S_TRANSFER);
|
||||
signal state : states := S_IDLE;
|
||||
|
||||
--------------------------------------------------------------------------------
|
||||
--------------------------------------------------------------------------------
|
||||
--------------------------------------------------------------------------------
|
||||
begin
|
||||
|
||||
pol_phase <= c_cpol & c_cpha;
|
||||
|
||||
--------------------------------------------------------------------------------
|
||||
-- SAMPLE_EN process assigns mosi_en and miso_en internal signals to sclk_fall or sclk_rise in a combinational logic according to
|
||||
-- generic parameters of c_cpol and c_cpha via pol_phase signal.
|
||||
P_SAMPLE_EN : process (pol_phase, sclk_fall, sclk_rise) begin
|
||||
|
||||
case pol_phase is
|
||||
|
||||
when "00" =>
|
||||
|
||||
mosi_en <= sclk_fall;
|
||||
miso_en <= sclk_rise;
|
||||
|
||||
when "01" =>
|
||||
|
||||
mosi_en <= sclk_rise;
|
||||
miso_en <= sclk_fall;
|
||||
|
||||
when "10" =>
|
||||
|
||||
mosi_en <= sclk_rise;
|
||||
miso_en <= sclk_fall;
|
||||
|
||||
when "11" =>
|
||||
|
||||
mosi_en <= sclk_fall;
|
||||
miso_en <= sclk_rise;
|
||||
|
||||
when others =>
|
||||
|
||||
end case;
|
||||
|
||||
end process P_SAMPLE_EN;
|
||||
|
||||
--------------------------------------------------------------------------------
|
||||
-- RISEFALL_DETECT process assigns sclk_rise and sclk_fall signals in a combinational logic.
|
||||
P_RISEFALL_DETECT : process (sclk, sclk_prev) begin
|
||||
|
||||
if (sclk = '1' and sclk_prev = '0') then
|
||||
sclk_rise <= '1';
|
||||
else
|
||||
sclk_rise <= '0';
|
||||
end if;
|
||||
|
||||
if (sclk = '0' and sclk_prev = '1') then
|
||||
sclk_fall <= '1';
|
||||
else
|
||||
sclk_fall <= '0';
|
||||
end if;
|
||||
|
||||
end process P_RISEFALL_DETECT;
|
||||
|
||||
--------------------------------------------------------------------------------
|
||||
-- In the MAIN process S_IDLE and S_TRANSFER states are implemented. state changes from S_IDLE to S_TRANSFER when en_i input
|
||||
-- signal has the logic high value. At that cycle, write_reg signal is assigned to mosi_data_i input signal. According to c_cpha generic
|
||||
-- parameter, the transaction operation changes slightly. This operational difference is well explained in the paper that can be found
|
||||
-- in Documents folder of the SPI, which is located in SVN server.
|
||||
P_MAIN : process (clk_i) begin
|
||||
if (rising_edge(clk_i)) then
|
||||
|
||||
data_ready_o <= '0';
|
||||
sclk_prev <= sclk;
|
||||
|
||||
case state is
|
||||
|
||||
--------------------------------------------------------------------------------
|
||||
when S_IDLE =>
|
||||
|
||||
cs_o <= '1';
|
||||
mosi_o <= '0';
|
||||
data_ready_o <= '0';
|
||||
sclk_en <= '0';
|
||||
cntr <= 0;
|
||||
|
||||
if (c_cpol = '0') then
|
||||
sclk_o <= '0';
|
||||
else
|
||||
sclk_o <= '1';
|
||||
end if;
|
||||
|
||||
if (en_i = '1') then
|
||||
state <= S_TRANSFER;
|
||||
sclk_en <= '1';
|
||||
write_reg <= mosi_data_i;
|
||||
mosi_o <= mosi_data_i(7);
|
||||
read_reg <= x"00";
|
||||
end if;
|
||||
|
||||
--------------------------------------------------------------------------------
|
||||
when S_TRANSFER =>
|
||||
|
||||
cs_o <= '0';
|
||||
mosi_o <= write_reg(7);
|
||||
|
||||
|
||||
if (c_cpha = '1') then
|
||||
|
||||
if (cntr = 0) then
|
||||
sclk_o <= sclk;
|
||||
if (miso_en = '1') then
|
||||
read_reg(0) <= miso_i;
|
||||
read_reg(7 downto 1) <= read_reg(6 downto 0);
|
||||
cntr <= cntr + 1;
|
||||
once <= '1';
|
||||
end if;
|
||||
elsif (cntr = 8) then
|
||||
if (once = '1') then
|
||||
data_ready_o <= '1';
|
||||
once <= '0';
|
||||
end if;
|
||||
miso_data_o <= read_reg;
|
||||
if (mosi_en = '1') then
|
||||
if (en_i = '1') then
|
||||
write_reg <= mosi_data_i;
|
||||
mosi_o <= mosi_data_i(7);
|
||||
sclk_o <= sclk;
|
||||
cntr <= 0;
|
||||
else
|
||||
state <= S_IDLE;
|
||||
cs_o <= '1';
|
||||
end if;
|
||||
end if;
|
||||
elsif (cntr = 9) then
|
||||
if (miso_en = '1') then
|
||||
state <= S_IDLE;
|
||||
cs_o <= '1';
|
||||
end if;
|
||||
else
|
||||
sclk_o <= sclk;
|
||||
if (miso_en = '1') then
|
||||
read_reg(0) <= miso_i;
|
||||
read_reg(7 downto 1) <= read_reg(6 downto 0);
|
||||
cntr <= cntr + 1;
|
||||
end if;
|
||||
if (mosi_en = '1') then
|
||||
mosi_o <= write_reg(7);
|
||||
write_reg(7 downto 1) <= write_reg(6 downto 0);
|
||||
end if;
|
||||
end if;
|
||||
|
||||
else -- c_cpha = '0'
|
||||
|
||||
if (cntr = 0) then
|
||||
sclk_o <= sclk;
|
||||
if (miso_en = '1') then
|
||||
read_reg(0) <= miso_i;
|
||||
read_reg(7 downto 1) <= read_reg(6 downto 0);
|
||||
cntr <= cntr + 1;
|
||||
once <= '1';
|
||||
end if;
|
||||
elsif (cntr = 8) then
|
||||
if (once = '1') then
|
||||
data_ready_o <= '1';
|
||||
once <= '0';
|
||||
end if;
|
||||
miso_data_o <= read_reg;
|
||||
sclk_o <= sclk;
|
||||
if (mosi_en = '1') then
|
||||
if (en_i = '1') then
|
||||
write_reg <= mosi_data_i;
|
||||
mosi_o <= mosi_data_i(7);
|
||||
cntr <= 0;
|
||||
else
|
||||
cntr <= cntr + 1;
|
||||
end if;
|
||||
if (miso_en = '1') then
|
||||
state <= S_IDLE;
|
||||
cs_o <= '1';
|
||||
end if;
|
||||
end if;
|
||||
elsif (cntr = 9) then
|
||||
if (miso_en = '1') then
|
||||
state <= S_IDLE;
|
||||
cs_o <= '1';
|
||||
end if;
|
||||
else
|
||||
sclk_o <= sclk;
|
||||
if (miso_en = '1') then
|
||||
read_reg(0) <= miso_i;
|
||||
read_reg(7 downto 1) <= read_reg(6 downto 0);
|
||||
cntr <= cntr + 1;
|
||||
end if;
|
||||
if (mosi_en = '1') then
|
||||
write_reg(7 downto 1) <= write_reg(6 downto 0);
|
||||
end if;
|
||||
end if;
|
||||
|
||||
end if;
|
||||
|
||||
end case;
|
||||
|
||||
end if;
|
||||
end process P_MAIN;
|
||||
|
||||
--------------------------------------------------------------------------------
|
||||
-- In the SCLK_GEN process, internal sclk signal is generated if sclk_en signal is '1'.
|
||||
P_SCLK_GEN : process (clk_i) begin
|
||||
if (rising_edge(clk_i)) then
|
||||
|
||||
if (sclk_en = '1') then
|
||||
if edgecntr = c_edgecntrlimdiv2-1 then
|
||||
sclk <= not sclk;
|
||||
edgecntr <= 0;
|
||||
else
|
||||
edgecntr <= edgecntr + 1;
|
||||
end if;
|
||||
else
|
||||
edgecntr <= 0;
|
||||
if (c_cpol = '0') then
|
||||
sclk <= '0';
|
||||
else
|
||||
sclk <= '1';
|
||||
end if;
|
||||
end if;
|
||||
|
||||
end if;
|
||||
end process P_SCLK_GEN;
|
||||
|
||||
end Behavioral;
|
||||
Binary file not shown.
|
After Width: | Height: | Size: 68 KiB |
Binary file not shown.
|
After Width: | Height: | Size: 186 KiB |
@@ -0,0 +1,233 @@
|
||||
LIBRARY ieee;
|
||||
USE ieee.std_logic_1164.ALL;
|
||||
|
||||
ENTITY tb_lw_spi_master IS
|
||||
END tb_lw_spi_master;
|
||||
|
||||
ARCHITECTURE behavior OF tb_lw_spi_master IS
|
||||
|
||||
-- Component Declaration for the Unit Under Test (UUT)
|
||||
|
||||
COMPONENT lw_spi_master
|
||||
PORT(
|
||||
clk_i : IN std_logic;
|
||||
en_i : IN std_logic;
|
||||
mosi_data_i : IN std_logic_vector(7 downto 0);
|
||||
miso_data_o : OUT std_logic_vector(7 downto 0);
|
||||
data_ready_o : OUT std_logic;
|
||||
cs_o : OUT std_logic;
|
||||
sclk_o : OUT std_logic;
|
||||
mosi_o : OUT std_logic;
|
||||
miso_i : IN std_logic
|
||||
);
|
||||
END COMPONENT;
|
||||
|
||||
|
||||
--Inputs
|
||||
signal clk_i : std_logic := '0';
|
||||
signal en_i : std_logic := '0';
|
||||
signal mosi_data_i : std_logic_vector(7 downto 0) := (others => '0');
|
||||
signal miso_i : std_logic := '0';
|
||||
|
||||
--Outputs
|
||||
signal miso_data_o : std_logic_vector(7 downto 0);
|
||||
signal data_ready_o : std_logic;
|
||||
signal cs_o : std_logic;
|
||||
signal sclk_o : std_logic;
|
||||
signal mosi_o : std_logic;
|
||||
|
||||
-- Clock period definitions
|
||||
-- Clock period definitions
|
||||
constant clk_i_period : time := 20 ns;
|
||||
constant sckPeriod : time := 200 ns;
|
||||
|
||||
signal SPISIGNAL : std_logic_vector(7 downto 0) := (others => '0');
|
||||
signal spiWrite : std_logic := '0';
|
||||
signal spiWriteDone : std_logic := '0';
|
||||
|
||||
BEGIN
|
||||
|
||||
|
||||
|
||||
-- Instantiate the Unit Under Test (UUT)
|
||||
uut: lw_spi_master PORT MAP (
|
||||
clk_i => clk_i,
|
||||
en_i => en_i,
|
||||
mosi_data_i => mosi_data_i,
|
||||
miso_data_o => miso_data_o,
|
||||
data_ready_o => data_ready_o,
|
||||
cs_o => cs_o,
|
||||
sclk_o => sclk_o,
|
||||
mosi_o => mosi_o,
|
||||
miso_i => miso_i
|
||||
);
|
||||
|
||||
-- Clock process definitions
|
||||
clk_i_process :process
|
||||
begin
|
||||
clk_i <= '0';
|
||||
wait for clk_i_period/2;
|
||||
clk_i <= '1';
|
||||
wait for clk_i_period/2;
|
||||
end process;
|
||||
|
||||
SPIWRITE_P : process begin
|
||||
|
||||
wait until rising_edge(spiWrite);
|
||||
|
||||
-- for cpol = 1 cpha = 1
|
||||
-- for cpol = 0 cpha = 0
|
||||
|
||||
miso_i <= SPISIGNAL(7);
|
||||
wait until falling_edge(sclk_o);
|
||||
miso_i <= SPISIGNAL(6);
|
||||
wait until falling_edge(sclk_o);
|
||||
miso_i <= SPISIGNAL(5);
|
||||
wait until falling_edge(sclk_o);
|
||||
miso_i <= SPISIGNAL(4);
|
||||
wait until falling_edge(sclk_o);
|
||||
miso_i <= SPISIGNAL(3);
|
||||
wait until falling_edge(sclk_o);
|
||||
miso_i <= SPISIGNAL(2);
|
||||
wait until falling_edge(sclk_o);
|
||||
miso_i <= SPISIGNAL(1);
|
||||
wait until falling_edge(sclk_o);
|
||||
miso_i <= SPISIGNAL(0);
|
||||
|
||||
-- for cpol = 0 cpha = 1
|
||||
-- for cpol = 1 cpha = 0
|
||||
|
||||
-- miso_i <= SPISIGNAL(7);
|
||||
-- wait until rising_edge(sclk_o);
|
||||
-- miso_i <= SPISIGNAL(6);
|
||||
-- wait until rising_edge(sclk_o);
|
||||
-- miso_i <= SPISIGNAL(5);
|
||||
-- wait until rising_edge(sclk_o);
|
||||
-- miso_i <= SPISIGNAL(4);
|
||||
-- wait until rising_edge(sclk_o);
|
||||
-- miso_i <= SPISIGNAL(3);
|
||||
-- wait until rising_edge(sclk_o);
|
||||
-- miso_i <= SPISIGNAL(2);
|
||||
-- wait until rising_edge(sclk_o);
|
||||
-- miso_i <= SPISIGNAL(1);
|
||||
-- wait until rising_edge(sclk_o);
|
||||
-- miso_i <= SPISIGNAL(0);
|
||||
|
||||
spiWriteDone <= '1';
|
||||
wait for 1 ps;
|
||||
spiWriteDone <= '0';
|
||||
|
||||
end process;
|
||||
|
||||
|
||||
-- Stimulus process
|
||||
stim_proc: process
|
||||
begin
|
||||
-- hold reset state for 100 ns.
|
||||
wait for 100 ns;
|
||||
|
||||
wait for clk_i_period*10;
|
||||
|
||||
-- insert stimulus here
|
||||
|
||||
----------------------------------------------------------------
|
||||
-- -- CPOL,CPHA = 00
|
||||
en_i <= '1';
|
||||
|
||||
-- write 0xA7, read 0xB2
|
||||
mosi_data_i <= x"A7";
|
||||
wait until falling_edge(cs_o);
|
||||
SPISIGNAL <= x"B2";
|
||||
spiWrite <= '1';
|
||||
wait until rising_edge(spiWriteDone);
|
||||
spiWrite <= '0';
|
||||
|
||||
-- write 0xB8, read 0xC3
|
||||
wait until rising_edge(data_ready_o);
|
||||
mosi_data_i <= x"B8";
|
||||
wait until falling_edge(data_ready_o);
|
||||
SPISIGNAL <= x"C3";
|
||||
spiWrite <= '1';
|
||||
wait until rising_edge(spiWriteDone);
|
||||
spiWrite <= '0';
|
||||
en_i <= '0';
|
||||
|
||||
----------------------------------------------------------------
|
||||
-- -- CPOL,CPHA = 10
|
||||
-- en_i <= '1';
|
||||
--
|
||||
-- -- write 0xA7, read 0xB2
|
||||
-- mosi_data_i <= x"A7";
|
||||
-- wait until falling_edge(cs_o);
|
||||
-- wait for 50 ns;
|
||||
-- SPISIGNAL <= x"B2";
|
||||
-- spiWrite <= '1';
|
||||
-- wait until rising_edge(spiWriteDone);
|
||||
-- spiWrite <= '0';
|
||||
--
|
||||
-- -- write 0xB8, read 0xC3
|
||||
-- wait until rising_edge(data_ready_o);
|
||||
-- mosi_data_i <= x"B8";
|
||||
-- wait until falling_edge(data_ready_o);
|
||||
-- SPISIGNAL <= x"C3";
|
||||
-- spiWrite <= '1';
|
||||
-- wait until rising_edge(spiWriteDone);
|
||||
-- spiWrite <= '0';
|
||||
-- en_i <= '0';
|
||||
|
||||
----------------------------------------------------------------
|
||||
-- CPOL,CPHA = 01
|
||||
-- en_i <= '1';
|
||||
--
|
||||
-- -- write 0xA7, read 0xB2
|
||||
-- mosi_data_i <= x"A7";
|
||||
-- wait until falling_edge(cs_o);
|
||||
-- wait until rising_edge(sclk_o);
|
||||
-- SPISIGNAL <= x"B2";
|
||||
-- spiWrite <= '1';
|
||||
-- wait until rising_edge(spiWriteDone);
|
||||
-- spiWrite <= '0';
|
||||
--
|
||||
-- -- write 0xB8, read 0xC3
|
||||
-- wait until rising_edge(data_ready_o);
|
||||
-- mosi_data_i <= x"B8";
|
||||
-- wait until rising_edge(sclk_o);
|
||||
-- SPISIGNAL <= x"C3";
|
||||
-- spiWrite <= '1';
|
||||
-- wait until rising_edge(spiWriteDone);
|
||||
-- spiWrite <= '0';
|
||||
-- en_i <= '0';
|
||||
|
||||
----------------------------------------------------------------
|
||||
-- -- CPOL,CPHA = 11
|
||||
-- en_i <= '1';
|
||||
--
|
||||
-- -- write 0xA7, read 0xB2
|
||||
-- mosi_data_i <= x"A7";
|
||||
-- wait until falling_edge(cs_o);
|
||||
-- wait until falling_edge(sclk_o);
|
||||
-- SPISIGNAL <= x"B2";
|
||||
-- spiWrite <= '1';
|
||||
-- wait until rising_edge(spiWriteDone);
|
||||
-- spiWrite <= '0';
|
||||
--
|
||||
-- -- write 0xB8, read 0xC3
|
||||
-- wait until rising_edge(data_ready_o);
|
||||
-- mosi_data_i <= x"B8";
|
||||
-- wait until falling_edge(sclk_o);
|
||||
-- SPISIGNAL <= x"C3";
|
||||
-- spiWrite <= '1';
|
||||
-- wait until rising_edge(spiWriteDone);
|
||||
-- spiWrite <= '0';
|
||||
-- en_i <= '0';
|
||||
|
||||
|
||||
|
||||
wait for 1 us;
|
||||
|
||||
assert false
|
||||
report "SIM DONE"
|
||||
severity failure;
|
||||
end process;
|
||||
|
||||
END;
|
||||
@@ -0,0 +1,74 @@
|
||||
# Definitional proc to organize widgets for parameters.
|
||||
proc init_gui { IPINST } {
|
||||
ipgui::add_param $IPINST -name "Component_Name"
|
||||
#Adding Page
|
||||
set Page_0 [ipgui::add_page $IPINST -name "Page 0"]
|
||||
ipgui::add_param $IPINST -name "c_clkfreq" -parent ${Page_0}
|
||||
#Adding Group
|
||||
set SPI_parameters [ipgui::add_group $IPINST -name "SPI parameters" -parent ${Page_0}]
|
||||
set c_sclkfreq [ipgui::add_param $IPINST -name "c_sclkfreq" -parent ${SPI_parameters}]
|
||||
set_property tooltip {Desired SCLK frequency (must be less or equal than aclk_freq/8)} ${c_sclkfreq}
|
||||
ipgui::add_param $IPINST -name "c_cpol" -parent ${SPI_parameters}
|
||||
ipgui::add_param $IPINST -name "c_cpha" -parent ${SPI_parameters}
|
||||
|
||||
|
||||
|
||||
}
|
||||
|
||||
proc update_PARAM_VALUE.c_clkfreq { PARAM_VALUE.c_clkfreq } {
|
||||
# Procedure called to update c_clkfreq when any of the dependent parameters in the arguments change
|
||||
}
|
||||
|
||||
proc validate_PARAM_VALUE.c_clkfreq { PARAM_VALUE.c_clkfreq } {
|
||||
# Procedure called to validate c_clkfreq
|
||||
return true
|
||||
}
|
||||
|
||||
proc update_PARAM_VALUE.c_cpha { PARAM_VALUE.c_cpha } {
|
||||
# Procedure called to update c_cpha when any of the dependent parameters in the arguments change
|
||||
}
|
||||
|
||||
proc validate_PARAM_VALUE.c_cpha { PARAM_VALUE.c_cpha } {
|
||||
# Procedure called to validate c_cpha
|
||||
return true
|
||||
}
|
||||
|
||||
proc update_PARAM_VALUE.c_cpol { PARAM_VALUE.c_cpol } {
|
||||
# Procedure called to update c_cpol when any of the dependent parameters in the arguments change
|
||||
}
|
||||
|
||||
proc validate_PARAM_VALUE.c_cpol { PARAM_VALUE.c_cpol } {
|
||||
# Procedure called to validate c_cpol
|
||||
return true
|
||||
}
|
||||
|
||||
proc update_PARAM_VALUE.c_sclkfreq { PARAM_VALUE.c_sclkfreq } {
|
||||
# Procedure called to update c_sclkfreq when any of the dependent parameters in the arguments change
|
||||
}
|
||||
|
||||
proc validate_PARAM_VALUE.c_sclkfreq { PARAM_VALUE.c_sclkfreq } {
|
||||
# Procedure called to validate c_sclkfreq
|
||||
return true
|
||||
}
|
||||
|
||||
|
||||
proc update_MODELPARAM_VALUE.c_clkfreq { MODELPARAM_VALUE.c_clkfreq PARAM_VALUE.c_clkfreq } {
|
||||
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
|
||||
set_property value [get_property value ${PARAM_VALUE.c_clkfreq}] ${MODELPARAM_VALUE.c_clkfreq}
|
||||
}
|
||||
|
||||
proc update_MODELPARAM_VALUE.c_sclkfreq { MODELPARAM_VALUE.c_sclkfreq PARAM_VALUE.c_sclkfreq } {
|
||||
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
|
||||
set_property value [get_property value ${PARAM_VALUE.c_sclkfreq}] ${MODELPARAM_VALUE.c_sclkfreq}
|
||||
}
|
||||
|
||||
proc update_MODELPARAM_VALUE.c_cpol { MODELPARAM_VALUE.c_cpol PARAM_VALUE.c_cpol } {
|
||||
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
|
||||
set_property value [get_property value ${PARAM_VALUE.c_cpol}] ${MODELPARAM_VALUE.c_cpol}
|
||||
}
|
||||
|
||||
proc update_MODELPARAM_VALUE.c_cpha { MODELPARAM_VALUE.c_cpha PARAM_VALUE.c_cpha } {
|
||||
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
|
||||
set_property value [get_property value ${PARAM_VALUE.c_cpha}] ${MODELPARAM_VALUE.c_cpha}
|
||||
}
|
||||
|
||||
3
LAB3/sim/ReadMe.md
Normal file
3
LAB3/sim/ReadMe.md
Normal file
@@ -0,0 +1,3 @@
|
||||
# Placeholder
|
||||
|
||||
This is a placeholder.
|
||||
313
LAB3/vivado/lab3/lab3.xpr
Normal file
313
LAB3/vivado/lab3/lab3.xpr
Normal file
@@ -0,0 +1,313 @@
|
||||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<!-- Product Version: Vivado v2020.2 (64-bit) -->
|
||||
<!-- -->
|
||||
<!-- Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. -->
|
||||
|
||||
<Project Version="7" Minor="54" Path="C:/DESD/LAB3/vivado/lab3/lab3.xpr">
|
||||
<DefaultLaunch Dir="$PRUNDIR"/>
|
||||
<Configuration>
|
||||
<Option Name="Id" Val="45a33585426e4c4e913883d4be838656"/>
|
||||
<Option Name="Part" Val="xc7a35tcpg236-1"/>
|
||||
<Option Name="CompiledLibDir" Val="$PCACHEDIR/compile_simlib"/>
|
||||
<Option Name="CompiledLibDirXSim" Val=""/>
|
||||
<Option Name="CompiledLibDirModelSim" Val="$PCACHEDIR/compile_simlib/modelsim"/>
|
||||
<Option Name="CompiledLibDirQuesta" Val="$PCACHEDIR/compile_simlib/questa"/>
|
||||
<Option Name="CompiledLibDirIES" Val="$PCACHEDIR/compile_simlib/ies"/>
|
||||
<Option Name="CompiledLibDirXcelium" Val="$PCACHEDIR/compile_simlib/xcelium"/>
|
||||
<Option Name="CompiledLibDirVCS" Val="$PCACHEDIR/compile_simlib/vcs"/>
|
||||
<Option Name="CompiledLibDirRiviera" Val="$PCACHEDIR/compile_simlib/riviera"/>
|
||||
<Option Name="CompiledLibDirActivehdl" Val="$PCACHEDIR/compile_simlib/activehdl"/>
|
||||
<Option Name="SimulatorInstallDirModelSim" Val=""/>
|
||||
<Option Name="SimulatorInstallDirQuesta" Val=""/>
|
||||
<Option Name="SimulatorInstallDirIES" Val=""/>
|
||||
<Option Name="SimulatorInstallDirXcelium" Val=""/>
|
||||
<Option Name="SimulatorInstallDirVCS" Val=""/>
|
||||
<Option Name="SimulatorInstallDirRiviera" Val=""/>
|
||||
<Option Name="SimulatorInstallDirActiveHdl" Val=""/>
|
||||
<Option Name="SimulatorGccInstallDirModelSim" Val=""/>
|
||||
<Option Name="SimulatorGccInstallDirQuesta" Val=""/>
|
||||
<Option Name="SimulatorGccInstallDirIES" Val=""/>
|
||||
<Option Name="SimulatorGccInstallDirXcelium" Val=""/>
|
||||
<Option Name="SimulatorGccInstallDirVCS" Val=""/>
|
||||
<Option Name="SimulatorGccInstallDirRiviera" Val=""/>
|
||||
<Option Name="SimulatorGccInstallDirActiveHdl" Val=""/>
|
||||
<Option Name="TargetLanguage" Val="VHDL"/>
|
||||
<Option Name="BoardPart" Val="digilentinc.com:basys3:part0:1.1"/>
|
||||
<Option Name="BoardPartRepoPaths" Val="$PPRDIR/../../../../Users/david/AppData/Roaming/Xilinx/Vivado/2020.2/xhub/board_store/xilinx_board_store"/>
|
||||
<Option Name="ActiveSimSet" Val="sim_1"/>
|
||||
<Option Name="DefaultLib" Val="xil_defaultlib"/>
|
||||
<Option Name="ProjectType" Val="Default"/>
|
||||
<Option Name="IPRepoPath" Val="$PPRDIR/../../ip"/>
|
||||
<Option Name="IPOutputRepo" Val="$PCACHEDIR/ip"/>
|
||||
<Option Name="IPDefaultOutputPath" Val="$PGENDIR/sources_1"/>
|
||||
<Option Name="IPCachePermission" Val="read"/>
|
||||
<Option Name="IPCachePermission" Val="write"/>
|
||||
<Option Name="EnableCoreContainer" Val="FALSE"/>
|
||||
<Option Name="CreateRefXciForCoreContainers" Val="FALSE"/>
|
||||
<Option Name="IPUserFilesDir" Val="$PIPUSERFILESDIR"/>
|
||||
<Option Name="IPStaticSourceDir" Val="$PIPUSERFILESDIR/ipstatic"/>
|
||||
<Option Name="EnableBDX" Val="FALSE"/>
|
||||
<Option Name="DSABoardId" Val="basys3"/>
|
||||
<Option Name="WTXSimLaunchSim" Val="0"/>
|
||||
<Option Name="WTModelSimLaunchSim" Val="0"/>
|
||||
<Option Name="WTQuestaLaunchSim" Val="0"/>
|
||||
<Option Name="WTIesLaunchSim" Val="0"/>
|
||||
<Option Name="WTVcsLaunchSim" Val="0"/>
|
||||
<Option Name="WTRivieraLaunchSim" Val="0"/>
|
||||
<Option Name="WTActivehdlLaunchSim" Val="0"/>
|
||||
<Option Name="WTXSimExportSim" Val="2"/>
|
||||
<Option Name="WTModelSimExportSim" Val="2"/>
|
||||
<Option Name="WTQuestaExportSim" Val="2"/>
|
||||
<Option Name="WTIesExportSim" Val="2"/>
|
||||
<Option Name="WTVcsExportSim" Val="2"/>
|
||||
<Option Name="WTRivieraExportSim" Val="2"/>
|
||||
<Option Name="WTActivehdlExportSim" Val="2"/>
|
||||
<Option Name="GenerateIPUpgradeLog" Val="TRUE"/>
|
||||
<Option Name="XSimRadix" Val="hex"/>
|
||||
<Option Name="XSimTimeUnit" Val="ns"/>
|
||||
<Option Name="XSimArrayDisplayLimit" Val="1024"/>
|
||||
<Option Name="XSimTraceLimit" Val="65536"/>
|
||||
<Option Name="SimTypes" Val="rtl"/>
|
||||
<Option Name="SimTypes" Val="bfm"/>
|
||||
<Option Name="SimTypes" Val="tlm"/>
|
||||
<Option Name="SimTypes" Val="tlm_dpi"/>
|
||||
<Option Name="MEMEnableMemoryMapGeneration" Val="TRUE"/>
|
||||
<Option Name="DcpsUptoDate" Val="TRUE"/>
|
||||
</Configuration>
|
||||
<FileSets Version="1" Minor="31">
|
||||
<FileSet Name="sources_1" Type="DesignSrcs" RelSrcDir="$PSRCDIR/sources_1" RelGenDir="$PGENDIR/sources_1">
|
||||
<Filter Type="Srcs"/>
|
||||
<File Path="$PPRDIR/../../src/digilent_jstk2.vhd">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PPRDIR/../../src/edge_detector_toggle.vhd">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PPRDIR/../../src/debouncer.vhd">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PPRDIR/../../src/moving_average_filter_en.vhd">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PPRDIR/../../src/volume_controller.vhd">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PPRDIR/../../src/LFO.vhd">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PPRDIR/../../src/balance_controller.vhd">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PPRDIR/../../src/effect_selector.vhd">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PPRDIR/../../src/led_controller.vhd">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PPRDIR/../../src/led_level_controller.vhd">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PPRDIR/../../src/mute_controller.vhd">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PPRDIR/../../design/lab_3/lab_3.bd">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PPRDIR/../../../../lab3.gen/sources_1/bd/lab_3/hdl/lab_3_wrapper.vhd">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PPRDIR/../../src/all_pass_filter.vhd">
|
||||
<FileInfo>
|
||||
<Attr Name="AutoDisabled" Val="1"/>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PPRDIR/../../src/jstk_uart_bridge.vhd">
|
||||
<FileInfo>
|
||||
<Attr Name="AutoDisabled" Val="1"/>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PPRDIR/../../src/moving_average_filter.vhd">
|
||||
<FileInfo>
|
||||
<Attr Name="AutoDisabled" Val="1"/>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PPRDIR/../../src/volume_multiplier.vhd">
|
||||
<FileInfo>
|
||||
<Attr Name="AutoDisabled" Val="1"/>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PPRDIR/../../src/volume_saturator.vhd">
|
||||
<FileInfo>
|
||||
<Attr Name="AutoDisabled" Val="1"/>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<Config>
|
||||
<Option Name="DesignMode" Val="RTL"/>
|
||||
<Option Name="TopModule" Val="lab_3_wrapper"/>
|
||||
</Config>
|
||||
</FileSet>
|
||||
<FileSet Name="constrs_1" Type="Constrs" RelSrcDir="$PSRCDIR/constrs_1" RelGenDir="$PGENDIR/constrs_1">
|
||||
<Filter Type="Constrs"/>
|
||||
<File Path="$PPRDIR/../../cons/io.xdc">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<Config>
|
||||
<Option Name="ConstrsType" Val="XDC"/>
|
||||
</Config>
|
||||
</FileSet>
|
||||
<FileSet Name="sim_1" Type="SimulationSrcs" RelSrcDir="$PSRCDIR/sim_1" RelGenDir="$PGENDIR/sim_1">
|
||||
<Filter Type="Srcs"/>
|
||||
<Config>
|
||||
<Option Name="DesignMode" Val="RTL"/>
|
||||
<Option Name="TopModule" Val="lab_3_wrapper"/>
|
||||
<Option Name="TopLib" Val="xil_defaultlib"/>
|
||||
<Option Name="TopAutoSet" Val="TRUE"/>
|
||||
<Option Name="TransportPathDelay" Val="0"/>
|
||||
<Option Name="TransportIntDelay" Val="0"/>
|
||||
<Option Name="SelectedSimModel" Val="rtl"/>
|
||||
<Option Name="PamDesignTestbench" Val=""/>
|
||||
<Option Name="PamDutBypassFile" Val="xil_dut_bypass"/>
|
||||
<Option Name="PamSignalDriverFile" Val="xil_bypass_driver"/>
|
||||
<Option Name="PamPseudoTop" Val="pseudo_tb"/>
|
||||
<Option Name="SrcSet" Val="sources_1"/>
|
||||
</Config>
|
||||
</FileSet>
|
||||
<FileSet Name="utils_1" Type="Utils" RelSrcDir="$PSRCDIR/utils_1" RelGenDir="$PGENDIR/utils_1">
|
||||
<Filter Type="Utils"/>
|
||||
<Config>
|
||||
<Option Name="TopAutoSet" Val="TRUE"/>
|
||||
</Config>
|
||||
</FileSet>
|
||||
</FileSets>
|
||||
<Simulators>
|
||||
<Simulator Name="XSim">
|
||||
<Option Name="Description" Val="Vivado Simulator"/>
|
||||
<Option Name="CompiledLib" Val="0"/>
|
||||
</Simulator>
|
||||
<Simulator Name="ModelSim">
|
||||
<Option Name="Description" Val="ModelSim Simulator"/>
|
||||
</Simulator>
|
||||
<Simulator Name="Questa">
|
||||
<Option Name="Description" Val="Questa Advanced Simulator"/>
|
||||
</Simulator>
|
||||
<Simulator Name="Riviera">
|
||||
<Option Name="Description" Val="Riviera-PRO Simulator"/>
|
||||
</Simulator>
|
||||
<Simulator Name="ActiveHDL">
|
||||
<Option Name="Description" Val="Active-HDL Simulator"/>
|
||||
</Simulator>
|
||||
</Simulators>
|
||||
<Runs Version="1" Minor="15">
|
||||
<Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7a35tcpg236-1" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" IncludeInArchive="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/synth_1">
|
||||
<Strategy Version="1" Minor="2">
|
||||
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2020"/>
|
||||
<Step Id="synth_design"/>
|
||||
</Strategy>
|
||||
<ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2020"/>
|
||||
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
|
||||
<RQSFiles/>
|
||||
</Run>
|
||||
<Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7a35tcpg236-1" ConstrsSet="constrs_1" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" SynthRun="synth_1" IncludeInArchive="true" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/impl_1">
|
||||
<Strategy Version="1" Minor="2">
|
||||
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2020"/>
|
||||
<Step Id="init_design"/>
|
||||
<Step Id="opt_design"/>
|
||||
<Step Id="power_opt_design"/>
|
||||
<Step Id="place_design"/>
|
||||
<Step Id="post_place_power_opt_design"/>
|
||||
<Step Id="phys_opt_design"/>
|
||||
<Step Id="route_design"/>
|
||||
<Step Id="post_route_phys_opt_design"/>
|
||||
<Step Id="write_bitstream"/>
|
||||
</Strategy>
|
||||
<ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2020"/>
|
||||
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
|
||||
<RQSFiles/>
|
||||
</Run>
|
||||
</Runs>
|
||||
<Board>
|
||||
<Jumpers/>
|
||||
</Board>
|
||||
<DashboardSummary Version="1" Minor="0">
|
||||
<Dashboards>
|
||||
<Dashboard Name="default_dashboard">
|
||||
<Gadgets>
|
||||
<Gadget Name="drc_1" Type="drc" Version="1" Row="2" Column="0">
|
||||
<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_drc_0 "/>
|
||||
</Gadget>
|
||||
<Gadget Name="methodology_1" Type="methodology" Version="1" Row="2" Column="1">
|
||||
<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_methodology_0 "/>
|
||||
</Gadget>
|
||||
<Gadget Name="power_1" Type="power" Version="1" Row="1" Column="0">
|
||||
<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_power_0 "/>
|
||||
</Gadget>
|
||||
<Gadget Name="timing_1" Type="timing" Version="1" Row="0" Column="1">
|
||||
<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_timing_summary_0 "/>
|
||||
</Gadget>
|
||||
<Gadget Name="utilization_1" Type="utilization" Version="1" Row="0" Column="0">
|
||||
<GadgetParam Name="REPORTS" Type="string_list" Value="synth_1#synth_1_synth_report_utilization_0 "/>
|
||||
<GadgetParam Name="RUN.STEP" Type="string" Value="synth_design"/>
|
||||
<GadgetParam Name="RUN.TYPE" Type="string" Value="synthesis"/>
|
||||
</Gadget>
|
||||
<Gadget Name="utilization_2" Type="utilization" Version="1" Row="1" Column="1">
|
||||
<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_place_report_utilization_0 "/>
|
||||
</Gadget>
|
||||
</Gadgets>
|
||||
</Dashboard>
|
||||
<CurrentDashboard>default_dashboard</CurrentDashboard>
|
||||
</Dashboards>
|
||||
</DashboardSummary>
|
||||
</Project>
|
||||
@@ -15,10 +15,10 @@ lab2_lib.files = [
|
||||
"LAB2/sim/**/*.vhd"
|
||||
]
|
||||
|
||||
# lab3_lib.files = [
|
||||
# "LAB3/src/**/*.vhd",
|
||||
# "LAB3/sim/**/*.vhd"
|
||||
# ]
|
||||
lab3_lib.files = [
|
||||
"LAB3/src/**/*.vhd",
|
||||
"LAB3/sim/**/*.vhd"
|
||||
]
|
||||
|
||||
xpm.files = [
|
||||
"C:/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_VCOMP.vhd"
|
||||
|
||||
Reference in New Issue
Block a user