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Refactor depacketizer: enhance state machine logic, improve signal handling, and streamline data processing for better functionality

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This commit is contained in:
Davide Cavagnola
2025-04-24 13:07:26 +02:00
parent 75fb66e531
commit a5b23940de
2 changed files with 42 additions and 48 deletions
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2
LAB2/sim/tb_depacketizer.vhd
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@@ -73,7 +73,7 @@ ARCHITECTURE Behavioral OF tb_depacketizer IS
4 => x"54", 4 => x"54",
5 => x"65", 5 => x"65",
6 => x"73", 6 => x"73",
7 => x"90" 7 => x"50"
); );
SIGNAL tready_block_req : STD_LOGIC := '0'; SIGNAL tready_block_req : STD_LOGIC := '0';

80
LAB2/src/depacketizer.vhd
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@@ -26,84 +26,78 @@ END ENTITY depacketizer;
ARCHITECTURE rtl OF depacketizer IS ARCHITECTURE rtl OF depacketizer IS
TYPE state_type IS (WAITING_HEADER, RECEIVING); TYPE state_type IS (WAITING_HEADER, RECEIVING, SEND);
SIGNAL state : state_type := WAITING_HEADER; SIGNAL state : state_type := WAITING_HEADER;
SIGNAL data_buffer : STD_LOGIC_VECTOR(7 DOWNTO 0); SIGNAL s_axis_tready_int : STD_LOGIC := '1';
SIGNAL m_axis_tvalid_int : STD_LOGIC := '0';
SIGNAL m_axis_tdata_int : STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');
SIGNAL m_axis_tlast_int : STD_LOGIC := '0';
SIGNAL s_axis_tready_int : STD_LOGIC; SIGNAL data_buffer : STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');
SIGNAL m_axis_tvalid_int : STD_LOGIC; SIGNAL data_ready : STD_LOGIC := '0';
SIGNAL trigger : STD_LOGIC := '0';
BEGIN BEGIN
s_axis_tready <= s_axis_tready_int; s_axis_tready <= s_axis_tready_int;
m_axis_tvalid <= m_axis_tvalid_int; m_axis_tvalid <= m_axis_tvalid_int;
m_axis_tdata <= m_axis_tdata_int;
m_axis_tlast <= m_axis_tlast_int;
PROCESS (clk) PROCESS (clk)
BEGIN BEGIN
IF rising_edge(clk) THEN IF rising_edge(clk) THEN
IF aresetn = '0' THEN IF aresetn = '0' THEN
state <= WAITING_HEADER; state <= WAITING_HEADER;
m_axis_tdata_int <= (OTHERS => '0');
m_axis_tlast_int <= '0';
s_axis_tready_int <= '1';
m_axis_tvalid_int <= '0';
data_buffer <= (OTHERS => '0'); data_buffer <= (OTHERS => '0');
data_ready <= '0';
m_axis_tdata <= (OTHERS => '0');
m_axis_tlast <= '0';
s_axis_tready_int <= '0';
m_axis_tvalid_int <= '0';
ELSE ELSE
m_axis_tlast_int <= '0';
-- Default values
m_axis_tlast <= '0';
-- Input data - slave
s_axis_tready_int <= m_axis_tready;
IF s_axis_tvalid = '1' AND s_axis_tready_int = '1' THEN
data_buffer <= s_axis_tdata;
END IF;
-- Output data - master
IF m_axis_tready = '1' THEN
m_axis_tvalid_int <= '0';
END IF;
IF trigger = '1' AND (m_axis_tvalid_int = '0' OR m_axis_tready = '1') THEN
m_axis_tvalid_int <= '1';
m_axis_tdata <= data_buffer;
trigger <= '0';
END IF;
-- State machine for depacketization
CASE state IS CASE state IS
WHEN WAITING_HEADER => WHEN WAITING_HEADER =>
s_axis_tready_int <= '1';
m_axis_tvalid_int <= '0';
data_ready <= '0';
IF s_axis_tvalid = '1' AND s_axis_tready_int = '1' THEN IF s_axis_tvalid = '1' AND s_axis_tready_int = '1' THEN
IF data_buffer = STD_LOGIC_VECTOR(to_unsigned(HEADER, 8)) THEN IF s_axis_tdata = STD_LOGIC_VECTOR(to_unsigned(HEADER, 8)) THEN
trigger <= '1';
state <= RECEIVING; state <= RECEIVING;
END IF; END IF;
END IF; END IF;
WHEN RECEIVING => WHEN RECEIVING =>
IF s_axis_tvalid = '1' AND s_axis_tready_int = '1' THEN IF s_axis_tvalid = '1' AND s_axis_tready_int = '1' THEN
IF data_ready = '1' THEN
m_axis_tdata_int <= data_buffer;
m_axis_tvalid_int <= '1';
IF s_axis_tdata = STD_LOGIC_VECTOR(to_unsigned(FOOTER, 8)) THEN IF s_axis_tdata = STD_LOGIC_VECTOR(to_unsigned(FOOTER, 8)) THEN
m_axis_tlast <= '1'; m_axis_tlast_int <= '1';
state <= WAITING_HEADER; state <= WAITING_HEADER;
s_axis_tready_int <= '0';
data_ready <= '0';
ELSE ELSE
trigger <= '1'; state <= SEND;
s_axis_tready_int <= '0';
END IF; END IF;
END IF; END IF;
data_buffer <= s_axis_tdata;
data_ready <= '1';
END IF;
WHEN SEND =>
IF m_axis_tvalid_int = '1' AND m_axis_tready = '1' THEN
m_axis_tvalid_int <= '0';
s_axis_tready_int <= '1';
state <= RECEIVING;
END IF;
END CASE; END CASE;
END IF; END IF;
END IF; END IF;
END PROCESS; END PROCESS;
END ARCHITECTURE; END ARCHITECTURE;