Refactor and clean up project files

- Removed obsolete GraphML file `pak_depak.bda` and UI file `bd_c9b29a54.ui`.
- Updated `rgb2gray.vhd` to improve signal handling and state machine logic.
- Created new Vivado project files for `depacketizer_test`, including testbench configuration.
- Adjusted `pak_depak.xpr` to disable the FIFO module and set the top module correctly.
- Updated `rgb2grey_test.xpr` to modify simulation launch settings.

.gitignore

@@ -68,12 +68,4 @@ vivado*.backup.log
 
 
 # SDK workspace
-.sdk/
-
-# Lab2 files
-LAB2/src/lab_2/ipshared/
-LAB2/src/lab_2/ip/
-LAB2/src/lab_2/sim/
-LAB2/src/lab_2/synth/
-LAB2/src/lab_2/ui/
-LAB2/src/lab_2/hw_handoff/
+.sdk/

LAB2/sim/tb_depacketizer.vhd

@@ -0,0 +1,240 @@
+----------------------------------------------------------------------------------
+-- Company: 
+-- Engineer: 
+-- 
+-- Create Date: 04/21/2025
+-- Design Name: 
+-- Module Name: tb_depacketizer - Behavioral
+-- Project Name: 
+-- Target Devices: 
+-- Tool Versions: 
+-- Description: Testbench for depacketizer
+-- 
+-- Dependencies: 
+-- 
+-- Revision:
+-- Revision 0.01 - File Created
+-- Additional Comments:
+-- 
+----------------------------------------------------------------------------------
+LIBRARY IEEE;
+USE IEEE.STD_LOGIC_1164.ALL;
+USE IEEE.NUMERIC_STD.ALL;
+
+ENTITY tb_depacketizer IS
+END tb_depacketizer;
+
+ARCHITECTURE Behavioral OF tb_depacketizer IS
+
+    COMPONENT depacketizer IS
+        GENERIC (
+            HEADER : INTEGER := 16#FF#;
+            FOOTER : INTEGER := 16#F1#
+        );
+        PORT (
+            clk : IN STD_LOGIC;
+            aresetn : IN STD_LOGIC;
+
+            s_axis_tdata : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
+            s_axis_tvalid : IN STD_LOGIC;
+            s_axis_tready : OUT STD_LOGIC;
+
+            m_axis_tdata : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
+            m_axis_tvalid : OUT STD_LOGIC;
+            m_axis_tready : IN STD_LOGIC;
+            m_axis_tlast : OUT STD_LOGIC
+        );
+    END COMPONENT;
+
+    -- Constants
+    CONSTANT HEADER : INTEGER := 16#FF#;
+    CONSTANT FOOTER : INTEGER := 16#F1#;
+
+    -- Signals
+    SIGNAL clk : STD_LOGIC := '0';
+    SIGNAL aresetn : STD_LOGIC := '0';
+
+    SIGNAL s_axis_tdata : STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');
+    SIGNAL s_axis_tvalid : STD_LOGIC := '0';
+    SIGNAL s_axis_tready : STD_LOGIC;
+
+    SIGNAL m_axis_tdata : STD_LOGIC_VECTOR(7 DOWNTO 0);
+    SIGNAL m_axis_tvalid : STD_LOGIC;
+    SIGNAL m_axis_tready : STD_LOGIC := '1';
+    SIGNAL m_axis_tlast : STD_LOGIC;
+
+    -- Stimulus memory
+    TYPE mem_type IS ARRAY(0 TO 7) OF STD_LOGIC_VECTOR(7 DOWNTO 0);
+    SIGNAL mem : mem_type := (
+        0 => x"10",
+        1 => x"20",
+        2 => x"30",
+        3 => x"04",
+        4 => x"54",
+        5 => x"65",
+        6 => x"73",
+        7 => x"90"
+    );
+
+    SIGNAL tready_block_req : STD_LOGIC := '0';
+
+BEGIN
+
+    -- Clock generation
+    clk <= NOT clk AFTER 5 ns;
+
+    -- Asynchronous tready block process
+    PROCESS (clk)
+        VARIABLE block_counter : INTEGER := 0;
+        VARIABLE tready_blocked : BOOLEAN := FALSE;
+    BEGIN
+        IF rising_edge(clk) THEN
+            IF tready_block_req = '1' AND NOT tready_blocked THEN
+                tready_blocked := TRUE;
+                block_counter := 0;
+            END IF;
+
+            IF tready_blocked THEN
+                IF block_counter < 9 THEN
+                    m_axis_tready <= '0';
+                    block_counter := block_counter + 1;
+                ELSE
+                    m_axis_tready <= '1';
+                    tready_blocked := FALSE;
+                    block_counter := 0;
+                END IF;
+            ELSE
+                m_axis_tready <= '1';
+            END IF;
+        END IF;
+    END PROCESS;
+
+    -- DUT instantiation
+    uut: depacketizer
+        PORT MAP (
+            clk => clk,
+            aresetn => aresetn,
+
+            s_axis_tdata => s_axis_tdata,
+            s_axis_tvalid => s_axis_tvalid,
+            s_axis_tready => s_axis_tready,
+
+            m_axis_tdata => m_axis_tdata,
+            m_axis_tvalid => m_axis_tvalid,
+            m_axis_tready => m_axis_tready,
+            m_axis_tlast => m_axis_tlast
+        );
+
+    -- Stimulus process
+    PROCESS
+    BEGIN
+        -- Reset
+        aresetn <= '0';
+        WAIT FOR 20 ns;
+        aresetn <= '1';
+        WAIT UNTIL rising_edge(clk);
+
+        -- Start tready block asynchronously after 60 ns
+        WAIT FOR 60 ns;
+        tready_block_req <= '1';
+        WAIT UNTIL rising_edge(clk);
+        tready_block_req <= '0';
+
+        -- Send 4 data words as a packet with Header and Footer
+        -- Header
+        s_axis_tdata <= STD_LOGIC_VECTOR(TO_UNSIGNED(HEADER, 8));
+        s_axis_tvalid <= '1';
+        WAIT UNTIL s_axis_tvalid = '1' AND s_axis_tready = '1' AND rising_edge(clk);
+        s_axis_tvalid <= '0';
+
+        -- Data
+        FOR i IN 0 TO 3 LOOP
+            s_axis_tdata <= mem(i);
+            s_axis_tvalid <= '1';
+            WAIT UNTIL s_axis_tvalid = '1' AND s_axis_tready = '1' AND rising_edge(clk);
+            s_axis_tvalid <= '0';
+        END LOOP;
+
+        -- Footer
+        s_axis_tdata <= STD_LOGIC_VECTOR(TO_UNSIGNED(FOOTER, 8));
+        s_axis_tvalid <= '1';
+        WAIT UNTIL s_axis_tvalid = '1' AND s_axis_tready = '1' AND rising_edge(clk);
+        s_axis_tvalid <= '0';
+
+        -- Wait a bit, then send another packet of 2 words with Header and Footer
+        WAIT FOR 50 ns;
+
+        -- Header
+        s_axis_tdata <= STD_LOGIC_VECTOR(TO_UNSIGNED(HEADER, 8));
+        s_axis_tvalid <= '1';
+        WAIT UNTIL s_axis_tvalid = '1' AND s_axis_tready = '1' AND rising_edge(clk);
+        s_axis_tvalid <= '0';
+
+        -- Data
+        FOR i IN 4 TO 5 LOOP
+            s_axis_tdata <= mem(i);
+            s_axis_tvalid <= '1';
+            WAIT UNTIL s_axis_tvalid = '1' AND s_axis_tready = '1' AND rising_edge(clk);
+            s_axis_tvalid <= '0';
+        END LOOP;
+
+        -- Footer
+        s_axis_tdata <= STD_LOGIC_VECTOR(TO_UNSIGNED(FOOTER, 8));
+        s_axis_tvalid <= '1';
+        WAIT UNTIL s_axis_tvalid = '1' AND s_axis_tready = '1' AND rising_edge(clk);
+        s_axis_tvalid <= '0';
+
+        -- Start another tready block asynchronously
+        WAIT FOR 40 ns;
+        tready_block_req <= '1';
+        WAIT UNTIL rising_edge(clk);
+        tready_block_req <= '0';
+
+        -- Send packet of 3 words with Header and Footer
+        WAIT FOR 30 ns;
+
+        -- Header
+        s_axis_tdata <= STD_LOGIC_VECTOR(TO_UNSIGNED(HEADER, 8));
+        s_axis_tvalid <= '1';
+        WAIT UNTIL s_axis_tvalid = '1' AND s_axis_tready = '1' AND rising_edge(clk);
+        s_axis_tvalid <= '0';
+
+        -- Data
+        FOR i IN 5 TO 7 LOOP
+            s_axis_tdata <= mem(i);
+            s_axis_tvalid <= '1';
+            WAIT UNTIL s_axis_tvalid = '1' AND s_axis_tready = '1' AND rising_edge(clk);
+            s_axis_tvalid <= '0';
+        END LOOP;
+
+        -- Footer
+        s_axis_tdata <= STD_LOGIC_VECTOR(TO_UNSIGNED(FOOTER, 8));
+        s_axis_tvalid <= '1';
+        WAIT UNTIL s_axis_tvalid = '1' AND s_axis_tready = '1' AND rising_edge(clk);
+        s_axis_tvalid <= '0';
+
+        -- Send packet of 4 words without initial waiting, with Header and Footer
+        -- Header
+        s_axis_tdata <= STD_LOGIC_VECTOR(TO_UNSIGNED(HEADER, 8));
+        s_axis_tvalid <= '1';
+        WAIT UNTIL s_axis_tvalid = '1' AND s_axis_tready = '1' AND rising_edge(clk);
+        s_axis_tvalid <= '0';
+
+        -- Data
+        FOR i IN 2 TO 6 LOOP
+            s_axis_tdata <= mem(i);
+            s_axis_tvalid <= '1';
+            WAIT UNTIL s_axis_tvalid = '1' AND s_axis_tready = '1' AND rising_edge(clk);
+            s_axis_tvalid <= '0';
+        END LOOP;
+
+        -- Footer
+        s_axis_tdata <= STD_LOGIC_VECTOR(TO_UNSIGNED(FOOTER, 8));
+        s_axis_tvalid <= '1';
+        WAIT UNTIL s_axis_tvalid = '1' AND s_axis_tready = '1' AND rising_edge(clk);
+        s_axis_tvalid <= '0';
+
+        WAIT;
+    END PROCESS;
+
+END Behavioral;

LAB2/sim/tb_packetizer.vhd

@@ -71,8 +71,6 @@ ARCHITECTURE Behavioral OF tb_packetizer IS
         7 => x"90"
     );
 
-    SIGNAL data_index : INTEGER := 0;
-
     SIGNAL tready_block_req : STD_LOGIC := '0';
 
 BEGIN

LAB2/sim/tb_rgb2gray.vhd

@@ -40,13 +40,54 @@ ARCHITECTURE Behavioral OF rgb2gray_tb IS
     SIGNAL s_axis_tready : STD_LOGIC;
     SIGNAL s_axis_tlast : STD_LOGIC := '0';
 
-    -- Clock generation
+    -- Stimulus memory for RGB triplets (R, G, B)
+    TYPE rgb_mem_type IS ARRAY(0 TO 8, 0 TO 2) OF STD_LOGIC_VECTOR(7 DOWNTO 0);
+    SIGNAL rgb_mem : rgb_mem_type := (
+        (x"10", x"20", x"30"),
+        (x"40", x"50", x"60"),
+        (x"70", x"80", x"90"),
+        (x"A0", x"B0", x"C0"),
+        (x"D0", x"E0", x"F0"),
+        (x"01", x"02", x"03"),
+        (x"04", x"05", x"06"),
+        (x"07", x"08", x"09"),
+        (x"0A", x"0B", x"0C")
+    );
+
+    SIGNAL tready_block_req : STD_LOGIC := '0';
+
     CONSTANT clk_period : TIME := 10 ns;
 
 BEGIN
 
     clk <= NOT clk AFTER clk_period / 2; -- Clock generation
 
+    -- Asynchronous tready block process (simulate downstream backpressure)
+    PROCESS (clk)
+        VARIABLE block_counter : INTEGER := 0;
+        VARIABLE tready_blocked : BOOLEAN := FALSE;
+    BEGIN
+        IF rising_edge(clk) THEN
+            IF tready_block_req = '1' AND NOT tready_blocked THEN
+                tready_blocked := TRUE;
+                block_counter := 0;
+            END IF;
+
+            IF tready_blocked THEN
+                IF block_counter < 6 THEN
+                    m_axis_tready <= '0';
+                    block_counter := block_counter + 1;
+                ELSE
+                    m_axis_tready <= '1';
+                    tready_blocked := FALSE;
+                    block_counter := 0;
+                END IF;
+            ELSE
+                m_axis_tready <= '1';
+            END IF;
+        END IF;
+    END PROCESS;
+
     -- Instantiate the Device Under Test (DUT)
     DUT : rgb2gray
     PORT MAP(
@@ -64,91 +105,91 @@ BEGIN
 
     -- Stimulus process
     stimulus_process : PROCESS
-        VARIABLE pixel_value : INTEGER := 1; -- Variable to increment pixel values
     BEGIN
-        WAIT FOR 10 ns;
+        -- Reset
+        resetn <= '0';
+        WAIT FOR 20 ns;
         resetn <= '1';
-        s_axis_tvalid <= '1';
+        WAIT UNTIL rising_edge(clk);
 
-        -- Send multiple RGB pixels with incrementing values
-        FOR i IN 0 TO 5 LOOP -- Send 10 pixels
-            -- R component
-            s_axis_tdata <= STD_LOGIC_VECTOR(TO_UNSIGNED(pixel_value, 8));
-            WAIT FOR clk_period;
+        -- Start tready block asynchronously after 40 ns
+        WAIT FOR 40 ns;
+        tready_block_req <= '1';
+        WAIT UNTIL rising_edge(clk);
+        tready_block_req <= '0';
 
-            -- G component
-            pixel_value := pixel_value + 5;
-            s_axis_tdata <= STD_LOGIC_VECTOR(TO_UNSIGNED(pixel_value, 8));
-            WAIT FOR clk_period;
-
-            -- B component
-            pixel_value := pixel_value + 1;
-            s_axis_tdata <= STD_LOGIC_VECTOR(TO_UNSIGNED(pixel_value, 8));
-            WAIT FOR clk_period;
-
-            -- Reset last signal
-            pixel_value := pixel_value + 1;
+        -- Send 3 RGB pixels (9 bytes)
+        FOR i IN 0 TO 2 LOOP
+            FOR j IN 0 TO 2 LOOP
+                s_axis_tdata <= rgb_mem(i, j);
+                s_axis_tvalid <= '1';
+                IF i = 2 AND j = 2 THEN
+                    s_axis_tlast <= '1';
+                ELSE
+                    s_axis_tlast <= '0';
+                END IF;
+                -- Wait for handshake
+                WAIT UNTIL s_axis_tvalid = '1' AND s_axis_tready = '1' AND rising_edge(clk);
+                s_axis_tvalid <= '0';
+            END LOOP;
         END LOOP;
+        s_axis_tlast <= '0';
 
-        m_axis_tready <= '0';
-
-        -- R component
-        s_axis_tdata <= STD_LOGIC_VECTOR(TO_UNSIGNED(pixel_value, 8));
-        WAIT FOR clk_period;
-
-        -- G component
-        pixel_value := pixel_value + 5;
-        s_axis_tdata <= STD_LOGIC_VECTOR(TO_UNSIGNED(pixel_value, 8));
-        WAIT FOR clk_period;
-
-        -- B component
-        pixel_value := pixel_value + 1;
-        s_axis_tdata <= STD_LOGIC_VECTOR(TO_UNSIGNED(pixel_value, 8));
-        WAIT FOR clk_period;
-
-        FOR i IN 0 TO 3 LOOP -- Send 10 pixels
-            -- R component
-            s_axis_tdata <= STD_LOGIC_VECTOR(TO_UNSIGNED(pixel_value, 8));
-            WAIT FOR clk_period;
-
-            -- G component
-            pixel_value := pixel_value + 5;
-            s_axis_tdata <= STD_LOGIC_VECTOR(TO_UNSIGNED(pixel_value, 8));
-            WAIT FOR clk_period;
-
-            -- B component
-            pixel_value := pixel_value + 1;
-            s_axis_tdata <= STD_LOGIC_VECTOR(TO_UNSIGNED(pixel_value, 8));
-            WAIT FOR clk_period;
-
-            -- Reset last signal
-            pixel_value := pixel_value + 1;
+        -- Wait, then send 2 more RGB pixels
+        WAIT FOR 30 ns;
+        FOR i IN 3 TO 4 LOOP
+            FOR j IN 0 TO 2 LOOP
+                s_axis_tdata <= rgb_mem(i, j);
+                s_axis_tvalid <= '1';
+                IF i = 4 AND j = 2 THEN
+                    s_axis_tlast <= '1';
+                ELSE
+                    s_axis_tlast <= '0';
+                END IF;
+                WAIT UNTIL s_axis_tvalid = '1' AND s_axis_tready = '1' AND rising_edge(clk);
+                s_axis_tvalid <= '0';
+            END LOOP;
         END LOOP;
+        s_axis_tlast <= '0';
 
-        m_axis_tready <= '1';
+        -- Start another tready block asynchronously
+        WAIT FOR 30 ns;
+        tready_block_req <= '1';
+        WAIT UNTIL rising_edge(clk);
+        tready_block_req <= '0';
 
-        FOR i IN 0 TO 3 LOOP -- Send 10 pixels
-            -- R component
-            s_axis_tdata <= STD_LOGIC_VECTOR(TO_UNSIGNED(pixel_value, 8));
-            WAIT FOR clk_period;
-
-            -- G component
-            pixel_value := pixel_value + 5;
-            s_axis_tdata <= STD_LOGIC_VECTOR(TO_UNSIGNED(pixel_value, 8));
-            WAIT FOR clk_period;
-
-            -- B component
-            pixel_value := pixel_value + 1;
-            s_axis_tdata <= STD_LOGIC_VECTOR(TO_UNSIGNED(pixel_value, 8));
-            WAIT FOR clk_period;
-
-            -- Reset last signal
-            pixel_value := pixel_value + 1;
+        -- Send 2 more RGB pixels
+        WAIT FOR 20 ns;
+        FOR i IN 5 TO 6 LOOP
+            FOR j IN 0 TO 2 LOOP
+                s_axis_tdata <= rgb_mem(i, j);
+                s_axis_tvalid <= '1';
+                IF i = 6 AND j = 2 THEN
+                    s_axis_tlast <= '1';
+                ELSE
+                    s_axis_tlast <= '0';
+                END IF;
+                WAIT UNTIL s_axis_tvalid = '1' AND s_axis_tready = '1' AND rising_edge(clk);
+                s_axis_tvalid <= '0';
+            END LOOP;
         END LOOP;
+        s_axis_tlast <= '0';
 
-        -- Deassert valid signal
-        s_axis_tlast <= '1'; -- Indicate end of pixel
-        s_axis_tvalid <= '0';
+        -- Send last 2 RGB pixels
+        FOR i IN 7 TO 8 LOOP
+            FOR j IN 0 TO 2 LOOP
+                s_axis_tdata <= rgb_mem(i, j);
+                s_axis_tvalid <= '1';
+                IF i = 8 AND j = 2 THEN
+                    s_axis_tlast <= '1';
+                ELSE
+                    s_axis_tlast <= '0';
+                END IF;
+                WAIT UNTIL s_axis_tvalid = '1' AND s_axis_tready = '1' AND rising_edge(clk);
+                s_axis_tvalid <= '0';
+            END LOOP;
+        END LOOP;
+        s_axis_tlast <= '0';
 
         WAIT;
     END PROCESS;

LAB2/src/depacketizer.vhd

@@ -18,63 +18,55 @@ ENTITY depacketizer IS
 
         m_axis_tdata : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
         m_axis_tvalid : OUT STD_LOGIC;
-        m_axis_tlast : OUT STD_LOGIC;
-        m_axis_tready : IN STD_LOGIC
+        m_axis_tready : IN STD_LOGIC;
+        m_axis_tlast : OUT STD_LOGIC
     );
 
 END ENTITY depacketizer;
 
 ARCHITECTURE rtl OF depacketizer IS
 
-    TYPE state_type IS (IDLE, RECEIVING);
-    SIGNAL state : state_type := IDLE;
+    TYPE state_type IS (WAITING_HEADER, RECEIVING);
+    SIGNAL state : state_type := WAITING_HEADER;
 
     SIGNAL data_buffer : STD_LOGIC_VECTOR(7 DOWNTO 0);
 
     SIGNAL s_axis_tready_int : STD_LOGIC;
     SIGNAL m_axis_tvalid_int : STD_LOGIC;
 
+    SIGNAL trigger : STD_LOGIC := '0';
+
 BEGIN
 
     s_axis_tready <= s_axis_tready_int;
     m_axis_tvalid <= m_axis_tvalid_int;
 
     PROCESS (clk)
-        VARIABLE trigger : STD_LOGIC := '0';
     BEGIN
 
         IF rising_edge(clk) THEN
             IF aresetn = '0' THEN
+                state <= WAITING_HEADER;
 
                 data_buffer <= (OTHERS => '0');
 
+                m_axis_tdata <= (OTHERS => '0');
+                m_axis_tlast <= '0';
+
                 s_axis_tready_int <= '0';
                 m_axis_tvalid_int <= '0';
-                m_axis_tlast <= '0';
 
             ELSE
 
-                CASE state IS
-                    WHEN IDLE =>
-                        IF s_axis_tvalid = '1' AND s_axis_tready_int = '1' THEN
-                            IF data_buffer = STD_LOGIC_VECTOR(to_unsigned(HEADER, 8)) THEN
-                                state <= RECEIVING;
-                            END IF;
-                        END IF;
+                -- Default values
+                m_axis_tlast <= '0';
 
-                    WHEN RECEIVING =>
-                        IF s_axis_tvalid = '1' AND s_axis_tready_int = '1' THEN
-                            IF s_axis_tdata = STD_LOGIC_VECTOR(to_unsigned(FOOTER, 8)) THEN
-                                m_axis_tlast <= '1';
-                                state <= IDLE;
-                            ELSE
-                                m_axis_tlast <= '0';
-                            END IF;
+                -- Input data - slave
+                s_axis_tready_int <= m_axis_tready;
 
-                            trigger := '1';
-                        END IF;
-
-                END CASE;
+                IF s_axis_tvalid = '1' AND s_axis_tready_int = '1' THEN
+                    data_buffer <= s_axis_tdata;
+                END IF;
 
                 -- Output data - master
                 IF m_axis_tready = '1' THEN
@@ -85,16 +77,30 @@ BEGIN
                     m_axis_tvalid_int <= '1';
                     m_axis_tdata <= data_buffer;
 
-                    trigger := '0';
+                    trigger <= '0';
                 END IF;
 
-                -- Input data - slave
-                s_axis_tready_int <= m_axis_tready;
+                -- State machine for depacketization
+                CASE state IS
+                    WHEN WAITING_HEADER =>
+                        IF s_axis_tvalid = '1' AND s_axis_tready_int = '1' THEN
+                            IF data_buffer = STD_LOGIC_VECTOR(to_unsigned(HEADER, 8)) THEN
+                                trigger <= '1';
+                                state <= RECEIVING;
+                            END IF;
+                        END IF;
 
-                IF s_axis_tvalid = '1' AND s_axis_tready_int = '1' THEN
-                    data_buffer <= s_axis_tdata;
-                END IF;
+                    WHEN RECEIVING =>
+                        IF s_axis_tvalid = '1' AND s_axis_tready_int = '1' THEN
+                            IF s_axis_tdata = STD_LOGIC_VECTOR(to_unsigned(FOOTER, 8)) THEN
+                                m_axis_tlast <= '1';
+                                state <= WAITING_HEADER;
+                            ELSE
+                                trigger <= '1';
+                            END IF;
+                        END IF;
 
+                END CASE;
             END IF;
         END IF;
 

LAB2/src/lab_2/hdl/lab_2_wrapper.vhd

@@ -1,49 +0,0 @@
---Copyright 1986-2020 Xilinx, Inc. All Rights Reserved.
-----------------------------------------------------------------------------------
---Tool Version: Vivado v.2020.2 (win64) Build 3064766 Wed Nov 18 09:12:45 MST 2020
---Date        : Wed Apr  9 11:36:10 2025
---Host        : Davide-Samsung running 64-bit major release  (build 9200)
---Command     : generate_target lab_2_wrapper.bd
---Design      : lab_2_wrapper
---Purpose     : IP block netlist
-----------------------------------------------------------------------------------
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-library UNISIM;
-use UNISIM.VCOMPONENTS.ALL;
-entity lab_2_wrapper is
-  port (
-    led_of : out STD_LOGIC;
-    led_ok : out STD_LOGIC;
-    led_uf : out STD_LOGIC;
-    reset : in STD_LOGIC;
-    sys_clock : in STD_LOGIC;
-    usb_uart_rxd : in STD_LOGIC;
-    usb_uart_txd : out STD_LOGIC
-  );
-end lab_2_wrapper;
-
-architecture STRUCTURE of lab_2_wrapper is
-  component lab_2 is
-  port (
-    led_of : out STD_LOGIC;
-    led_ok : out STD_LOGIC;
-    led_uf : out STD_LOGIC;
-    sys_clock : in STD_LOGIC;
-    reset : in STD_LOGIC;
-    usb_uart_txd : out STD_LOGIC;
-    usb_uart_rxd : in STD_LOGIC
-  );
-  end component lab_2;
-begin
-lab_2_i: component lab_2
-     port map (
-      led_of => led_of,
-      led_ok => led_ok,
-      led_uf => led_uf,
-      reset => reset,
-      sys_clock => sys_clock,
-      usb_uart_rxd => usb_uart_rxd,
-      usb_uart_txd => usb_uart_txd
-    );
-end STRUCTURE;

LAB2/src/lab_2/lab_2.bda

@@ -1,42 +0,0 @@
-<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
-<graphml xmlns="http://graphml.graphdrawing.org/xmlns" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:schemaLocation="http://graphml.graphdrawing.org/xmlns http://graphml.graphdrawing.org/xmlns/1.0/graphml.xsd">
-  <key attr.name="base_addr" attr.type="string" for="node" id="BA"/>
-  <key attr.name="base_param" attr.type="string" for="node" id="BP"/>
-  <key attr.name="edge_hid" attr.type="int" for="edge" id="EH"/>
-  <key attr.name="high_addr" attr.type="string" for="node" id="HA"/>
-  <key attr.name="high_param" attr.type="string" for="node" id="HP"/>
-  <key attr.name="master_addrspace" attr.type="string" for="node" id="MA"/>
-  <key attr.name="master_instance" attr.type="string" for="node" id="MX"/>
-  <key attr.name="master_interface" attr.type="string" for="node" id="MI"/>
-  <key attr.name="master_segment" attr.type="string" for="node" id="MS"/>
-  <key attr.name="master_vlnv" attr.type="string" for="node" id="MV"/>
-  <key attr.name="memory_type" attr.type="string" for="node" id="TM"/>
-  <key attr.name="slave_instance" attr.type="string" for="node" id="SX"/>
-  <key attr.name="slave_interface" attr.type="string" for="node" id="SI"/>
-  <key attr.name="slave_segment" attr.type="string" for="node" id="SS"/>
-  <key attr.name="slave_vlnv" attr.type="string" for="node" id="SV"/>
-  <key attr.name="usage_type" attr.type="string" for="node" id="TU"/>
-  <key attr.name="vert_hid" attr.type="int" for="node" id="VH"/>
-  <key attr.name="vert_name" attr.type="string" for="node" id="VM"/>
-  <key attr.name="vert_type" attr.type="string" for="node" id="VT"/>
-  <graph edgedefault="undirected" id="G" parse.edgeids="canonical" parse.nodeids="canonical" parse.order="nodesfirst">
-    <node id="n0">
-      <data key="VM">lab_2</data>
-      <data key="VT">BC</data>
-    </node>
-    <node id="n1">
-      <data key="VH">2</data>
-      <data key="VM">lab_2</data>
-      <data key="VT">VR</data>
-    </node>
-    <node id="n2">
-      <data key="TU">active</data>
-      <data key="VH">2</data>
-      <data key="VT">PM</data>
-    </node>
-    <edge id="e0" source="n0" target="n1">
-    </edge>
-    <edge id="e1" source="n1" target="n2">
-    </edge>
-  </graph>
-</graphml>

LAB2/src/packetizer.vhd

@@ -49,7 +49,6 @@ BEGIN
                 data_buffer <= (OTHERS => '0');
 
                 m_axis_tdata <= (OTHERS => '0');
-                m_axis_tvalid_int <= '0';
 
                 s_axis_tready_int <= '0';
                 m_axis_tvalid_int <= '0';

LAB2/src/pak_depak/hdl/pak_depak_wrapper.vhd

@@ -1,40 +0,0 @@
---Copyright 1986-2020 Xilinx, Inc. All Rights Reserved.
-----------------------------------------------------------------------------------
---Tool Version: Vivado v.2020.2 (win64) Build 3064766 Wed Nov 18 09:12:45 MST 2020
---Date        : Mon Apr 14 16:01:03 2025
---Host        : Davide-Samsung running 64-bit major release  (build 9200)
---Command     : generate_target pak_depak_wrapper.bd
---Design      : pak_depak_wrapper
---Purpose     : IP block netlist
-----------------------------------------------------------------------------------
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-library UNISIM;
-use UNISIM.VCOMPONENTS.ALL;
-entity pak_depak_wrapper is
-  port (
-    reset : in STD_LOGIC;
-    sys_clock : in STD_LOGIC;
-    usb_uart_rxd : in STD_LOGIC;
-    usb_uart_txd : out STD_LOGIC
-  );
-end pak_depak_wrapper;
-
-architecture STRUCTURE of pak_depak_wrapper is
-  component pak_depak is
-  port (
-    reset : in STD_LOGIC;
-    sys_clock : in STD_LOGIC;
-    usb_uart_txd : out STD_LOGIC;
-    usb_uart_rxd : in STD_LOGIC
-  );
-  end component pak_depak;
-begin
-pak_depak_i: component pak_depak
-     port map (
-      reset => reset,
-      sys_clock => sys_clock,
-      usb_uart_rxd => usb_uart_rxd,
-      usb_uart_txd => usb_uart_txd
-    );
-end STRUCTURE;

LAB2/src/pak_depak/ip/pak_depak_AXI4Stream_UART_0_0/sim/pak_depak_AXI4Stream_UART_0_0.vhd

@@ -1,151 +0,0 @@
--- (c) Copyright 1995-2025 Xilinx, Inc. All rights reserved.
--- 
--- This file contains confidential and proprietary information
--- of Xilinx, Inc. and is protected under U.S. and
--- international copyright and other intellectual property
--- laws.
--- 
--- DISCLAIMER
--- This disclaimer is not a license and does not grant any
--- rights to the materials distributed herewith. Except as
--- otherwise provided in a valid license issued to you by
--- Xilinx, and to the maximum extent permitted by applicable
--- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
--- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
--- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
--- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
--- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
--- (2) Xilinx shall not be liable (whether in contract or tort,
--- including negligence, or under any other theory of
--- liability) for any loss or damage of any kind or nature
--- related to, arising under or in connection with these
--- materials, including for any direct, or any indirect,
--- special, incidental, or consequential loss or damage
--- (including loss of data, profits, goodwill, or any type of
--- loss or damage suffered as a result of any action brought
--- by a third party) even if such damage or loss was
--- reasonably foreseeable or Xilinx had been advised of the
--- possibility of the same.
--- 
--- CRITICAL APPLICATIONS
--- Xilinx products are not designed or intended to be fail-
--- safe, or for use in any application requiring fail-safe
--- performance, such as life-support or safety devices or
--- systems, Class III medical devices, nuclear facilities,
--- applications related to the deployment of airbags, or any
--- other applications that could lead to death, personal
--- injury, or severe property or environmental damage
--- (individually and collectively, "Critical
--- Applications"). Customer assumes the sole risk and
--- liability of any use of Xilinx products in Critical
--- Applications, subject only to applicable laws and
--- regulations governing limitations on product liability.
--- 
--- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
--- PART OF THIS FILE AT ALL TIMES.
--- 
--- DO NOT MODIFY THIS FILE.
-
--- IP VLNV: DigiLAB:ip:AXI4Stream_UART:1.1
--- IP Revision: 1
-
-LIBRARY ieee;
-USE ieee.std_logic_1164.ALL;
-USE ieee.numeric_std.ALL;
-
-ENTITY pak_depak_AXI4Stream_UART_0_0 IS
-  PORT (
-    clk_uart : IN STD_LOGIC;
-    rst : IN STD_LOGIC;
-    UART_TX : OUT STD_LOGIC;
-    UART_RX : IN STD_LOGIC;
-    m00_axis_rx_aclk : IN STD_LOGIC;
-    m00_axis_rx_aresetn : IN STD_LOGIC;
-    m00_axis_rx_tvalid : OUT STD_LOGIC;
-    m00_axis_rx_tdata : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
-    m00_axis_rx_tready : IN STD_LOGIC;
-    s00_axis_tx_aclk : IN STD_LOGIC;
-    s00_axis_tx_aresetn : IN STD_LOGIC;
-    s00_axis_tx_tready : OUT STD_LOGIC;
-    s00_axis_tx_tdata : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
-    s00_axis_tx_tvalid : IN STD_LOGIC
-  );
-END pak_depak_AXI4Stream_UART_0_0;
-
-ARCHITECTURE pak_depak_AXI4Stream_UART_0_0_arch OF pak_depak_AXI4Stream_UART_0_0 IS
-  ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
-  ATTRIBUTE DowngradeIPIdentifiedWarnings OF pak_depak_AXI4Stream_UART_0_0_arch: ARCHITECTURE IS "yes";
-  COMPONENT AXI4Stream_UART_v1_0 IS
-    GENERIC (
-      UART_BAUD_RATE : INTEGER;
-      UART_CLOCK_FREQUENCY : INTEGER;
-      C_M00_AXIS_RX_TDATA_WIDTH : INTEGER;
-      C_S00_AXIS_TX_TDATA_WIDTH : INTEGER
-    );
-    PORT (
-      clk_uart : IN STD_LOGIC;
-      rst : IN STD_LOGIC;
-      UART_TX : OUT STD_LOGIC;
-      UART_RX : IN STD_LOGIC;
-      m00_axis_rx_aclk : IN STD_LOGIC;
-      m00_axis_rx_aresetn : IN STD_LOGIC;
-      m00_axis_rx_tvalid : OUT STD_LOGIC;
-      m00_axis_rx_tdata : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
-      m00_axis_rx_tready : IN STD_LOGIC;
-      s00_axis_tx_aclk : IN STD_LOGIC;
-      s00_axis_tx_aresetn : IN STD_LOGIC;
-      s00_axis_tx_tready : OUT STD_LOGIC;
-      s00_axis_tx_tdata : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
-      s00_axis_tx_tvalid : IN STD_LOGIC
-    );
-  END COMPONENT AXI4Stream_UART_v1_0;
-  ATTRIBUTE X_INTERFACE_INFO : STRING;
-  ATTRIBUTE X_INTERFACE_PARAMETER : STRING;
-  ATTRIBUTE X_INTERFACE_INFO OF s00_axis_tx_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 S00_AXIS_TX TVALID";
-  ATTRIBUTE X_INTERFACE_INFO OF s00_axis_tx_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 S00_AXIS_TX TDATA";
-  ATTRIBUTE X_INTERFACE_PARAMETER OF s00_axis_tx_tready: SIGNAL IS "XIL_INTERFACENAME S00_AXIS_TX, WIZ_DATA_WIDTH 32, TDATA_NUM_BYTES 1, TDEST_WIDTH 0, TID_WIDTH 0, TUSER_WIDTH 0, HAS_TREADY 1, HAS_TSTRB 0, HAS_TKEEP 0, HAS_TLAST 0, FREQ_HZ 100000000, PHASE 0.0, CLK_DOMAIN /clk_wiz_0_clk_out1, LAYERED_METADATA undef, INSERT_VIP 0";
-  ATTRIBUTE X_INTERFACE_INFO OF s00_axis_tx_tready: SIGNAL IS "xilinx.com:interface:axis:1.0 S00_AXIS_TX TREADY";
-  ATTRIBUTE X_INTERFACE_PARAMETER OF s00_axis_tx_aresetn: SIGNAL IS "XIL_INTERFACENAME S00_AXIS_TX_RST, POLARITY ACTIVE_LOW, INSERT_VIP 0";
-  ATTRIBUTE X_INTERFACE_INFO OF s00_axis_tx_aresetn: SIGNAL IS "xilinx.com:signal:reset:1.0 S00_AXIS_TX_RST RST";
-  ATTRIBUTE X_INTERFACE_PARAMETER OF s00_axis_tx_aclk: SIGNAL IS "XIL_INTERFACENAME S00_AXIS_TX_CLK, ASSOCIATED_BUSIF S00_AXIS_TX, ASSOCIATED_RESET s00_axis_tx_aresetn, FREQ_HZ 100000000, FREQ_TOLERANCE_HZ 0, PHASE 0.0, CLK_DOMAIN /clk_wiz_0_clk_out1, INSERT_VIP 0";
-  ATTRIBUTE X_INTERFACE_INFO OF s00_axis_tx_aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 S00_AXIS_TX_CLK CLK";
-  ATTRIBUTE X_INTERFACE_INFO OF m00_axis_rx_tready: SIGNAL IS "xilinx.com:interface:axis:1.0 M00_AXIS_RX TREADY";
-  ATTRIBUTE X_INTERFACE_INFO OF m00_axis_rx_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 M00_AXIS_RX TDATA";
-  ATTRIBUTE X_INTERFACE_PARAMETER OF m00_axis_rx_tvalid: SIGNAL IS "XIL_INTERFACENAME M00_AXIS_RX, WIZ_DATA_WIDTH 32, TDATA_NUM_BYTES 1, TDEST_WIDTH 0, TID_WIDTH 0, TUSER_WIDTH 0, HAS_TREADY 1, HAS_TSTRB 0, HAS_TKEEP 0, HAS_TLAST 0, FREQ_HZ 100000000, PHASE 0.0, CLK_DOMAIN /clk_wiz_0_clk_out1, LAYERED_METADATA undef, INSERT_VIP 0";
-  ATTRIBUTE X_INTERFACE_INFO OF m00_axis_rx_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 M00_AXIS_RX TVALID";
-  ATTRIBUTE X_INTERFACE_PARAMETER OF m00_axis_rx_aresetn: SIGNAL IS "XIL_INTERFACENAME M00_AXIS_RX_RST, POLARITY ACTIVE_LOW, INSERT_VIP 0";
-  ATTRIBUTE X_INTERFACE_INFO OF m00_axis_rx_aresetn: SIGNAL IS "xilinx.com:signal:reset:1.0 M00_AXIS_RX_RST RST";
-  ATTRIBUTE X_INTERFACE_PARAMETER OF m00_axis_rx_aclk: SIGNAL IS "XIL_INTERFACENAME M00_AXIS_RX_CLK, ASSOCIATED_BUSIF M00_AXIS_RX, ASSOCIATED_RESET m00_axis_rx_aresetn, FREQ_HZ 100000000, FREQ_TOLERANCE_HZ 0, PHASE 0.0, CLK_DOMAIN /clk_wiz_0_clk_out1, INSERT_VIP 0";
-  ATTRIBUTE X_INTERFACE_INFO OF m00_axis_rx_aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 M00_AXIS_RX_CLK CLK";
-  ATTRIBUTE X_INTERFACE_INFO OF UART_RX: SIGNAL IS "xilinx.com:interface:uart:1.0 UART RxD";
-  ATTRIBUTE X_INTERFACE_PARAMETER OF UART_TX: SIGNAL IS "XIL_INTERFACENAME UART, BOARD.ASSOCIATED_PARAM UART_BOARD_INTERFACE";
-  ATTRIBUTE X_INTERFACE_INFO OF UART_TX: SIGNAL IS "xilinx.com:interface:uart:1.0 UART TxD";
-  ATTRIBUTE X_INTERFACE_PARAMETER OF rst: SIGNAL IS "XIL_INTERFACENAME reset, POLARITY ACTIVE_HIGH, INSERT_VIP 0";
-  ATTRIBUTE X_INTERFACE_INFO OF rst: SIGNAL IS "xilinx.com:signal:reset:1.0 reset RST";
-  ATTRIBUTE X_INTERFACE_PARAMETER OF clk_uart: SIGNAL IS "XIL_INTERFACENAME ClockUART, ASSOCIATED_BUSIF UART, ASSOCIATED_RESET rst, FREQ_HZ 100000000, FREQ_TOLERANCE_HZ 0, PHASE 0.0, CLK_DOMAIN /clk_wiz_0_clk_out1, INSERT_VIP 0";
-  ATTRIBUTE X_INTERFACE_INFO OF clk_uart: SIGNAL IS "xilinx.com:signal:clock:1.0 ClockUART CLK";
-BEGIN
-  U0 : AXI4Stream_UART_v1_0
-    GENERIC MAP (
-      UART_BAUD_RATE => 115200,
-      UART_CLOCK_FREQUENCY => 100000000,
-      C_M00_AXIS_RX_TDATA_WIDTH => 8,
-      C_S00_AXIS_TX_TDATA_WIDTH => 8
-    )
-    PORT MAP (
-      clk_uart => clk_uart,
-      rst => rst,
-      UART_TX => UART_TX,
-      UART_RX => UART_RX,
-      m00_axis_rx_aclk => m00_axis_rx_aclk,
-      m00_axis_rx_aresetn => m00_axis_rx_aresetn,
-      m00_axis_rx_tvalid => m00_axis_rx_tvalid,
-      m00_axis_rx_tdata => m00_axis_rx_tdata,
-      m00_axis_rx_tready => m00_axis_rx_tready,
-      s00_axis_tx_aclk => s00_axis_tx_aclk,
-      s00_axis_tx_aresetn => s00_axis_tx_aresetn,
-      s00_axis_tx_tready => s00_axis_tx_tready,
-      s00_axis_tx_tdata => s00_axis_tx_tdata,
-      s00_axis_tx_tvalid => s00_axis_tx_tvalid
-    );
-END pak_depak_AXI4Stream_UART_0_0_arch;

LAB2/src/pak_depak/ip/pak_depak_AXI4Stream_UART_0_0/synth/pak_depak_AXI4Stream_UART_0_0.vhd

@@ -1,155 +0,0 @@
--- (c) Copyright 1995-2025 Xilinx, Inc. All rights reserved.
--- 
--- This file contains confidential and proprietary information
--- of Xilinx, Inc. and is protected under U.S. and
--- international copyright and other intellectual property
--- laws.
--- 
--- DISCLAIMER
--- This disclaimer is not a license and does not grant any
--- rights to the materials distributed herewith. Except as
--- otherwise provided in a valid license issued to you by
--- Xilinx, and to the maximum extent permitted by applicable
--- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
--- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
--- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
--- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
--- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
--- (2) Xilinx shall not be liable (whether in contract or tort,
--- including negligence, or under any other theory of
--- liability) for any loss or damage of any kind or nature
--- related to, arising under or in connection with these
--- materials, including for any direct, or any indirect,
--- special, incidental, or consequential loss or damage
--- (including loss of data, profits, goodwill, or any type of
--- loss or damage suffered as a result of any action brought
--- by a third party) even if such damage or loss was
--- reasonably foreseeable or Xilinx had been advised of the
--- possibility of the same.
--- 
--- CRITICAL APPLICATIONS
--- Xilinx products are not designed or intended to be fail-
--- safe, or for use in any application requiring fail-safe
--- performance, such as life-support or safety devices or
--- systems, Class III medical devices, nuclear facilities,
--- applications related to the deployment of airbags, or any
--- other applications that could lead to death, personal
--- injury, or severe property or environmental damage
--- (individually and collectively, "Critical
--- Applications"). Customer assumes the sole risk and
--- liability of any use of Xilinx products in Critical
--- Applications, subject only to applicable laws and
--- regulations governing limitations on product liability.
--- 
--- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
--- PART OF THIS FILE AT ALL TIMES.
--- 
--- DO NOT MODIFY THIS FILE.
-
--- IP VLNV: DigiLAB:ip:AXI4Stream_UART:1.1
--- IP Revision: 1
-
-LIBRARY ieee;
-USE ieee.std_logic_1164.ALL;
-USE ieee.numeric_std.ALL;
-
-ENTITY pak_depak_AXI4Stream_UART_0_0 IS
-  PORT (
-    clk_uart : IN STD_LOGIC;
-    rst : IN STD_LOGIC;
-    UART_TX : OUT STD_LOGIC;
-    UART_RX : IN STD_LOGIC;
-    m00_axis_rx_aclk : IN STD_LOGIC;
-    m00_axis_rx_aresetn : IN STD_LOGIC;
-    m00_axis_rx_tvalid : OUT STD_LOGIC;
-    m00_axis_rx_tdata : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
-    m00_axis_rx_tready : IN STD_LOGIC;
-    s00_axis_tx_aclk : IN STD_LOGIC;
-    s00_axis_tx_aresetn : IN STD_LOGIC;
-    s00_axis_tx_tready : OUT STD_LOGIC;
-    s00_axis_tx_tdata : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
-    s00_axis_tx_tvalid : IN STD_LOGIC
-  );
-END pak_depak_AXI4Stream_UART_0_0;
-
-ARCHITECTURE pak_depak_AXI4Stream_UART_0_0_arch OF pak_depak_AXI4Stream_UART_0_0 IS
-  ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
-  ATTRIBUTE DowngradeIPIdentifiedWarnings OF pak_depak_AXI4Stream_UART_0_0_arch: ARCHITECTURE IS "yes";
-  COMPONENT AXI4Stream_UART_v1_0 IS
-    GENERIC (
-      UART_BAUD_RATE : INTEGER;
-      UART_CLOCK_FREQUENCY : INTEGER;
-      C_M00_AXIS_RX_TDATA_WIDTH : INTEGER;
-      C_S00_AXIS_TX_TDATA_WIDTH : INTEGER
-    );
-    PORT (
-      clk_uart : IN STD_LOGIC;
-      rst : IN STD_LOGIC;
-      UART_TX : OUT STD_LOGIC;
-      UART_RX : IN STD_LOGIC;
-      m00_axis_rx_aclk : IN STD_LOGIC;
-      m00_axis_rx_aresetn : IN STD_LOGIC;
-      m00_axis_rx_tvalid : OUT STD_LOGIC;
-      m00_axis_rx_tdata : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
-      m00_axis_rx_tready : IN STD_LOGIC;
-      s00_axis_tx_aclk : IN STD_LOGIC;
-      s00_axis_tx_aresetn : IN STD_LOGIC;
-      s00_axis_tx_tready : OUT STD_LOGIC;
-      s00_axis_tx_tdata : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
-      s00_axis_tx_tvalid : IN STD_LOGIC
-    );
-  END COMPONENT AXI4Stream_UART_v1_0;
-  ATTRIBUTE X_CORE_INFO : STRING;
-  ATTRIBUTE X_CORE_INFO OF pak_depak_AXI4Stream_UART_0_0_arch: ARCHITECTURE IS "AXI4Stream_UART_v1_0,Vivado 2020.2";
-  ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
-  ATTRIBUTE CHECK_LICENSE_TYPE OF pak_depak_AXI4Stream_UART_0_0_arch : ARCHITECTURE IS "pak_depak_AXI4Stream_UART_0_0,AXI4Stream_UART_v1_0,{}";
-  ATTRIBUTE X_INTERFACE_INFO : STRING;
-  ATTRIBUTE X_INTERFACE_PARAMETER : STRING;
-  ATTRIBUTE X_INTERFACE_INFO OF s00_axis_tx_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 S00_AXIS_TX TVALID";
-  ATTRIBUTE X_INTERFACE_INFO OF s00_axis_tx_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 S00_AXIS_TX TDATA";
-  ATTRIBUTE X_INTERFACE_PARAMETER OF s00_axis_tx_tready: SIGNAL IS "XIL_INTERFACENAME S00_AXIS_TX, WIZ_DATA_WIDTH 32, TDATA_NUM_BYTES 1, TDEST_WIDTH 0, TID_WIDTH 0, TUSER_WIDTH 0, HAS_TREADY 1, HAS_TSTRB 0, HAS_TKEEP 0, HAS_TLAST 0, FREQ_HZ 100000000, PHASE 0.0, CLK_DOMAIN /clk_wiz_0_clk_out1, LAYERED_METADATA undef, INSERT_VIP 0";
-  ATTRIBUTE X_INTERFACE_INFO OF s00_axis_tx_tready: SIGNAL IS "xilinx.com:interface:axis:1.0 S00_AXIS_TX TREADY";
-  ATTRIBUTE X_INTERFACE_PARAMETER OF s00_axis_tx_aresetn: SIGNAL IS "XIL_INTERFACENAME S00_AXIS_TX_RST, POLARITY ACTIVE_LOW, INSERT_VIP 0";
-  ATTRIBUTE X_INTERFACE_INFO OF s00_axis_tx_aresetn: SIGNAL IS "xilinx.com:signal:reset:1.0 S00_AXIS_TX_RST RST";
-  ATTRIBUTE X_INTERFACE_PARAMETER OF s00_axis_tx_aclk: SIGNAL IS "XIL_INTERFACENAME S00_AXIS_TX_CLK, ASSOCIATED_BUSIF S00_AXIS_TX, ASSOCIATED_RESET s00_axis_tx_aresetn, FREQ_HZ 100000000, FREQ_TOLERANCE_HZ 0, PHASE 0.0, CLK_DOMAIN /clk_wiz_0_clk_out1, INSERT_VIP 0";
-  ATTRIBUTE X_INTERFACE_INFO OF s00_axis_tx_aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 S00_AXIS_TX_CLK CLK";
-  ATTRIBUTE X_INTERFACE_INFO OF m00_axis_rx_tready: SIGNAL IS "xilinx.com:interface:axis:1.0 M00_AXIS_RX TREADY";
-  ATTRIBUTE X_INTERFACE_INFO OF m00_axis_rx_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 M00_AXIS_RX TDATA";
-  ATTRIBUTE X_INTERFACE_PARAMETER OF m00_axis_rx_tvalid: SIGNAL IS "XIL_INTERFACENAME M00_AXIS_RX, WIZ_DATA_WIDTH 32, TDATA_NUM_BYTES 1, TDEST_WIDTH 0, TID_WIDTH 0, TUSER_WIDTH 0, HAS_TREADY 1, HAS_TSTRB 0, HAS_TKEEP 0, HAS_TLAST 0, FREQ_HZ 100000000, PHASE 0.0, CLK_DOMAIN /clk_wiz_0_clk_out1, LAYERED_METADATA undef, INSERT_VIP 0";
-  ATTRIBUTE X_INTERFACE_INFO OF m00_axis_rx_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 M00_AXIS_RX TVALID";
-  ATTRIBUTE X_INTERFACE_PARAMETER OF m00_axis_rx_aresetn: SIGNAL IS "XIL_INTERFACENAME M00_AXIS_RX_RST, POLARITY ACTIVE_LOW, INSERT_VIP 0";
-  ATTRIBUTE X_INTERFACE_INFO OF m00_axis_rx_aresetn: SIGNAL IS "xilinx.com:signal:reset:1.0 M00_AXIS_RX_RST RST";
-  ATTRIBUTE X_INTERFACE_PARAMETER OF m00_axis_rx_aclk: SIGNAL IS "XIL_INTERFACENAME M00_AXIS_RX_CLK, ASSOCIATED_BUSIF M00_AXIS_RX, ASSOCIATED_RESET m00_axis_rx_aresetn, FREQ_HZ 100000000, FREQ_TOLERANCE_HZ 0, PHASE 0.0, CLK_DOMAIN /clk_wiz_0_clk_out1, INSERT_VIP 0";
-  ATTRIBUTE X_INTERFACE_INFO OF m00_axis_rx_aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 M00_AXIS_RX_CLK CLK";
-  ATTRIBUTE X_INTERFACE_INFO OF UART_RX: SIGNAL IS "xilinx.com:interface:uart:1.0 UART RxD";
-  ATTRIBUTE X_INTERFACE_PARAMETER OF UART_TX: SIGNAL IS "XIL_INTERFACENAME UART, BOARD.ASSOCIATED_PARAM UART_BOARD_INTERFACE";
-  ATTRIBUTE X_INTERFACE_INFO OF UART_TX: SIGNAL IS "xilinx.com:interface:uart:1.0 UART TxD";
-  ATTRIBUTE X_INTERFACE_PARAMETER OF rst: SIGNAL IS "XIL_INTERFACENAME reset, POLARITY ACTIVE_HIGH, INSERT_VIP 0";
-  ATTRIBUTE X_INTERFACE_INFO OF rst: SIGNAL IS "xilinx.com:signal:reset:1.0 reset RST";
-  ATTRIBUTE X_INTERFACE_PARAMETER OF clk_uart: SIGNAL IS "XIL_INTERFACENAME ClockUART, ASSOCIATED_BUSIF UART, ASSOCIATED_RESET rst, FREQ_HZ 100000000, FREQ_TOLERANCE_HZ 0, PHASE 0.0, CLK_DOMAIN /clk_wiz_0_clk_out1, INSERT_VIP 0";
-  ATTRIBUTE X_INTERFACE_INFO OF clk_uart: SIGNAL IS "xilinx.com:signal:clock:1.0 ClockUART CLK";
-BEGIN
-  U0 : AXI4Stream_UART_v1_0
-    GENERIC MAP (
-      UART_BAUD_RATE => 115200,
-      UART_CLOCK_FREQUENCY => 100000000,
-      C_M00_AXIS_RX_TDATA_WIDTH => 8,
-      C_S00_AXIS_TX_TDATA_WIDTH => 8
-    )
-    PORT MAP (
-      clk_uart => clk_uart,
-      rst => rst,
-      UART_TX => UART_TX,
-      UART_RX => UART_RX,
-      m00_axis_rx_aclk => m00_axis_rx_aclk,
-      m00_axis_rx_aresetn => m00_axis_rx_aresetn,
-      m00_axis_rx_tvalid => m00_axis_rx_tvalid,
-      m00_axis_rx_tdata => m00_axis_rx_tdata,
-      m00_axis_rx_tready => m00_axis_rx_tready,
-      s00_axis_tx_aclk => s00_axis_tx_aclk,
-      s00_axis_tx_aresetn => s00_axis_tx_aresetn,
-      s00_axis_tx_tready => s00_axis_tx_tready,
-      s00_axis_tx_tdata => s00_axis_tx_tdata,
-      s00_axis_tx_tvalid => s00_axis_tx_tvalid
-    );
-END pak_depak_AXI4Stream_UART_0_0_arch;

LAB2/src/pak_depak/ip/pak_depak_clk_wiz_0_1/pak_depak_clk_wiz_0_1.v

@@ -1,92 +0,0 @@
-
-// file: pak_depak_clk_wiz_0_1.v
-// 
-// (c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved.
-// 
-// This file contains confidential and proprietary information
-// of Xilinx, Inc. and is protected under U.S. and
-// international copyright and other intellectual property
-// laws.
-// 
-// DISCLAIMER
-// This disclaimer is not a license and does not grant any
-// rights to the materials distributed herewith. Except as
-// otherwise provided in a valid license issued to you by
-// Xilinx, and to the maximum extent permitted by applicable
-// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-// (2) Xilinx shall not be liable (whether in contract or tort,
-// including negligence, or under any other theory of
-// liability) for any loss or damage of any kind or nature
-// related to, arising under or in connection with these
-// materials, including for any direct, or any indirect,
-// special, incidental, or consequential loss or damage
-// (including loss of data, profits, goodwill, or any type of
-// loss or damage suffered as a result of any action brought
-// by a third party) even if such damage or loss was
-// reasonably foreseeable or Xilinx had been advised of the
-// possibility of the same.
-// 
-// CRITICAL APPLICATIONS
-// Xilinx products are not designed or intended to be fail-
-// safe, or for use in any application requiring fail-safe
-// performance, such as life-support or safety devices or
-// systems, Class III medical devices, nuclear facilities,
-// applications related to the deployment of airbags, or any
-// other applications that could lead to death, personal
-// injury, or severe property or environmental damage
-// (individually and collectively, "Critical
-// Applications"). Customer assumes the sole risk and
-// liability of any use of Xilinx products in Critical
-// Applications, subject only to applicable laws and
-// regulations governing limitations on product liability.
-// 
-// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-// PART OF THIS FILE AT ALL TIMES.
-// 
-//----------------------------------------------------------------------------
-// User entered comments
-//----------------------------------------------------------------------------
-// None
-//
-//----------------------------------------------------------------------------
-//  Output     Output      Phase    Duty Cycle   Pk-to-Pk     Phase
-//   Clock     Freq (MHz)  (degrees)    (%)     Jitter (ps)  Error (ps)
-//----------------------------------------------------------------------------
-// clk_out1__100.00000______0.000______50.0______130.958_____98.575
-//
-//----------------------------------------------------------------------------
-// Input Clock   Freq (MHz)    Input Jitter (UI)
-//----------------------------------------------------------------------------
-// __primary_________100.000____________0.010
-
-`timescale 1ps/1ps
-
-(* CORE_GENERATION_INFO = "pak_depak_clk_wiz_0_1,clk_wiz_v6_0_6_0_0,{component_name=pak_depak_clk_wiz_0_1,use_phase_alignment=true,use_min_o_jitter=false,use_max_i_jitter=false,use_dyn_phase_shift=false,use_inclk_switchover=false,use_dyn_reconfig=false,enable_axi=0,feedback_source=FDBK_AUTO,PRIMITIVE=MMCM,num_out_clk=1,clkin1_period=10.000,clkin2_period=10.000,use_power_down=false,use_reset=true,use_locked=true,use_inclk_stopped=false,feedback_type=SINGLE,CLOCK_MGR_TYPE=NA,manual_override=false}" *)
-
-module pak_depak_clk_wiz_0_1 
- (
-  // Clock out ports
-  output        clk_out1,
-  // Status and control signals
-  input         reset,
-  output        locked,
- // Clock in ports
-  input         clk_in1
- );
-
-  pak_depak_clk_wiz_0_1_clk_wiz inst
-  (
-  // Clock out ports  
-  .clk_out1(clk_out1),
-  // Status and control signals               
-  .reset(reset), 
-  .locked(locked),
- // Clock in ports
-  .clk_in1(clk_in1)
-  );
-
-endmodule

LAB2/src/pak_depak/ip/pak_depak_clk_wiz_0_1/pak_depak_clk_wiz_0_1_clk_wiz.v

@@ -1,204 +0,0 @@
-
-// file: pak_depak_clk_wiz_0_1.v
-// 
-// (c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved.
-// 
-// This file contains confidential and proprietary information
-// of Xilinx, Inc. and is protected under U.S. and
-// international copyright and other intellectual property
-// laws.
-// 
-// DISCLAIMER
-// This disclaimer is not a license and does not grant any
-// rights to the materials distributed herewith. Except as
-// otherwise provided in a valid license issued to you by
-// Xilinx, and to the maximum extent permitted by applicable
-// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-// (2) Xilinx shall not be liable (whether in contract or tort,
-// including negligence, or under any other theory of
-// liability) for any loss or damage of any kind or nature
-// related to, arising under or in connection with these
-// materials, including for any direct, or any indirect,
-// special, incidental, or consequential loss or damage
-// (including loss of data, profits, goodwill, or any type of
-// loss or damage suffered as a result of any action brought
-// by a third party) even if such damage or loss was
-// reasonably foreseeable or Xilinx had been advised of the
-// possibility of the same.
-// 
-// CRITICAL APPLICATIONS
-// Xilinx products are not designed or intended to be fail-
-// safe, or for use in any application requiring fail-safe
-// performance, such as life-support or safety devices or
-// systems, Class III medical devices, nuclear facilities,
-// applications related to the deployment of airbags, or any
-// other applications that could lead to death, personal
-// injury, or severe property or environmental damage
-// (individually and collectively, "Critical
-// Applications"). Customer assumes the sole risk and
-// liability of any use of Xilinx products in Critical
-// Applications, subject only to applicable laws and
-// regulations governing limitations on product liability.
-// 
-// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-// PART OF THIS FILE AT ALL TIMES.
-// 
-//----------------------------------------------------------------------------
-// User entered comments
-//----------------------------------------------------------------------------
-// None
-//
-//----------------------------------------------------------------------------
-//  Output     Output      Phase    Duty Cycle   Pk-to-Pk     Phase
-//   Clock     Freq (MHz)  (degrees)    (%)     Jitter (ps)  Error (ps)
-//----------------------------------------------------------------------------
-// clk_out1__100.00000______0.000______50.0______130.958_____98.575
-//
-//----------------------------------------------------------------------------
-// Input Clock   Freq (MHz)    Input Jitter (UI)
-//----------------------------------------------------------------------------
-// __primary_________100.000____________0.010
-
-`timescale 1ps/1ps
-
-module pak_depak_clk_wiz_0_1_clk_wiz 
-
- (// Clock in ports
-  // Clock out ports
-  output        clk_out1,
-  // Status and control signals
-  input         reset,
-  output        locked,
-  input         clk_in1
- );
-  // Input buffering
-  //------------------------------------
-wire clk_in1_pak_depak_clk_wiz_0_1;
-wire clk_in2_pak_depak_clk_wiz_0_1;
-  IBUF clkin1_ibufg
-   (.O (clk_in1_pak_depak_clk_wiz_0_1),
-    .I (clk_in1));
-
-
-
-
-  // Clocking PRIMITIVE
-  //------------------------------------
-
-  // Instantiation of the MMCM PRIMITIVE
-  //    * Unused inputs are tied off
-  //    * Unused outputs are labeled unused
-
-  wire        clk_out1_pak_depak_clk_wiz_0_1;
-  wire        clk_out2_pak_depak_clk_wiz_0_1;
-  wire        clk_out3_pak_depak_clk_wiz_0_1;
-  wire        clk_out4_pak_depak_clk_wiz_0_1;
-  wire        clk_out5_pak_depak_clk_wiz_0_1;
-  wire        clk_out6_pak_depak_clk_wiz_0_1;
-  wire        clk_out7_pak_depak_clk_wiz_0_1;
-
-  wire [15:0] do_unused;
-  wire        drdy_unused;
-  wire        psdone_unused;
-  wire        locked_int;
-  wire        clkfbout_pak_depak_clk_wiz_0_1;
-  wire        clkfbout_buf_pak_depak_clk_wiz_0_1;
-  wire        clkfboutb_unused;
-    wire clkout0b_unused;
-   wire clkout1_unused;
-   wire clkout1b_unused;
-   wire clkout2_unused;
-   wire clkout2b_unused;
-   wire clkout3_unused;
-   wire clkout3b_unused;
-   wire clkout4_unused;
-  wire        clkout5_unused;
-  wire        clkout6_unused;
-  wire        clkfbstopped_unused;
-  wire        clkinstopped_unused;
-  wire        reset_high;
-
-  MMCME2_ADV
-  #(.BANDWIDTH            ("OPTIMIZED"),
-    .CLKOUT4_CASCADE      ("FALSE"),
-    .COMPENSATION         ("ZHOLD"),
-    .STARTUP_WAIT         ("FALSE"),
-    .DIVCLK_DIVIDE        (1),
-    .CLKFBOUT_MULT_F      (10.000),
-    .CLKFBOUT_PHASE       (0.000),
-    .CLKFBOUT_USE_FINE_PS ("FALSE"),
-    .CLKOUT0_DIVIDE_F     (10.000),
-    .CLKOUT0_PHASE        (0.000),
-    .CLKOUT0_DUTY_CYCLE   (0.500),
-    .CLKOUT0_USE_FINE_PS  ("FALSE"),
-    .CLKIN1_PERIOD        (10.000))
-  mmcm_adv_inst
-    // Output clocks
-   (
-    .CLKFBOUT            (clkfbout_pak_depak_clk_wiz_0_1),
-    .CLKFBOUTB           (clkfboutb_unused),
-    .CLKOUT0             (clk_out1_pak_depak_clk_wiz_0_1),
-    .CLKOUT0B            (clkout0b_unused),
-    .CLKOUT1             (clkout1_unused),
-    .CLKOUT1B            (clkout1b_unused),
-    .CLKOUT2             (clkout2_unused),
-    .CLKOUT2B            (clkout2b_unused),
-    .CLKOUT3             (clkout3_unused),
-    .CLKOUT3B            (clkout3b_unused),
-    .CLKOUT4             (clkout4_unused),
-    .CLKOUT5             (clkout5_unused),
-    .CLKOUT6             (clkout6_unused),
-     // Input clock control
-    .CLKFBIN             (clkfbout_buf_pak_depak_clk_wiz_0_1),
-    .CLKIN1              (clk_in1_pak_depak_clk_wiz_0_1),
-    .CLKIN2              (1'b0),
-     // Tied to always select the primary input clock
-    .CLKINSEL            (1'b1),
-    // Ports for dynamic reconfiguration
-    .DADDR               (7'h0),
-    .DCLK                (1'b0),
-    .DEN                 (1'b0),
-    .DI                  (16'h0),
-    .DO                  (do_unused),
-    .DRDY                (drdy_unused),
-    .DWE                 (1'b0),
-    // Ports for dynamic phase shift
-    .PSCLK               (1'b0),
-    .PSEN                (1'b0),
-    .PSINCDEC            (1'b0),
-    .PSDONE              (psdone_unused),
-    // Other control and status signals
-    .LOCKED              (locked_int),
-    .CLKINSTOPPED        (clkinstopped_unused),
-    .CLKFBSTOPPED        (clkfbstopped_unused),
-    .PWRDWN              (1'b0),
-    .RST                 (reset_high));
-  assign reset_high = reset; 
-
-  assign locked = locked_int;
-// Clock Monitor clock assigning
-//--------------------------------------
- // Output buffering
-  //-----------------------------------
-
-  BUFG clkf_buf
-   (.O (clkfbout_buf_pak_depak_clk_wiz_0_1),
-    .I (clkfbout_pak_depak_clk_wiz_0_1));
-
-
-
-
-
-
-  BUFG clkout1_buf
-   (.O   (clk_out1),
-    .I   (clk_out1_pak_depak_clk_wiz_0_1));
-
-
-
-
-endmodule

LAB2/src/pak_depak/ip/pak_depak_depacketizer_0_0/pak_depak_depacketizer_0_0.xml

@@ -1,626 +0,0 @@
-<?xml version="1.0" encoding="UTF-8"?>
-<spirit:component xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
-  <spirit:vendor>xilinx.com</spirit:vendor>
-  <spirit:library>customized_ip</spirit:library>
-  <spirit:name>pak_depak_depacketizer_0_0</spirit:name>
-  <spirit:version>1.0</spirit:version>
-  <spirit:busInterfaces>
-    <spirit:busInterface>
-      <spirit:name>m_axis</spirit:name>
-      <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="axis" spirit:version="1.0"/>
-      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="axis_rtl" spirit:version="1.0"/>
-      <spirit:master/>
-      <spirit:portMaps>
-        <spirit:portMap>
-          <spirit:logicalPort>
-            <spirit:name>TDATA</spirit:name>
-          </spirit:logicalPort>
-          <spirit:physicalPort>
-            <spirit:name>m_axis_tdata</spirit:name>
-          </spirit:physicalPort>
-        </spirit:portMap>
-        <spirit:portMap>
-          <spirit:logicalPort>
-            <spirit:name>TLAST</spirit:name>
-          </spirit:logicalPort>
-          <spirit:physicalPort>
-            <spirit:name>m_axis_tlast</spirit:name>
-          </spirit:physicalPort>
-        </spirit:portMap>
-        <spirit:portMap>
-          <spirit:logicalPort>
-            <spirit:name>TVALID</spirit:name>
-          </spirit:logicalPort>
-          <spirit:physicalPort>
-            <spirit:name>m_axis_tvalid</spirit:name>
-          </spirit:physicalPort>
-        </spirit:portMap>
-        <spirit:portMap>
-          <spirit:logicalPort>
-            <spirit:name>TREADY</spirit:name>
-          </spirit:logicalPort>
-          <spirit:physicalPort>
-            <spirit:name>m_axis_tready</spirit:name>
-          </spirit:physicalPort>
-        </spirit:portMap>
-      </spirit:portMaps>
-      <spirit:parameters>
-        <spirit:parameter>
-          <spirit:name>TDATA_NUM_BYTES</spirit:name>
-          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXIS.TDATA_NUM_BYTES">1</spirit:value>
-          <spirit:vendorExtensions>
-            <xilinx:parameterInfo>
-              <xilinx:parameterUsage>none</xilinx:parameterUsage>
-            </xilinx:parameterInfo>
-          </spirit:vendorExtensions>
-        </spirit:parameter>
-        <spirit:parameter>
-          <spirit:name>TDEST_WIDTH</spirit:name>
-          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXIS.TDEST_WIDTH">0</spirit:value>
-          <spirit:vendorExtensions>
-            <xilinx:parameterInfo>
-              <xilinx:parameterUsage>none</xilinx:parameterUsage>
-            </xilinx:parameterInfo>
-          </spirit:vendorExtensions>
-        </spirit:parameter>
-        <spirit:parameter>
-          <spirit:name>TID_WIDTH</spirit:name>
-          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXIS.TID_WIDTH">0</spirit:value>
-          <spirit:vendorExtensions>
-            <xilinx:parameterInfo>
-              <xilinx:parameterUsage>none</xilinx:parameterUsage>
-            </xilinx:parameterInfo>
-          </spirit:vendorExtensions>
-        </spirit:parameter>
-        <spirit:parameter>
-          <spirit:name>TUSER_WIDTH</spirit:name>
-          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXIS.TUSER_WIDTH">0</spirit:value>
-          <spirit:vendorExtensions>
-            <xilinx:parameterInfo>
-              <xilinx:parameterUsage>none</xilinx:parameterUsage>
-            </xilinx:parameterInfo>
-          </spirit:vendorExtensions>
-        </spirit:parameter>
-        <spirit:parameter>
-          <spirit:name>HAS_TREADY</spirit:name>
-          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXIS.HAS_TREADY">1</spirit:value>
-          <spirit:vendorExtensions>
-            <xilinx:parameterInfo>
-              <xilinx:parameterUsage>none</xilinx:parameterUsage>
-            </xilinx:parameterInfo>
-          </spirit:vendorExtensions>
-        </spirit:parameter>
-        <spirit:parameter>
-          <spirit:name>HAS_TSTRB</spirit:name>
-          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXIS.HAS_TSTRB">0</spirit:value>
-          <spirit:vendorExtensions>
-            <xilinx:parameterInfo>
-              <xilinx:parameterUsage>none</xilinx:parameterUsage>
-            </xilinx:parameterInfo>
-          </spirit:vendorExtensions>
-        </spirit:parameter>
-        <spirit:parameter>
-          <spirit:name>HAS_TKEEP</spirit:name>
-          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXIS.HAS_TKEEP">0</spirit:value>
-          <spirit:vendorExtensions>
-            <xilinx:parameterInfo>
-              <xilinx:parameterUsage>none</xilinx:parameterUsage>
-            </xilinx:parameterInfo>
-          </spirit:vendorExtensions>
-        </spirit:parameter>
-        <spirit:parameter>
-          <spirit:name>HAS_TLAST</spirit:name>
-          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXIS.HAS_TLAST">1</spirit:value>
-          <spirit:vendorExtensions>
-            <xilinx:parameterInfo>
-              <xilinx:parameterUsage>none</xilinx:parameterUsage>
-            </xilinx:parameterInfo>
-          </spirit:vendorExtensions>
-        </spirit:parameter>
-        <spirit:parameter>
-          <spirit:name>FREQ_HZ</spirit:name>
-          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXIS.FREQ_HZ">100000000</spirit:value>
-          <spirit:vendorExtensions>
-            <xilinx:parameterInfo>
-              <xilinx:parameterUsage>none</xilinx:parameterUsage>
-            </xilinx:parameterInfo>
-          </spirit:vendorExtensions>
-        </spirit:parameter>
-        <spirit:parameter>
-          <spirit:name>PHASE</spirit:name>
-          <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXIS.PHASE">0.000</spirit:value>
-          <spirit:vendorExtensions>
-            <xilinx:parameterInfo>
-              <xilinx:parameterUsage>none</xilinx:parameterUsage>
-            </xilinx:parameterInfo>
-          </spirit:vendorExtensions>
-        </spirit:parameter>
-        <spirit:parameter>
-          <spirit:name>CLK_DOMAIN</spirit:name>
-          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXIS.CLK_DOMAIN"/>
-          <spirit:vendorExtensions>
-            <xilinx:parameterInfo>
-              <xilinx:parameterUsage>none</xilinx:parameterUsage>
-            </xilinx:parameterInfo>
-          </spirit:vendorExtensions>
-        </spirit:parameter>
-        <spirit:parameter>
-          <spirit:name>LAYERED_METADATA</spirit:name>
-          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXIS.LAYERED_METADATA">undef</spirit:value>
-          <spirit:vendorExtensions>
-            <xilinx:parameterInfo>
-              <xilinx:parameterUsage>none</xilinx:parameterUsage>
-            </xilinx:parameterInfo>
-          </spirit:vendorExtensions>
-        </spirit:parameter>
-        <spirit:parameter>
-          <spirit:name>INSERT_VIP</spirit:name>
-          <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.M_AXIS.INSERT_VIP">0</spirit:value>
-          <spirit:vendorExtensions>
-            <xilinx:parameterInfo>
-              <xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
-            </xilinx:parameterInfo>
-          </spirit:vendorExtensions>
-        </spirit:parameter>
-      </spirit:parameters>
-    </spirit:busInterface>
-    <spirit:busInterface>
-      <spirit:name>s_axis</spirit:name>
-      <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="axis" spirit:version="1.0"/>
-      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="axis_rtl" spirit:version="1.0"/>
-      <spirit:slave/>
-      <spirit:portMaps>
-        <spirit:portMap>
-          <spirit:logicalPort>
-            <spirit:name>TDATA</spirit:name>
-          </spirit:logicalPort>
-          <spirit:physicalPort>
-            <spirit:name>s_axis_tdata</spirit:name>
-          </spirit:physicalPort>
-        </spirit:portMap>
-        <spirit:portMap>
-          <spirit:logicalPort>
-            <spirit:name>TVALID</spirit:name>
-          </spirit:logicalPort>
-          <spirit:physicalPort>
-            <spirit:name>s_axis_tvalid</spirit:name>
-          </spirit:physicalPort>
-        </spirit:portMap>
-        <spirit:portMap>
-          <spirit:logicalPort>
-            <spirit:name>TREADY</spirit:name>
-          </spirit:logicalPort>
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-        </spirit:parameter>
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-          <spirit:name>INSERT_VIP</spirit:name>
-          <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.ARESETN.INSERT_VIP">0</spirit:value>
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-      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock_rtl" spirit:version="1.0"/>
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-      <spirit:portMaps>
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-          <spirit:physicalPort>
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-          <spirit:value spirit:id="BUSIFPARAM_VALUE.CLK.ASSOCIATED_RESET">aresetn</spirit:value>
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-          <spirit:name>FREQ_HZ</spirit:name>
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-          <spirit:vendorExtensions>
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-          <spirit:vendorExtensions>
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-          <spirit:name>CLK_DOMAIN</spirit:name>
-          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.CLK.CLK_DOMAIN"/>
-          <spirit:vendorExtensions>
-            <xilinx:parameterInfo>
-              <xilinx:parameterUsage>none</xilinx:parameterUsage>
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-        </spirit:parameter>
-        <spirit:parameter>
-          <spirit:name>INSERT_VIP</spirit:name>
-          <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.CLK.INSERT_VIP">0</spirit:value>
-          <spirit:vendorExtensions>
-            <xilinx:parameterInfo>
-              <xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
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-    <spirit:ports>
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-        <spirit:name>clk</spirit:name>
-        <spirit:wire>
-          <spirit:direction>in</spirit:direction>
-          <spirit:wireTypeDefs>
-            <spirit:wireTypeDef>
-              <spirit:typeName>STD_LOGIC</spirit:typeName>
-              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
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-          <spirit:direction>in</spirit:direction>
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-        <spirit:name>m_axis_tlast</spirit:name>
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-        <spirit:name>HEADER</spirit:name>
-        <spirit:displayName>Header</spirit:displayName>
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-      <spirit:modelParameter spirit:dataType="INTEGER">
-        <spirit:name>FOOTER</spirit:name>
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-        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.FOOTER">241</spirit:value>
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-    <spirit:parameter>
-      <spirit:name>HEADER</spirit:name>
-      <spirit:displayName>Header</spirit:displayName>
-      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.HEADER">255</spirit:value>
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-      <spirit:name>FOOTER</spirit:name>
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-    <spirit:parameter>
-      <spirit:name>Component_Name</spirit:name>
-      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.Component_Name" spirit:order="1">pak_depak_depacketizer_0_0</spirit:value>
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-    <xilinx:coreExtensions>
-      <xilinx:displayName>depacketizer_v1_0</xilinx:displayName>
-      <xilinx:definitionSource>module_ref</xilinx:definitionSource>
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LAB2/src/pak_depak/ip/pak_depak_packetizer_0_0/pak_depak_packetizer_0_0.xml

@@ -1,649 +0,0 @@
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-          <spirit:physicalPort>
-            <spirit:name>m_axis_tdata</spirit:name>
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-        <spirit:portMap>
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-            <spirit:name>TLAST</spirit:name>
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-          <spirit:physicalPort>
-            <spirit:name>m_axis_tlast</spirit:name>
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-          <spirit:logicalPort>
-            <spirit:name>TVALID</spirit:name>
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-          <spirit:physicalPort>
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-        <spirit:portMap>
-          <spirit:logicalPort>
-            <spirit:name>TREADY</spirit:name>
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-          <spirit:physicalPort>
-            <spirit:name>m_axis_tready</spirit:name>
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-          <spirit:vendorExtensions>
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-          <spirit:name>TDEST_WIDTH</spirit:name>
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-            <xilinx:parameterInfo>
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-        <spirit:parameter>
-          <spirit:name>TID_WIDTH</spirit:name>
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-          <spirit:vendorExtensions>
-            <xilinx:parameterInfo>
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-        <spirit:parameter>
-          <spirit:name>TUSER_WIDTH</spirit:name>
-          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXIS.TUSER_WIDTH">0</spirit:value>
-          <spirit:vendorExtensions>
-            <xilinx:parameterInfo>
-              <xilinx:parameterUsage>none</xilinx:parameterUsage>
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-        <spirit:parameter>
-          <spirit:name>HAS_TREADY</spirit:name>
-          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXIS.HAS_TREADY">1</spirit:value>
-          <spirit:vendorExtensions>
-            <xilinx:parameterInfo>
-              <xilinx:parameterUsage>none</xilinx:parameterUsage>
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-          </spirit:vendorExtensions>
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-        <spirit:parameter>
-          <spirit:name>HAS_TSTRB</spirit:name>
-          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXIS.HAS_TSTRB">0</spirit:value>
-          <spirit:vendorExtensions>
-            <xilinx:parameterInfo>
-              <xilinx:parameterUsage>none</xilinx:parameterUsage>
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-        <spirit:parameter>
-          <spirit:name>HAS_TKEEP</spirit:name>
-          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXIS.HAS_TKEEP">0</spirit:value>
-          <spirit:vendorExtensions>
-            <xilinx:parameterInfo>
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-          <spirit:name>HAS_TLAST</spirit:name>
-          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXIS.HAS_TLAST">1</spirit:value>
-          <spirit:vendorExtensions>
-            <xilinx:parameterInfo>
-              <xilinx:parameterUsage>none</xilinx:parameterUsage>
-            </xilinx:parameterInfo>
-          </spirit:vendorExtensions>
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-        <spirit:parameter>
-          <spirit:name>FREQ_HZ</spirit:name>
-          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXIS.FREQ_HZ">100000000</spirit:value>
-          <spirit:vendorExtensions>
-            <xilinx:parameterInfo>
-              <xilinx:parameterUsage>none</xilinx:parameterUsage>
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-          </spirit:vendorExtensions>
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-        <spirit:parameter>
-          <spirit:name>PHASE</spirit:name>
-          <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXIS.PHASE">0.000</spirit:value>
-          <spirit:vendorExtensions>
-            <xilinx:parameterInfo>
-              <xilinx:parameterUsage>none</xilinx:parameterUsage>
-            </xilinx:parameterInfo>
-          </spirit:vendorExtensions>
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-        <spirit:parameter>
-          <spirit:name>CLK_DOMAIN</spirit:name>
-          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXIS.CLK_DOMAIN"/>
-          <spirit:vendorExtensions>
-            <xilinx:parameterInfo>
-              <xilinx:parameterUsage>none</xilinx:parameterUsage>
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-          </spirit:vendorExtensions>
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-        <spirit:parameter>
-          <spirit:name>LAYERED_METADATA</spirit:name>
-          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXIS.LAYERED_METADATA">undef</spirit:value>
-          <spirit:vendorExtensions>
-            <xilinx:parameterInfo>
-              <xilinx:parameterUsage>none</xilinx:parameterUsage>
-            </xilinx:parameterInfo>
-          </spirit:vendorExtensions>
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-        <spirit:parameter>
-          <spirit:name>INSERT_VIP</spirit:name>
-          <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.M_AXIS.INSERT_VIP">0</spirit:value>
-          <spirit:vendorExtensions>
-            <xilinx:parameterInfo>
-              <xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
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-      <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="axis" spirit:version="1.0"/>
-      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="axis_rtl" spirit:version="1.0"/>
-      <spirit:slave/>
-      <spirit:portMaps>
-        <spirit:portMap>
-          <spirit:logicalPort>
-            <spirit:name>TDATA</spirit:name>
-          </spirit:logicalPort>
-          <spirit:physicalPort>
-            <spirit:name>s_axis_tdata</spirit:name>
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-        <spirit:portMap>
-          <spirit:logicalPort>
-            <spirit:name>TLAST</spirit:name>
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-          <spirit:physicalPort>
-            <spirit:name>s_axis_tlast</spirit:name>
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-        <spirit:portMap>
-          <spirit:logicalPort>
-            <spirit:name>TVALID</spirit:name>
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-          <spirit:physicalPort>
-            <spirit:name>s_axis_tvalid</spirit:name>
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-        <spirit:portMap>
-          <spirit:logicalPort>
-            <spirit:name>TREADY</spirit:name>
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-          <spirit:physicalPort>
-            <spirit:name>s_axis_tready</spirit:name>
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-          <spirit:name>TDATA_NUM_BYTES</spirit:name>
-          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXIS.TDATA_NUM_BYTES">1</spirit:value>
-          <spirit:vendorExtensions>
-            <xilinx:parameterInfo>
-              <xilinx:parameterUsage>none</xilinx:parameterUsage>
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-          </spirit:vendorExtensions>
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-        <spirit:parameter>
-          <spirit:name>TDEST_WIDTH</spirit:name>
-          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXIS.TDEST_WIDTH">0</spirit:value>
-          <spirit:vendorExtensions>
-            <xilinx:parameterInfo>
-              <xilinx:parameterUsage>none</xilinx:parameterUsage>
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-          </spirit:vendorExtensions>
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-        <spirit:parameter>
-          <spirit:name>TID_WIDTH</spirit:name>
-          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXIS.TID_WIDTH">0</spirit:value>
-          <spirit:vendorExtensions>
-            <xilinx:parameterInfo>
-              <xilinx:parameterUsage>none</xilinx:parameterUsage>
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-          </spirit:vendorExtensions>
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-        <spirit:parameter>
-          <spirit:name>TUSER_WIDTH</spirit:name>
-          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXIS.TUSER_WIDTH">0</spirit:value>
-          <spirit:vendorExtensions>
-            <xilinx:parameterInfo>
-              <xilinx:parameterUsage>none</xilinx:parameterUsage>
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-          </spirit:vendorExtensions>
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-        <spirit:parameter>
-          <spirit:name>HAS_TREADY</spirit:name>
-          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXIS.HAS_TREADY">1</spirit:value>
-          <spirit:vendorExtensions>
-            <xilinx:parameterInfo>
-              <xilinx:parameterUsage>none</xilinx:parameterUsage>
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-          </spirit:vendorExtensions>
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-        <spirit:parameter>
-          <spirit:name>HAS_TSTRB</spirit:name>
-          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXIS.HAS_TSTRB">0</spirit:value>
-          <spirit:vendorExtensions>
-            <xilinx:parameterInfo>
-              <xilinx:parameterUsage>none</xilinx:parameterUsage>
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-          </spirit:vendorExtensions>
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-        <spirit:parameter>
-          <spirit:name>HAS_TKEEP</spirit:name>
-          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXIS.HAS_TKEEP">0</spirit:value>
-          <spirit:vendorExtensions>
-            <xilinx:parameterInfo>
-              <xilinx:parameterUsage>none</xilinx:parameterUsage>
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-          </spirit:vendorExtensions>
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-        <spirit:parameter>
-          <spirit:name>HAS_TLAST</spirit:name>
-          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXIS.HAS_TLAST">1</spirit:value>
-          <spirit:vendorExtensions>
-            <xilinx:parameterInfo>
-              <xilinx:parameterUsage>none</xilinx:parameterUsage>
-            </xilinx:parameterInfo>
-          </spirit:vendorExtensions>
-        </spirit:parameter>
-        <spirit:parameter>
-          <spirit:name>FREQ_HZ</spirit:name>
-          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXIS.FREQ_HZ">100000000</spirit:value>
-          <spirit:vendorExtensions>
-            <xilinx:parameterInfo>
-              <xilinx:parameterUsage>none</xilinx:parameterUsage>
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-          </spirit:vendorExtensions>
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-        <spirit:parameter>
-          <spirit:name>PHASE</spirit:name>
-          <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXIS.PHASE">0.000</spirit:value>
-          <spirit:vendorExtensions>
-            <xilinx:parameterInfo>
-              <xilinx:parameterUsage>none</xilinx:parameterUsage>
-            </xilinx:parameterInfo>
-          </spirit:vendorExtensions>
-        </spirit:parameter>
-        <spirit:parameter>
-          <spirit:name>CLK_DOMAIN</spirit:name>
-          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXIS.CLK_DOMAIN"/>
-          <spirit:vendorExtensions>
-            <xilinx:parameterInfo>
-              <xilinx:parameterUsage>none</xilinx:parameterUsage>
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-        <spirit:parameter>
-          <spirit:name>LAYERED_METADATA</spirit:name>
-          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXIS.LAYERED_METADATA">undef</spirit:value>
-          <spirit:vendorExtensions>
-            <xilinx:parameterInfo>
-              <xilinx:parameterUsage>none</xilinx:parameterUsage>
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-          </spirit:vendorExtensions>
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-        <spirit:parameter>
-          <spirit:name>INSERT_VIP</spirit:name>
-          <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.S_AXIS.INSERT_VIP">0</spirit:value>
-          <spirit:vendorExtensions>
-            <xilinx:parameterInfo>
-              <xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
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-    <spirit:busInterface>
-      <spirit:name>aresetn</spirit:name>
-      <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset" spirit:version="1.0"/>
-      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset_rtl" spirit:version="1.0"/>
-      <spirit:slave/>
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-          <spirit:logicalPort>
-            <spirit:name>RST</spirit:name>
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-          <spirit:physicalPort>
-            <spirit:name>aresetn</spirit:name>
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-          <spirit:name>POLARITY</spirit:name>
-          <spirit:value spirit:id="BUSIFPARAM_VALUE.ARESETN.POLARITY" spirit:choiceRef="choice_list_9d8b0d81">ACTIVE_LOW</spirit:value>
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-        <spirit:parameter>
-          <spirit:name>INSERT_VIP</spirit:name>
-          <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.ARESETN.INSERT_VIP">0</spirit:value>
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-      <spirit:name>clk</spirit:name>
-      <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock" spirit:version="1.0"/>
-      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock_rtl" spirit:version="1.0"/>
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-            <spirit:name>CLK</spirit:name>
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-          <spirit:physicalPort>
-            <spirit:name>clk</spirit:name>
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-      <spirit:parameters>
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-          <spirit:name>ASSOCIATED_BUSIF</spirit:name>
-          <spirit:value spirit:id="BUSIFPARAM_VALUE.CLK.ASSOCIATED_BUSIF">m_axis:s_axis</spirit:value>
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-        <spirit:parameter>
-          <spirit:name>ASSOCIATED_RESET</spirit:name>
-          <spirit:value spirit:id="BUSIFPARAM_VALUE.CLK.ASSOCIATED_RESET">aresetn</spirit:value>
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-        <spirit:parameter>
-          <spirit:name>FREQ_HZ</spirit:name>
-          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.CLK.FREQ_HZ">100000000</spirit:value>
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-            <xilinx:parameterInfo>
-              <xilinx:parameterUsage>none</xilinx:parameterUsage>
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-        <spirit:parameter>
-          <spirit:name>FREQ_TOLERANCE_HZ</spirit:name>
-          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.CLK.FREQ_TOLERANCE_HZ">0</spirit:value>
-          <spirit:vendorExtensions>
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-              <xilinx:parameterUsage>none</xilinx:parameterUsage>
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-        <spirit:parameter>
-          <spirit:name>PHASE</spirit:name>
-          <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.CLK.PHASE">0.000</spirit:value>
-          <spirit:vendorExtensions>
-            <xilinx:parameterInfo>
-              <xilinx:parameterUsage>none</xilinx:parameterUsage>
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-        <spirit:parameter>
-          <spirit:name>CLK_DOMAIN</spirit:name>
-          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.CLK.CLK_DOMAIN"/>
-          <spirit:vendorExtensions>
-            <xilinx:parameterInfo>
-              <xilinx:parameterUsage>none</xilinx:parameterUsage>
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-        <spirit:parameter>
-          <spirit:name>INSERT_VIP</spirit:name>
-          <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.CLK.INSERT_VIP">0</spirit:value>
-          <spirit:vendorExtensions>
-            <xilinx:parameterInfo>
-              <xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
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-              <spirit:typeName>STD_LOGIC</spirit:typeName>
-              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
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-      <spirit:port>
-        <spirit:name>aresetn</spirit:name>
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-              <spirit:typeName>STD_LOGIC</spirit:typeName>
-              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
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-      <spirit:port>
-        <spirit:name>s_axis_tdata</spirit:name>
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-              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
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-              <spirit:typeName>STD_LOGIC</spirit:typeName>
-              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
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-      <spirit:port>
-        <spirit:name>s_axis_tready</spirit:name>
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-              <spirit:typeName>STD_LOGIC</spirit:typeName>
-              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
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-              <spirit:typeName>STD_LOGIC</spirit:typeName>
-              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
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-      <spirit:port>
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-              <spirit:typeName>STD_LOGIC_VECTOR</spirit:typeName>
-              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
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-              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
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-              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
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-      <spirit:port>
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-        <spirit:wire>
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LAB2/src/pak_depak/ip/pak_depak_proc_sys_reset_0_0/pak_depak_proc_sys_reset_0_0.xml

@@ -1,900 +0,0 @@
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-            <spirit:name>slowest_sync_clk</spirit:name>
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-          <spirit:name>ASSOCIATED_RESET</spirit:name>
-          <spirit:value spirit:id="BUSIFPARAM_VALUE.CLOCK.ASSOCIATED_RESET">mb_reset:bus_struct_reset:interconnect_aresetn:peripheral_aresetn:peripheral_reset</spirit:value>
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-          <spirit:name>FREQ_HZ</spirit:name>
-          <spirit:displayName>Slowest Sync clock frequency</spirit:displayName>
-          <spirit:description>Slowest Synchronous clock frequency</spirit:description>
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-          <spirit:name>FREQ_TOLERANCE_HZ</spirit:name>
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-          <spirit:name>CLK_DOMAIN</spirit:name>
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-          <spirit:name>INSERT_VIP</spirit:name>
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-      <spirit:name>ext_reset</spirit:name>
-      <spirit:displayName>Ext_Reset</spirit:displayName>
-      <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset" spirit:version="1.0"/>
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-          <spirit:name>BOARD.ASSOCIATED_PARAM</spirit:name>
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-          <spirit:name>INSERT_VIP</spirit:name>
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-      <spirit:displayName>DBG_Reset</spirit:displayName>
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-      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_NUM_PERP_ARESETN" spirit:order="1800" spirit:minimum="1" spirit:maximum="16" spirit:rangeType="long">1</spirit:value>
-    </spirit:parameter>
-    <spirit:parameter>
-      <spirit:name>C_NUM_INTERCONNECT_ARESETN</spirit:name>
-      <spirit:displayName>No. of Interconnect Reset (Active Low)</spirit:displayName>
-      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_NUM_INTERCONNECT_ARESETN" spirit:order="1700" spirit:minimum="1" spirit:maximum="8" spirit:rangeType="long">1</spirit:value>
-    </spirit:parameter>
-    <spirit:parameter>
-      <spirit:name>C_NUM_PERP_RST</spirit:name>
-      <spirit:displayName>No. of Peripheral Reset (Active High)</spirit:displayName>
-      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_NUM_PERP_RST" spirit:order="1600" spirit:minimum="1" spirit:maximum="16" spirit:rangeType="long">1</spirit:value>
-    </spirit:parameter>
-    <spirit:parameter>
-      <spirit:name>C_NUM_BUS_RST</spirit:name>
-      <spirit:displayName>No. of Bus Reset (Active High)</spirit:displayName>
-      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_NUM_BUS_RST" spirit:order="1500" spirit:minimum="1" spirit:maximum="8" spirit:rangeType="long">1</spirit:value>
-    </spirit:parameter>
-    <spirit:parameter>
-      <spirit:name>C_AUX_RESET_HIGH</spirit:name>
-      <spirit:displayName>Aux Reset High</spirit:displayName>
-      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_AUX_RESET_HIGH" spirit:order="1400" spirit:minimum="0" spirit:maximum="1" spirit:rangeType="long">0</spirit:value>
-    </spirit:parameter>
-    <spirit:parameter>
-      <spirit:name>C_EXT_RESET_HIGH</spirit:name>
-      <spirit:displayName>Ext Reset High</spirit:displayName>
-      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_EXT_RESET_HIGH" spirit:order="1300" spirit:minimum="0" spirit:maximum="1" spirit:rangeType="long">1</spirit:value>
-    </spirit:parameter>
-    <spirit:parameter>
-      <spirit:name>C_AUX_RST_WIDTH</spirit:name>
-      <spirit:displayName>Aux Rst Width</spirit:displayName>
-      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_AUX_RST_WIDTH" spirit:order="1200" spirit:minimum="1" spirit:maximum="16" spirit:rangeType="long">4</spirit:value>
-    </spirit:parameter>
-    <spirit:parameter>
-      <spirit:name>C_EXT_RST_WIDTH</spirit:name>
-      <spirit:displayName>Ext Rst Width</spirit:displayName>
-      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_EXT_RST_WIDTH" spirit:order="1100" spirit:minimum="1" spirit:maximum="16" spirit:rangeType="long">4</spirit:value>
-    </spirit:parameter>
-    <spirit:parameter>
-      <spirit:name>Component_Name</spirit:name>
-      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.Component_Name" spirit:order="1">pak_depak_proc_sys_reset_0_0</spirit:value>
-    </spirit:parameter>
-    <spirit:parameter>
-      <spirit:name>USE_BOARD_FLOW</spirit:name>
-      <spirit:displayName>Generate Board based IO Constraints</spirit:displayName>
-      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.USE_BOARD_FLOW" spirit:order="2">true</spirit:value>
-    </spirit:parameter>
-    <spirit:parameter>
-      <spirit:name>RESET_BOARD_INTERFACE</spirit:name>
-      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.RESET_BOARD_INTERFACE" spirit:choiceRef="choice_list_ce26ebdb" spirit:order="3">reset</spirit:value>
-    </spirit:parameter>
-  </spirit:parameters>
-  <spirit:vendorExtensions>
-    <xilinx:coreExtensions>
-      <xilinx:displayName>Processor System Reset</xilinx:displayName>
-      <xilinx:coreRevision>13</xilinx:coreRevision>
-      <xilinx:configElementInfos>
-        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AUX_RESET.POLARITY" xilinx:valueSource="propagated" xilinx:valuePermission="bd"/>
-        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.BUS_STRUCT_RESET.POLARITY" xilinx:valuePermission="bd"/>
-        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.BUS_STRUCT_RESET.TYPE" xilinx:valuePermission="bd"/>
-        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.CLOCK.ASSOCIATED_BUSIF" xilinx:valuePermission="bd"/>
-        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.CLOCK.ASSOCIATED_RESET" xilinx:valuePermission="bd"/>
-        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.CLOCK.CLK_DOMAIN" xilinx:valueSource="ip_propagated" xilinx:valuePermission="bd"/>
-        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.CLOCK.FREQ_HZ" xilinx:valueSource="ip_propagated" xilinx:valuePermission="bd"/>
-        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.CLOCK.FREQ_TOLERANCE_HZ" xilinx:valuePermission="bd"/>
-        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.CLOCK.PHASE" xilinx:valueSource="ip_propagated" xilinx:valuePermission="bd"/>
-        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.DBG_RESET.POLARITY" xilinx:valuePermission="bd"/>
-        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.EXT_RESET.BOARD.ASSOCIATED_PARAM" xilinx:valuePermission="bd"/>
-        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.EXT_RESET.POLARITY" xilinx:valueSource="user_prop" xilinx:valuePermission="bd"/>
-        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.INTERCONNECT_LOW_RST.POLARITY" xilinx:valuePermission="bd"/>
-        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.INTERCONNECT_LOW_RST.TYPE" xilinx:valuePermission="bd"/>
-        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.MB_RST.POLARITY" xilinx:valuePermission="bd"/>
-        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.MB_RST.TYPE" xilinx:valuePermission="bd"/>
-        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.PERIPHERAL_HIGH_RST.POLARITY" xilinx:valuePermission="bd"/>
-        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.PERIPHERAL_HIGH_RST.TYPE" xilinx:valuePermission="bd"/>
-        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.PERIPHERAL_LOW_RST.POLARITY" xilinx:valuePermission="bd"/>
-        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.PERIPHERAL_LOW_RST.TYPE" xilinx:valuePermission="bd"/>
-        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C_AUX_RESET_HIGH" xilinx:valueSource="propagated" xilinx:valuePermission="bd_and_user"/>
-        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C_EXT_RESET_HIGH" xilinx:valuePermission="bd"/>
-        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.RESET_BOARD_INTERFACE" xilinx:valueSource="user"/>
-        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.USE_BOARD_FLOW" xilinx:valueSource="user"/>
-      </xilinx:configElementInfos>
-    </xilinx:coreExtensions>
-    <xilinx:packagingInfo>
-      <xilinx:xilinxVersion>2020.2</xilinx:xilinxVersion>
-      <xilinx:checksum xilinx:scope="busInterfaces" xilinx:value="26169568"/>
-      <xilinx:checksum xilinx:scope="fileGroups" xilinx:value="af82d8e6"/>
-      <xilinx:checksum xilinx:scope="ports" xilinx:value="f2ac9635"/>
-      <xilinx:checksum xilinx:scope="hdlParameters" xilinx:value="404de108"/>
-      <xilinx:checksum xilinx:scope="parameters" xilinx:value="8319b917"/>
-    </xilinx:packagingInfo>
-  </spirit:vendorExtensions>
-</spirit:component>

LAB2/src/pak_depak/ip/pak_depak_proc_sys_reset_0_0/sim/pak_depak_proc_sys_reset_0_0.vhd

@@ -1,147 +0,0 @@
--- (c) Copyright 1995-2025 Xilinx, Inc. All rights reserved.
--- 
--- This file contains confidential and proprietary information
--- of Xilinx, Inc. and is protected under U.S. and
--- international copyright and other intellectual property
--- laws.
--- 
--- DISCLAIMER
--- This disclaimer is not a license and does not grant any
--- rights to the materials distributed herewith. Except as
--- otherwise provided in a valid license issued to you by
--- Xilinx, and to the maximum extent permitted by applicable
--- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
--- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
--- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
--- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
--- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
--- (2) Xilinx shall not be liable (whether in contract or tort,
--- including negligence, or under any other theory of
--- liability) for any loss or damage of any kind or nature
--- related to, arising under or in connection with these
--- materials, including for any direct, or any indirect,
--- special, incidental, or consequential loss or damage
--- (including loss of data, profits, goodwill, or any type of
--- loss or damage suffered as a result of any action brought
--- by a third party) even if such damage or loss was
--- reasonably foreseeable or Xilinx had been advised of the
--- possibility of the same.
--- 
--- CRITICAL APPLICATIONS
--- Xilinx products are not designed or intended to be fail-
--- safe, or for use in any application requiring fail-safe
--- performance, such as life-support or safety devices or
--- systems, Class III medical devices, nuclear facilities,
--- applications related to the deployment of airbags, or any
--- other applications that could lead to death, personal
--- injury, or severe property or environmental damage
--- (individually and collectively, "Critical
--- Applications"). Customer assumes the sole risk and
--- liability of any use of Xilinx products in Critical
--- Applications, subject only to applicable laws and
--- regulations governing limitations on product liability.
--- 
--- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
--- PART OF THIS FILE AT ALL TIMES.
--- 
--- DO NOT MODIFY THIS FILE.
-
--- IP VLNV: xilinx.com:ip:proc_sys_reset:5.0
--- IP Revision: 13
-
-LIBRARY ieee;
-USE ieee.std_logic_1164.ALL;
-USE ieee.numeric_std.ALL;
-
-LIBRARY proc_sys_reset_v5_0_13;
-USE proc_sys_reset_v5_0_13.proc_sys_reset;
-
-ENTITY pak_depak_proc_sys_reset_0_0 IS
-  PORT (
-    slowest_sync_clk : IN STD_LOGIC;
-    ext_reset_in : IN STD_LOGIC;
-    aux_reset_in : IN STD_LOGIC;
-    mb_debug_sys_rst : IN STD_LOGIC;
-    dcm_locked : IN STD_LOGIC;
-    mb_reset : OUT STD_LOGIC;
-    bus_struct_reset : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
-    peripheral_reset : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
-    interconnect_aresetn : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
-    peripheral_aresetn : OUT STD_LOGIC_VECTOR(0 DOWNTO 0)
-  );
-END pak_depak_proc_sys_reset_0_0;
-
-ARCHITECTURE pak_depak_proc_sys_reset_0_0_arch OF pak_depak_proc_sys_reset_0_0 IS
-  ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
-  ATTRIBUTE DowngradeIPIdentifiedWarnings OF pak_depak_proc_sys_reset_0_0_arch: ARCHITECTURE IS "yes";
-  COMPONENT proc_sys_reset IS
-    GENERIC (
-      C_FAMILY : STRING;
-      C_EXT_RST_WIDTH : INTEGER;
-      C_AUX_RST_WIDTH : INTEGER;
-      C_EXT_RESET_HIGH : STD_LOGIC;
-      C_AUX_RESET_HIGH : STD_LOGIC;
-      C_NUM_BUS_RST : INTEGER;
-      C_NUM_PERP_RST : INTEGER;
-      C_NUM_INTERCONNECT_ARESETN : INTEGER;
-      C_NUM_PERP_ARESETN : INTEGER
-    );
-    PORT (
-      slowest_sync_clk : IN STD_LOGIC;
-      ext_reset_in : IN STD_LOGIC;
-      aux_reset_in : IN STD_LOGIC;
-      mb_debug_sys_rst : IN STD_LOGIC;
-      dcm_locked : IN STD_LOGIC;
-      mb_reset : OUT STD_LOGIC;
-      bus_struct_reset : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
-      peripheral_reset : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
-      interconnect_aresetn : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
-      peripheral_aresetn : OUT STD_LOGIC_VECTOR(0 DOWNTO 0)
-    );
-  END COMPONENT proc_sys_reset;
-  ATTRIBUTE X_INTERFACE_INFO : STRING;
-  ATTRIBUTE X_INTERFACE_PARAMETER : STRING;
-  ATTRIBUTE X_INTERFACE_PARAMETER OF peripheral_aresetn: SIGNAL IS "XIL_INTERFACENAME peripheral_low_rst, POLARITY ACTIVE_LOW, TYPE PERIPHERAL, INSERT_VIP 0";
-  ATTRIBUTE X_INTERFACE_INFO OF peripheral_aresetn: SIGNAL IS "xilinx.com:signal:reset:1.0 peripheral_low_rst RST";
-  ATTRIBUTE X_INTERFACE_PARAMETER OF interconnect_aresetn: SIGNAL IS "XIL_INTERFACENAME interconnect_low_rst, POLARITY ACTIVE_LOW, TYPE INTERCONNECT, INSERT_VIP 0";
-  ATTRIBUTE X_INTERFACE_INFO OF interconnect_aresetn: SIGNAL IS "xilinx.com:signal:reset:1.0 interconnect_low_rst RST";
-  ATTRIBUTE X_INTERFACE_PARAMETER OF peripheral_reset: SIGNAL IS "XIL_INTERFACENAME peripheral_high_rst, POLARITY ACTIVE_HIGH, TYPE PERIPHERAL, INSERT_VIP 0";
-  ATTRIBUTE X_INTERFACE_INFO OF peripheral_reset: SIGNAL IS "xilinx.com:signal:reset:1.0 peripheral_high_rst RST";
-  ATTRIBUTE X_INTERFACE_PARAMETER OF bus_struct_reset: SIGNAL IS "XIL_INTERFACENAME bus_struct_reset, POLARITY ACTIVE_HIGH, TYPE INTERCONNECT, INSERT_VIP 0";
-  ATTRIBUTE X_INTERFACE_INFO OF bus_struct_reset: SIGNAL IS "xilinx.com:signal:reset:1.0 bus_struct_reset RST";
-  ATTRIBUTE X_INTERFACE_PARAMETER OF mb_reset: SIGNAL IS "XIL_INTERFACENAME mb_rst, POLARITY ACTIVE_HIGH, TYPE PROCESSOR, INSERT_VIP 0";
-  ATTRIBUTE X_INTERFACE_INFO OF mb_reset: SIGNAL IS "xilinx.com:signal:reset:1.0 mb_rst RST";
-  ATTRIBUTE X_INTERFACE_PARAMETER OF mb_debug_sys_rst: SIGNAL IS "XIL_INTERFACENAME dbg_reset, POLARITY ACTIVE_HIGH, INSERT_VIP 0";
-  ATTRIBUTE X_INTERFACE_INFO OF mb_debug_sys_rst: SIGNAL IS "xilinx.com:signal:reset:1.0 dbg_reset RST";
-  ATTRIBUTE X_INTERFACE_PARAMETER OF aux_reset_in: SIGNAL IS "XIL_INTERFACENAME aux_reset, POLARITY ACTIVE_LOW, INSERT_VIP 0";
-  ATTRIBUTE X_INTERFACE_INFO OF aux_reset_in: SIGNAL IS "xilinx.com:signal:reset:1.0 aux_reset RST";
-  ATTRIBUTE X_INTERFACE_PARAMETER OF ext_reset_in: SIGNAL IS "XIL_INTERFACENAME ext_reset, BOARD.ASSOCIATED_PARAM RESET_BOARD_INTERFACE, POLARITY ACTIVE_HIGH, INSERT_VIP 0";
-  ATTRIBUTE X_INTERFACE_INFO OF ext_reset_in: SIGNAL IS "xilinx.com:signal:reset:1.0 ext_reset RST";
-  ATTRIBUTE X_INTERFACE_PARAMETER OF slowest_sync_clk: SIGNAL IS "XIL_INTERFACENAME clock, ASSOCIATED_RESET mb_reset:bus_struct_reset:interconnect_aresetn:peripheral_aresetn:peripheral_reset, FREQ_HZ 100000000, FREQ_TOLERANCE_HZ 0, PHASE 0.0, CLK_DOMAIN /clk_wiz_0_clk_out1, INSERT_VIP 0";
-  ATTRIBUTE X_INTERFACE_INFO OF slowest_sync_clk: SIGNAL IS "xilinx.com:signal:clock:1.0 clock CLK";
-BEGIN
-  U0 : proc_sys_reset
-    GENERIC MAP (
-      C_FAMILY => "artix7",
-      C_EXT_RST_WIDTH => 4,
-      C_AUX_RST_WIDTH => 4,
-      C_EXT_RESET_HIGH => '1',
-      C_AUX_RESET_HIGH => '0',
-      C_NUM_BUS_RST => 1,
-      C_NUM_PERP_RST => 1,
-      C_NUM_INTERCONNECT_ARESETN => 1,
-      C_NUM_PERP_ARESETN => 1
-    )
-    PORT MAP (
-      slowest_sync_clk => slowest_sync_clk,
-      ext_reset_in => ext_reset_in,
-      aux_reset_in => aux_reset_in,
-      mb_debug_sys_rst => mb_debug_sys_rst,
-      dcm_locked => dcm_locked,
-      mb_reset => mb_reset,
-      bus_struct_reset => bus_struct_reset,
-      peripheral_reset => peripheral_reset,
-      interconnect_aresetn => interconnect_aresetn,
-      peripheral_aresetn => peripheral_aresetn
-    );
-END pak_depak_proc_sys_reset_0_0_arch;

LAB2/src/pak_depak/ip/pak_depak_proc_sys_reset_0_0/synth/pak_depak_proc_sys_reset_0_0.vhd

@@ -1,153 +0,0 @@
--- (c) Copyright 1995-2025 Xilinx, Inc. All rights reserved.
--- 
--- This file contains confidential and proprietary information
--- of Xilinx, Inc. and is protected under U.S. and
--- international copyright and other intellectual property
--- laws.
--- 
--- DISCLAIMER
--- This disclaimer is not a license and does not grant any
--- rights to the materials distributed herewith. Except as
--- otherwise provided in a valid license issued to you by
--- Xilinx, and to the maximum extent permitted by applicable
--- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
--- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
--- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
--- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
--- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
--- (2) Xilinx shall not be liable (whether in contract or tort,
--- including negligence, or under any other theory of
--- liability) for any loss or damage of any kind or nature
--- related to, arising under or in connection with these
--- materials, including for any direct, or any indirect,
--- special, incidental, or consequential loss or damage
--- (including loss of data, profits, goodwill, or any type of
--- loss or damage suffered as a result of any action brought
--- by a third party) even if such damage or loss was
--- reasonably foreseeable or Xilinx had been advised of the
--- possibility of the same.
--- 
--- CRITICAL APPLICATIONS
--- Xilinx products are not designed or intended to be fail-
--- safe, or for use in any application requiring fail-safe
--- performance, such as life-support or safety devices or
--- systems, Class III medical devices, nuclear facilities,
--- applications related to the deployment of airbags, or any
--- other applications that could lead to death, personal
--- injury, or severe property or environmental damage
--- (individually and collectively, "Critical
--- Applications"). Customer assumes the sole risk and
--- liability of any use of Xilinx products in Critical
--- Applications, subject only to applicable laws and
--- regulations governing limitations on product liability.
--- 
--- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
--- PART OF THIS FILE AT ALL TIMES.
--- 
--- DO NOT MODIFY THIS FILE.
-
--- IP VLNV: xilinx.com:ip:proc_sys_reset:5.0
--- IP Revision: 13
-
-LIBRARY ieee;
-USE ieee.std_logic_1164.ALL;
-USE ieee.numeric_std.ALL;
-
-LIBRARY proc_sys_reset_v5_0_13;
-USE proc_sys_reset_v5_0_13.proc_sys_reset;
-
-ENTITY pak_depak_proc_sys_reset_0_0 IS
-  PORT (
-    slowest_sync_clk : IN STD_LOGIC;
-    ext_reset_in : IN STD_LOGIC;
-    aux_reset_in : IN STD_LOGIC;
-    mb_debug_sys_rst : IN STD_LOGIC;
-    dcm_locked : IN STD_LOGIC;
-    mb_reset : OUT STD_LOGIC;
-    bus_struct_reset : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
-    peripheral_reset : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
-    interconnect_aresetn : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
-    peripheral_aresetn : OUT STD_LOGIC_VECTOR(0 DOWNTO 0)
-  );
-END pak_depak_proc_sys_reset_0_0;
-
-ARCHITECTURE pak_depak_proc_sys_reset_0_0_arch OF pak_depak_proc_sys_reset_0_0 IS
-  ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
-  ATTRIBUTE DowngradeIPIdentifiedWarnings OF pak_depak_proc_sys_reset_0_0_arch: ARCHITECTURE IS "yes";
-  COMPONENT proc_sys_reset IS
-    GENERIC (
-      C_FAMILY : STRING;
-      C_EXT_RST_WIDTH : INTEGER;
-      C_AUX_RST_WIDTH : INTEGER;
-      C_EXT_RESET_HIGH : STD_LOGIC;
-      C_AUX_RESET_HIGH : STD_LOGIC;
-      C_NUM_BUS_RST : INTEGER;
-      C_NUM_PERP_RST : INTEGER;
-      C_NUM_INTERCONNECT_ARESETN : INTEGER;
-      C_NUM_PERP_ARESETN : INTEGER
-    );
-    PORT (
-      slowest_sync_clk : IN STD_LOGIC;
-      ext_reset_in : IN STD_LOGIC;
-      aux_reset_in : IN STD_LOGIC;
-      mb_debug_sys_rst : IN STD_LOGIC;
-      dcm_locked : IN STD_LOGIC;
-      mb_reset : OUT STD_LOGIC;
-      bus_struct_reset : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
-      peripheral_reset : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
-      interconnect_aresetn : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
-      peripheral_aresetn : OUT STD_LOGIC_VECTOR(0 DOWNTO 0)
-    );
-  END COMPONENT proc_sys_reset;
-  ATTRIBUTE X_CORE_INFO : STRING;
-  ATTRIBUTE X_CORE_INFO OF pak_depak_proc_sys_reset_0_0_arch: ARCHITECTURE IS "proc_sys_reset,Vivado 2020.2";
-  ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
-  ATTRIBUTE CHECK_LICENSE_TYPE OF pak_depak_proc_sys_reset_0_0_arch : ARCHITECTURE IS "pak_depak_proc_sys_reset_0_0,proc_sys_reset,{}";
-  ATTRIBUTE CORE_GENERATION_INFO : STRING;
-  ATTRIBUTE CORE_GENERATION_INFO OF pak_depak_proc_sys_reset_0_0_arch: ARCHITECTURE IS "pak_depak_proc_sys_reset_0_0,proc_sys_reset,{x_ipProduct=Vivado 2020.2,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=proc_sys_reset,x_ipVersion=5.0,x_ipCoreRevision=13,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED,C_FAMILY=artix7,C_EXT_RST_WIDTH=4,C_AUX_RST_WIDTH=4,C_EXT_RESET_HIGH=1,C_AUX_RESET_HIGH=0,C_NUM_BUS_RST=1,C_NUM_PERP_RST=1,C_NUM_INTERCONNECT_ARESETN=1,C_NUM_PERP_ARESETN=1}";
-  ATTRIBUTE X_INTERFACE_INFO : STRING;
-  ATTRIBUTE X_INTERFACE_PARAMETER : STRING;
-  ATTRIBUTE X_INTERFACE_PARAMETER OF peripheral_aresetn: SIGNAL IS "XIL_INTERFACENAME peripheral_low_rst, POLARITY ACTIVE_LOW, TYPE PERIPHERAL, INSERT_VIP 0";
-  ATTRIBUTE X_INTERFACE_INFO OF peripheral_aresetn: SIGNAL IS "xilinx.com:signal:reset:1.0 peripheral_low_rst RST";
-  ATTRIBUTE X_INTERFACE_PARAMETER OF interconnect_aresetn: SIGNAL IS "XIL_INTERFACENAME interconnect_low_rst, POLARITY ACTIVE_LOW, TYPE INTERCONNECT, INSERT_VIP 0";
-  ATTRIBUTE X_INTERFACE_INFO OF interconnect_aresetn: SIGNAL IS "xilinx.com:signal:reset:1.0 interconnect_low_rst RST";
-  ATTRIBUTE X_INTERFACE_PARAMETER OF peripheral_reset: SIGNAL IS "XIL_INTERFACENAME peripheral_high_rst, POLARITY ACTIVE_HIGH, TYPE PERIPHERAL, INSERT_VIP 0";
-  ATTRIBUTE X_INTERFACE_INFO OF peripheral_reset: SIGNAL IS "xilinx.com:signal:reset:1.0 peripheral_high_rst RST";
-  ATTRIBUTE X_INTERFACE_PARAMETER OF bus_struct_reset: SIGNAL IS "XIL_INTERFACENAME bus_struct_reset, POLARITY ACTIVE_HIGH, TYPE INTERCONNECT, INSERT_VIP 0";
-  ATTRIBUTE X_INTERFACE_INFO OF bus_struct_reset: SIGNAL IS "xilinx.com:signal:reset:1.0 bus_struct_reset RST";
-  ATTRIBUTE X_INTERFACE_PARAMETER OF mb_reset: SIGNAL IS "XIL_INTERFACENAME mb_rst, POLARITY ACTIVE_HIGH, TYPE PROCESSOR, INSERT_VIP 0";
-  ATTRIBUTE X_INTERFACE_INFO OF mb_reset: SIGNAL IS "xilinx.com:signal:reset:1.0 mb_rst RST";
-  ATTRIBUTE X_INTERFACE_PARAMETER OF mb_debug_sys_rst: SIGNAL IS "XIL_INTERFACENAME dbg_reset, POLARITY ACTIVE_HIGH, INSERT_VIP 0";
-  ATTRIBUTE X_INTERFACE_INFO OF mb_debug_sys_rst: SIGNAL IS "xilinx.com:signal:reset:1.0 dbg_reset RST";
-  ATTRIBUTE X_INTERFACE_PARAMETER OF aux_reset_in: SIGNAL IS "XIL_INTERFACENAME aux_reset, POLARITY ACTIVE_LOW, INSERT_VIP 0";
-  ATTRIBUTE X_INTERFACE_INFO OF aux_reset_in: SIGNAL IS "xilinx.com:signal:reset:1.0 aux_reset RST";
-  ATTRIBUTE X_INTERFACE_PARAMETER OF ext_reset_in: SIGNAL IS "XIL_INTERFACENAME ext_reset, BOARD.ASSOCIATED_PARAM RESET_BOARD_INTERFACE, POLARITY ACTIVE_HIGH, INSERT_VIP 0";
-  ATTRIBUTE X_INTERFACE_INFO OF ext_reset_in: SIGNAL IS "xilinx.com:signal:reset:1.0 ext_reset RST";
-  ATTRIBUTE X_INTERFACE_PARAMETER OF slowest_sync_clk: SIGNAL IS "XIL_INTERFACENAME clock, ASSOCIATED_RESET mb_reset:bus_struct_reset:interconnect_aresetn:peripheral_aresetn:peripheral_reset, FREQ_HZ 100000000, FREQ_TOLERANCE_HZ 0, PHASE 0.0, CLK_DOMAIN /clk_wiz_0_clk_out1, INSERT_VIP 0";
-  ATTRIBUTE X_INTERFACE_INFO OF slowest_sync_clk: SIGNAL IS "xilinx.com:signal:clock:1.0 clock CLK";
-BEGIN
-  U0 : proc_sys_reset
-    GENERIC MAP (
-      C_FAMILY => "artix7",
-      C_EXT_RST_WIDTH => 4,
-      C_AUX_RST_WIDTH => 4,
-      C_EXT_RESET_HIGH => '1',
-      C_AUX_RESET_HIGH => '0',
-      C_NUM_BUS_RST => 1,
-      C_NUM_PERP_RST => 1,
-      C_NUM_INTERCONNECT_ARESETN => 1,
-      C_NUM_PERP_ARESETN => 1
-    )
-    PORT MAP (
-      slowest_sync_clk => slowest_sync_clk,
-      ext_reset_in => ext_reset_in,
-      aux_reset_in => aux_reset_in,
-      mb_debug_sys_rst => mb_debug_sys_rst,
-      dcm_locked => dcm_locked,
-      mb_reset => mb_reset,
-      bus_struct_reset => bus_struct_reset,
-      peripheral_reset => peripheral_reset,
-      interconnect_aresetn => interconnect_aresetn,
-      peripheral_aresetn => peripheral_aresetn
-    );
-END pak_depak_proc_sys_reset_0_0_arch;

LAB2/src/pak_depak/ipshared/453d/hdl/AXI4Stream_UART_v1_0.vhd

@@ -1,398 +0,0 @@
-							-------------------------------------------------------------------------------------------------
-							-------------------------------------------------------------------------------------------------
-							-------------------------------------------------------------------------------------------------
-							----  *   )                                                                                  ----
-							----` )  /( (      )      (    (           (  (  (            (    (   (   (          (  (   ----
-							---- ( )(_)))\    (      ))\   )\    (     )\))( )\   (      ))\  ))\  )(  )\   (     )\))(  ----
-							----(_(_())((_)   )\  ' /((_) ((_)   )\ ) ((_))\((_)  )\ )  /((_)/((_)(()\((_)  )\ ) ((_))\  ----
-							----|_   _| (_) _((_)) (_))   | __| _(_/(  (()(_)(_) _(_/( (_)) (_))   ((_)(_) _(_/(  (()(_) ----
-							----  | |   | || '  \()/ -_)  | _| | ' \))/ _` | | || ' \))/ -_)/ -_) | '_|| || ' \))/ _` |  ----
-							----  |_|   |_||_|_|_| \___|  |___||_||_| \__, | |_||_||_| \___|\___| |_|  |_||_||_| \__, |  ----
-							----                                      |___/                                      |___/   ----
-							-------------------------------------------------------------------------------------------------
-							-------------------------------------------------------------------------------------------------
-							-------------------------------------------------------------------------------------------------
-
-------------------------------------------------------------------------------------------------------------------------------------------
-------------------------------------------------------------------------------------------------------------------------------------------
-------------------------------------------------------------------------------------------------------------------------------------------
-----           _____     _                      ___             __ _     _                                       _              __ _  ----
-----    o O O |_   _|   (_)    _ __     ___    | __|   _ _     / _` |   (_)    _ _      ___     ___      _ _    (_)    _ _     / _` | ----
-----   o        | |     | |   | '  \   / -_)   | _|   | ' \    \__, |   | |   | ' \    / -_)   / -_)    | '_|   | |   | ' \    \__, | ----
-----  TS__[O]  _|_|_   _|_|_  |_|_|_|  \___|   |___|  |_||_|   |___/   _|_|_  |_||_|   \___|   \___|   _|_|_   _|_|_  |_||_|   |___/  ----
----- {======|_|"""""|_|"""""|_|"""""|_|"""""|_|"""""|_|"""""|_|"""""|_|"""""|_|"""""|_|"""""|_|"""""|_|"""""|_|"""""|_|"""""|_|"""""| ----
-----./o--000'"`-0-0-'"`-0-0-'"`-0-0-'"`-0-0-'"`-0-0-'"`-0-0-'"`-0-0-'"`-0-0-'"`-0-0-'"`-0-0-'"`-0-0-'"`-0-0-'"`-0-0-'"`-0-0-'"`-0-0-' ----
-------------------------------------------------------------------------------------------------------------------------------------------
-------------------------------------------------------------------------------------------------------------------------------------------
-------------------------------------------------------------------------------------------------------------------------------------------
-
--------------------------------------DESCRIPTION------------------------------------------
-------------------------------------------------------------------------------------------
--- Bridge FT245Async to AXI4-Stream. 													--
-------------------------------------------------------------------------------------------
-------------------------------------------------------------------------------------------
-
-library ieee;
-	use ieee.std_logic_1164.all;
-	use ieee.numeric_std.all;
-
-library xpm;
-	use xpm.vcomponents.all;
-
-entity AXI4Stream_UART_v1_0 is
-	generic (
-		------------------UART PARAMETER-------------------
-		UART_BAUD_RATE           : positive := 115_200;
-		UART_CLOCK_FREQUENCY     : positive := 100_000_000;	--The associated clock frequency
-		----------------------------------------------------
-
-		-- Parameters of Axi Master Bus Interface M00_AXIS_RX
-		C_M00_AXIS_RX_TDATA_WIDTH	: integer	:= 8;
-		-- Parameters of Axi Slave Bus Interface S00_AXIS_TX
-		C_S00_AXIS_TX_TDATA_WIDTH	: integer	:= 8
-	);
-	port (
-		---------Global---------
-		clk_uart 	: IN  	STD_LOGIC;
-		rst 		: IN	STD_LOGIC;
-		------------------------
-
-		---------Connessioni comunicazione UART-----------
-		UART_TX  : OUT STD_LOGIC;
-		UART_RX  : IN  STD_LOGIC;
-		---------------------------------------------------
-
-		---Ports of Axi Master Bus Interface M00_AXIS_RX---
-		m00_axis_rx_aclk	: IN  	STD_LOGIC;
-		m00_axis_rx_aresetn	: IN  	STD_LOGIC;
-		m00_axis_rx_tvalid	: OUT  	STD_LOGIC;
-		m00_axis_rx_tdata	: OUT 	STD_LOGIC_VECTOR(C_M00_AXIS_RX_TDATA_WIDTH-1 DOWNTO 0);
-		m00_axis_rx_tready	: IN  	STD_LOGIC;
-		--------------------------------------------------
-		---Ports of Axi Slave Bus Interface S00_AXIS_TX---
-		s00_axis_tx_aclk	: IN  	STD_LOGIC;
-		s00_axis_tx_aresetn	: IN  	STD_LOGIC;
-		s00_axis_tx_tready	: OUT  	STD_LOGIC;
-		s00_axis_tx_tdata	: IN	STD_LOGIC_VECTOR(C_S00_AXIS_TX_TDATA_WIDTH-1 DOWNTO 0);
-		s00_axis_tx_tvalid	: IN  	STD_LOGIC
-		--------------------------------------------------
-	);
-end AXI4Stream_UART_v1_0;
-
-architecture arch_imp of AXI4Stream_UART_v1_0 is
-
-	--------------------------------COMPONENTS DECLARATION-----------------------------------
-	component UART_Manager is
-		generic(
-			UART_BAUD_RATE           : positive;
-			UART_CLOCK_FREQUENCY     : positive	--The associated clock frequency
-		);
-		Port (
-			---------Global---------
-			clk_uart 	: IN  STD_LOGIC;
-			reset 		: IN  STD_LOGIC;
-			------------------------
-
-			---------Connessioni comunicazione UART-----------
-			UART_TX  : OUT STD_LOGIC;
-			UART_RX  : IN  STD_LOGIC;
-			---------------------------------------------------
-
-			------------FIFO_DATA_RX (8bit)-------------
-			FIFO_DATA_RX_rst 			: OUT 	STD_LOGIC;
-			FIFO_DATA_RX_clk 			: OUT 	STD_LOGIC;
-			FIFO_DATA_RX_din 			: OUT 	STD_LOGIC_VECTOR(8-1 DOWNTO 0);
-			FIFO_DATA_RX_wr_en 			: OUT 	STD_LOGIC;
-			FIFO_DATA_RX_full			: IN 	STD_LOGIC;
-			FIFO_DATA_RX_almost_full 	: IN 	STD_LOGIC;
-			--------------------------------------------
-
-			------------FIFO_DATA_TX (8bit)-------------
-			--FIFO_DATA_RX_rst 			: OUT 	STD_LOGIC;
-			FIFO_DATA_TX_clk 			: OUT 	STD_LOGIC;
-			FIFO_DATA_TX_dout 			: IN 	STD_LOGIC_VECTOR(8-1 DOWNTO 0);
-			FIFO_DATA_TX_rd_en 			: OUT 	STD_LOGIC;
-			FIFO_DATA_TX_empty			: IN 	STD_LOGIC;
-			FIFO_DATA_TX_almost_empty 	: IN 	STD_LOGIC
-			--------------------------------------------
-		);
-	end component UART_Manager;
-
-	component AXI4Stream_UART_v1_0_M00_AXIS_RX is
-		generic (
-			-- Width of S_AXIS address bus. The slave accepts the read and write addresses of width C_M_AXIS_TDATA_WIDTH.
-			C_M_AXIS_TDATA_WIDTH	: integer	:= 8
-		);
-		port (
-			--------------FIFO_DATA (8bit)--------------
-			--FIFO_DATA_rst 				: OUT 	STD_LOGIC; Reset lo da chi scrive la FIFO
-			FIFO_DATA_clk 				: OUT 	STD_LOGIC;
-			FIFO_DATA_dout 				: IN 	STD_LOGIC_VECTOR(8-1 DOWNTO 0);
-			FIFO_DATA_rd_en 			: OUT 	STD_LOGIC;
-			FIFO_DATA_empty				: IN 	STD_LOGIC;
-			FIFO_DATA_almost_empty 		: IN 	STD_LOGIC;
-			--------------------------------------------
-
-			----------------AXI4-Stream-----------------
-			-- AXI4Stream Clock
-			M_AXIS_ACLK		: IN 	STD_LOGIC;
-			-- AXI4Stream Reset
-			M_AXIS_ARESETN	: IN 	STD_LOGIC;
-			-- Master Stream Ports. TVALID indicates that the master is driving a valid transfer, A transfer takes place when both TVALID and TREADY are asserted.
-			M_AXIS_TVALID	: OUT 	STD_LOGIC;
-			-- TDATA is the primary payload that is used to provide the data that is passing across the interface from the master.
-			M_AXIS_TDATA	: OUT 	STD_LOGIC_VECTOR(C_M_AXIS_TDATA_WIDTH-1 DOWNTO 0);
-			-- TREADY indicates that the slave can accept a transfer in the current cycle.
-			M_AXIS_TREADY	: IN 	STD_LOGIC
-			--------------------------------------------
-		);
-	end component AXI4Stream_UART_v1_0_M00_AXIS_RX;
-
-	component AXI4Stream_UART_v1_0_S00_AXIS_TX is
-		generic (
-			-- AXI4Stream sink: Data Width
-			C_S_AXIS_TDATA_WIDTH	: integer	:= 8
-		);
-		port (
-
-			--------------FIFO_DATA-------------
-			FIFO_DATA_rst 				: OUT 	STD_LOGIC;
-			FIFO_DATA_clk 				: OUT 	STD_LOGIC;
-			FIFO_DATA_din 				: OUT 	STD_LOGIC_VECTOR(C_S_AXIS_TDATA_WIDTH-1 DOWNTO 0);
-			FIFO_DATA_wr_en 			: OUT 	STD_LOGIC;
-			FIFO_DATA_full 				: IN 	STD_LOGIC;
-			FIFO_DATA_almost_full 		: IN 	STD_LOGIC;
-			--------------------------------------------
-
-			----------------AXI4-Stream-----------------
-			-- AXI4Stream sink: Clock
-			S_AXIS_ACLK		: IN 	STD_LOGIC;
-			-- AXI4Stream sink: Reset
-			S_AXIS_ARESETN	: IN 	STD_LOGIC;
-			-- Ready to accept data in
-			S_AXIS_TREADY	: OUT 	STD_LOGIC;
-			-- Data in
-			S_AXIS_TDATA	: IN 	STD_LOGIC_VECTOR(C_S_AXIS_TDATA_WIDTH-1 DOWNTO 0);
-			-- Data is in valid
-			S_AXIS_TVALID	: IN 	STD_LOGIC
-			--------------------------------------------
-		);
-	end component AXI4Stream_UART_v1_0_S00_AXIS_TX;
-	-----------------------------------------------------------------------------------------
-
-	---------------------------------------SIGNALS-------------------------------------------
-	-----------------FIFO_DATA_RX-----------------
-	signal FIFO_DATA_RX_rst 			: STD_LOGIC;
-    signal FIFO_DATA_RX_wr_clk 			: STD_LOGIC;
-    signal FIFO_DATA_RX_rd_clk 			: STD_LOGIC;
-	signal FIFO_DATA_RX_din 			: STD_LOGIC_VECTOR(7 DOWNTO 0);
-    signal FIFO_DATA_RX_wr_en 			: STD_LOGIC;
-    signal FIFO_DATA_RX_rd_en 			: STD_LOGIC;
-    signal FIFO_DATA_RX_dout 			: STD_LOGIC_VECTOR(7 DOWNTO 0);
-    signal FIFO_DATA_RX_full 			: STD_LOGIC;
-    signal FIFO_DATA_RX_almost_full 	: STD_LOGIC;
-    signal FIFO_DATA_RX_empty 			: STD_LOGIC;
-    signal FIFO_DATA_RX_almost_empty 	: STD_LOGIC;
-	----------------------------------------------
-
-	-----------------FIFO_DATA_TX-----------------
-	signal FIFO_DATA_TX_rst 			: STD_LOGIC;
-    signal FIFO_DATA_TX_wr_clk 			: STD_LOGIC;
-    signal FIFO_DATA_TX_rd_clk 			: STD_LOGIC;
-	signal FIFO_DATA_TX_din 			: STD_LOGIC_VECTOR(7 DOWNTO 0);
-    signal FIFO_DATA_TX_wr_en 			: STD_LOGIC;
-    signal FIFO_DATA_TX_rd_en 			: STD_LOGIC;
-    signal FIFO_DATA_TX_dout 			: STD_LOGIC_VECTOR(7 DOWNTO 0);
-    signal FIFO_DATA_TX_full 			: STD_LOGIC;
-    signal FIFO_DATA_TX_almost_full 	: STD_LOGIC;
-    signal FIFO_DATA_TX_empty 			: STD_LOGIC;
-    signal FIFO_DATA_TX_almost_empty 	: STD_LOGIC;
-	----------------------------------------------
-
-	-----------------------------------------------------------------------------------------
-
-begin
-
-	-----------------------MODULE INSTANTIATION-------------------------
-	AXI4Stream_UART_v1_0_S00_AXIS_TX_inst : AXI4Stream_UART_v1_0_S00_AXIS_TX
-		generic map(
-			-- AXI4Stream sink: Data Width
-			C_S_AXIS_TDATA_WIDTH		=> C_S00_AXIS_TX_TDATA_WIDTH
-		)
-		port map(
-
-			--------------FIFO_DATA-------------
-			FIFO_DATA_rst 				=> FIFO_DATA_TX_rst,
-			FIFO_DATA_clk 				=> FIFO_DATA_TX_wr_clk,
-			FIFO_DATA_din 				=> FIFO_DATA_TX_din,
-			FIFO_DATA_wr_en 			=> FIFO_DATA_TX_wr_en,
-			FIFO_DATA_full 				=> FIFO_DATA_TX_full,
-			FIFO_DATA_almost_full 		=> FIFO_DATA_TX_almost_full,
-			--------------------------------------------
-
-			----------------AXI4-Stream-----------------
-			-- AXI4Stream sink: Clock
-			S_AXIS_ACLK		=> s00_axis_tx_aclk,
-			-- AXI4Stream sink: Reset
-			S_AXIS_ARESETN	=> s00_axis_tx_aresetn,
-			-- Ready to accept data in
-			S_AXIS_TREADY	=> s00_axis_tx_tready,
-			-- Data in
-			S_AXIS_TDATA	=> s00_axis_tx_tdata,
-			-- Data is in valid
-			S_AXIS_TVALID	=> s00_axis_tx_tvalid
-			--------------------------------------------
-		);
-
-	-- xpm_fifo_async: Asynchronous FIFO
-	-- Xilinx Parameterized Macro, Version 2017.3
-	FIFO_DATA_TX : xpm_fifo_async
-		generic map (
-			FIFO_MEMORY_TYPE		=> "block",		--string; "auto", "block", "distributed", or "ultra";
-			FIFO_WRITE_DEPTH		=> 2048,		--positive integer;
-			RELATED_CLOCKS			=> 0,			--positive integer; 0 or 1;
-			WRITE_DATA_WIDTH		=> 8,			--positive integer;
-			WR_DATA_COUNT_WIDTH		=> 1,			--positive integer;
-			READ_MODE				=> "fwft",		--string; "std" or "fwft";
-			FIFO_READ_LATENCY		=> 0,			--positive integer;
-			--FULL_RESET_VALUE		=> 0,			--positive integer; 0 or 1;
-			READ_DATA_WIDTH			=> 8,			--positive integer;
-			RD_DATA_COUNT_WIDTH		=> 1,			--positive integer;
-			CDC_SYNC_STAGES			=> 2,			--positive integer;
-			ECC_MODE				=> "no_ecc",	--string; "no_ecc" or "en_ecc";
-			--PROG_FULL_THRESH		=> 10,			--positive integer
-			--PROG_EMPTY_THRESH		=> 10,			--positive integer
-			--DOUT_RESET_VALUE		=> "0",			--string
-			WAKEUP_TIME				=> 0,			--positive integer; 0 or 2;
-			USE_ADV_FEATURES		=> "0808"		--string; "0000" to "1F1F"; 0808 = almost_full and almost_empty
-		)
-		port map (
-			wr_clk 			=> FIFO_DATA_TX_wr_clk,
-			wr_en 			=> FIFO_DATA_TX_wr_en,
-			din 			=> FIFO_DATA_TX_din,
-			full 			=> FIFO_DATA_TX_full,
-			overflow		=> open,
-			wr_rst_busy		=> open,
-			sleep			=> '0',
-			rst				=> FIFO_DATA_TX_rst,
-			rd_clk 			=> FIFO_DATA_TX_rd_clk,
-			rd_en 			=> FIFO_DATA_TX_rd_en,
-			dout 			=> FIFO_DATA_TX_dout,
-			empty 			=> FIFO_DATA_TX_empty,
-			underflow		=> open,
-			rd_rst_busy		=> open,
-			injectsbiterr	=> '0',
-			injectdbiterr	=> '0',
-			almost_full 	=> FIFO_DATA_TX_almost_full,
-			almost_empty 	=> FIFO_DATA_TX_almost_empty
-		);
-
-	UART_Manager_inst : UART_Manager
-		Generic map(
-			UART_BAUD_RATE			=> UART_BAUD_RATE,
-			UART_CLOCK_FREQUENCY	=> UART_CLOCK_FREQUENCY
-		)
-		Port map(
-			---------Global---------
-			clk_uart 	=> clk_uart,
-			reset 		=> rst,
-			------------------------
-
-			---------Connessioni comunicazione UART-----------
-			UART_TX 	=> UART_TX,
-			UART_RX 	=> UART_RX,
-			---------------------------------------------------
-
-			------------FIFO_DATA_RX (8bit)-------------
-			FIFO_DATA_RX_rst 			=> FIFO_DATA_RX_rst,
-			FIFO_DATA_RX_clk 			=> FIFO_DATA_RX_wr_clk,
-			FIFO_DATA_RX_din 			=> FIFO_DATA_RX_din,
-			FIFO_DATA_RX_wr_en 			=> FIFO_DATA_RX_wr_en,
-			FIFO_DATA_RX_full			=> FIFO_DATA_RX_full,
-			FIFO_DATA_RX_almost_full 	=> FIFO_DATA_RX_almost_full,
-			--------------------------------------------
-
-			------------FIFO_DATA_TX (8bit)-------------
-			FIFO_DATA_TX_clk 			=> FIFO_DATA_TX_rd_clk,
-			FIFO_DATA_TX_dout 			=> FIFO_DATA_TX_dout,
-			FIFO_DATA_TX_rd_en 			=> FIFO_DATA_TX_rd_en,
-			FIFO_DATA_TX_empty			=> FIFO_DATA_TX_empty,
-			FIFO_DATA_TX_almost_empty 	=> FIFO_DATA_TX_almost_empty
-			--------------------------------------------
-		);
-
-	-- xpm_fifo_async: Asynchronous FIFO
-	-- Xilinx Parameterized Macro, Version 2017.3
-	FIFO_DATA_RX : xpm_fifo_async
-		generic map (
-			FIFO_MEMORY_TYPE		=> "block",		--string; "auto", "block", "distributed", or "ultra";
-			FIFO_WRITE_DEPTH		=> 2048,		--positive integer;
-			RELATED_CLOCKS			=> 0,			--positive integer; 0 or 1;
-			WRITE_DATA_WIDTH		=> 8,			--positive integer;
-			WR_DATA_COUNT_WIDTH		=> 1,			--positive integer;
-			READ_MODE				=> "fwft",		--string; "std" or "fwft";
-			FIFO_READ_LATENCY		=> 0,			--positive integer;
-			--FULL_RESET_VALUE		=> 0,			--positive integer; 0 or 1;
-			READ_DATA_WIDTH			=> 8,			--positive integer;
-			RD_DATA_COUNT_WIDTH		=> 1,			--positive integer;
-			CDC_SYNC_STAGES			=> 2,			--positive integer;
-			ECC_MODE				=> "no_ecc",	--string; "no_ecc" or "en_ecc";
-			--PROG_FULL_THRESH		=> 10,			--positive integer
-			--PROG_EMPTY_THRESH		=> 10,			--positive integer
-			--DOUT_RESET_VALUE		=> "0",			--string
-			WAKEUP_TIME				=> 0,			--positive integer; 0 or 2;
-			USE_ADV_FEATURES		=> "0808"		--string; "0000" to "1F1F"; 0808 = almost_full and almost_empty
-		)
-		port map (
-			wr_clk 			=> FIFO_DATA_RX_wr_clk,
-			wr_en 			=> FIFO_DATA_RX_wr_en,
-			din 			=> FIFO_DATA_RX_din,
-			full 			=> FIFO_DATA_RX_full,
-			overflow		=> open,
-			wr_rst_busy		=> open,
-			sleep			=> '0',
-			rst				=> FIFO_DATA_RX_rst,
-			rd_clk 			=> FIFO_DATA_RX_rd_clk,
-			rd_en 			=> FIFO_DATA_RX_rd_en,
-			dout 			=> FIFO_DATA_RX_dout,
-			empty 			=> FIFO_DATA_RX_empty,
-			underflow		=> open,
-			rd_rst_busy		=> open,
-			injectsbiterr	=> '0',
-			injectdbiterr	=> '0',
-			almost_full 	=> FIFO_DATA_RX_almost_full,
-			almost_empty 	=> FIFO_DATA_RX_almost_empty
-		);
-
-	AXI4Stream_UART_v1_0_M00_AXIS_RX_inst : AXI4Stream_UART_v1_0_M00_AXIS_RX
-		generic map(
-			-- Width of S_AXIS address bus. The slave accepts the read and write addresses of width C_M_AXIS_TDATA_WIDTH.
-			C_M_AXIS_TDATA_WIDTH	=> C_M00_AXIS_RX_TDATA_WIDTH
-
-		)
-		port map(
-			--------------FIFO_DATA (8bit)--------------
-			FIFO_DATA_clk 			=> FIFO_DATA_RX_rd_clk,
-			FIFO_DATA_dout 			=> FIFO_DATA_RX_dout,
-			FIFO_DATA_rd_en 		=> FIFO_DATA_RX_rd_en,
-			FIFO_DATA_empty			=> FIFO_DATA_RX_empty,
-			FIFO_DATA_almost_empty 	=> FIFO_DATA_RX_almost_empty,
-			--------------------------------------------
-
-			----------------AXI4-Stream-----------------
-			-- AXI4Stream Clock
-			M_AXIS_ACLK		=> m00_axis_rx_aclk,
-			-- AXI4Stream Reset
-			M_AXIS_ARESETN	=> m00_axis_rx_aresetn,
-			-- Master Stream Ports. TVALID indicates that the master is driving a valid transfer, A transfer takes place when both TVALID and TREADY are asserted.
-			M_AXIS_TVALID	=> m00_axis_rx_tvalid,
-			-- TDATA is the primary payload that is used to provide the data that is passing across the interface from the master.
-			M_AXIS_TDATA	=> m00_axis_rx_tdata,
-			-- TREADY indicates that the slave can accept a transfer in the current cycle.
-			M_AXIS_TREADY	=> m00_axis_rx_tready
-			--------------------------------------------
-		);
-
-	--------------------------------------------------------------------
-
-end arch_imp;

LAB2/src/pak_depak/ipshared/453d/hdl/AXI4Stream_UART_v1_0_M00_AXIS_RX.vhd

@@ -1,91 +0,0 @@
-							-------------------------------------------------------------------------------------------------
-							-------------------------------------------------------------------------------------------------
-							-------------------------------------------------------------------------------------------------
-							----  *   )                                                                                  ----
-							----` )  /( (      )      (    (           (  (  (            (    (   (   (          (  (   ----
-							---- ( )(_)))\    (      ))\   )\    (     )\))( )\   (      ))\  ))\  )(  )\   (     )\))(  ----
-							----(_(_())((_)   )\  ' /((_) ((_)   )\ ) ((_))\((_)  )\ )  /((_)/((_)(()\((_)  )\ ) ((_))\  ----
-							----|_   _| (_) _((_)) (_))   | __| _(_/(  (()(_)(_) _(_/( (_)) (_))   ((_)(_) _(_/(  (()(_) ----
-							----  | |   | || '  \()/ -_)  | _| | ' \))/ _` | | || ' \))/ -_)/ -_) | '_|| || ' \))/ _` |  ----
-							----  |_|   |_||_|_|_| \___|  |___||_||_| \__, | |_||_||_| \___|\___| |_|  |_||_||_| \__, |  ----
-							----                                      |___/                                      |___/   ----
-							-------------------------------------------------------------------------------------------------
-							-------------------------------------------------------------------------------------------------
-							-------------------------------------------------------------------------------------------------
-
-------------------------------------------------------------------------------------------------------------------------------------------
-------------------------------------------------------------------------------------------------------------------------------------------
-------------------------------------------------------------------------------------------------------------------------------------------
-----           _____     _                      ___             __ _     _                                       _              __ _  ----
-----    o O O |_   _|   (_)    _ __     ___    | __|   _ _     / _` |   (_)    _ _      ___     ___      _ _    (_)    _ _     / _` | ----
-----   o        | |     | |   | '  \   / -_)   | _|   | ' \    \__, |   | |   | ' \    / -_)   / -_)    | '_|   | |   | ' \    \__, | ----
-----  TS__[O]  _|_|_   _|_|_  |_|_|_|  \___|   |___|  |_||_|   |___/   _|_|_  |_||_|   \___|   \___|   _|_|_   _|_|_  |_||_|   |___/  ----
----- {======|_|"""""|_|"""""|_|"""""|_|"""""|_|"""""|_|"""""|_|"""""|_|"""""|_|"""""|_|"""""|_|"""""|_|"""""|_|"""""|_|"""""|_|"""""| ----
-----./o--000'"`-0-0-'"`-0-0-'"`-0-0-'"`-0-0-'"`-0-0-'"`-0-0-'"`-0-0-'"`-0-0-'"`-0-0-'"`-0-0-'"`-0-0-'"`-0-0-'"`-0-0-'"`-0-0-'"`-0-0-' ----
-------------------------------------------------------------------------------------------------------------------------------------------
-------------------------------------------------------------------------------------------------------------------------------------------
-------------------------------------------------------------------------------------------------------------------------------------------
-
--------------------------------------DESCRIPTION------------------------------------------
-------------------------------------------------------------------------------------------
--- Bridge da FIFO 8bit to AXI4 Stream.													--
-------------------------------------------------------------------------------------------
-------------------------------------------------------------------------------------------
-
-
-library ieee;
-	use ieee.std_logic_1164.all;
-	use ieee.numeric_std.all;
-	
-entity AXI4Stream_UART_v1_0_M00_AXIS_RX is
-	generic (
-		-- Width of S_AXIS address bus. The slave accepts the read and write addresses of width C_M_AXIS_TDATA_WIDTH.
-		C_M_AXIS_TDATA_WIDTH	: integer	:= 8
-	);
-	port (
-		--------------FIFO_DATA (8bit)--------------
-		--FIFO_DATA_rst 				: OUT 	STD_LOGIC; Reset lo da chi scrive la FIFO
-		FIFO_DATA_clk 				: OUT 	STD_LOGIC;
-		FIFO_DATA_dout 				: IN 	STD_LOGIC_VECTOR(8-1 DOWNTO 0);
-		FIFO_DATA_rd_en 			: OUT 	STD_LOGIC;
-		FIFO_DATA_empty				: IN 	STD_LOGIC;
-		FIFO_DATA_almost_empty 		: IN 	STD_LOGIC;
-		--------------------------------------------
-		
-		----------------AXI4-Stream-----------------
-		-- AXI4Stream Clock
-		M_AXIS_ACLK		: IN 	STD_LOGIC;
-		-- AXI4Stream Reset
-		M_AXIS_ARESETN	: IN 	STD_LOGIC;
-		-- Master Stream Ports. TVALID indicates that the master is driving a valid transfer, A transfer takes place when both TVALID and TREADY are asserted. 
-		M_AXIS_TVALID	: OUT 	STD_LOGIC;
-		-- TDATA is the primary payload that is used to provide the data that is passing across the interface from the master.
-		M_AXIS_TDATA	: OUT 	STD_LOGIC_VECTOR(C_M_AXIS_TDATA_WIDTH-1 DOWNTO 0);
-		-- TREADY indicates that the slave can accept a transfer in the current cycle.
-		M_AXIS_TREADY	: IN 	STD_LOGIC
-		--------------------------------------------
-	);
-end AXI4Stream_UART_v1_0_M00_AXIS_RX;
-
-architecture implementation of AXI4Stream_UART_v1_0_M00_AXIS_RX is
-	
-	----------------------------SIGNALS-----------------------------
-	signal M_AXIS_TVALID_int	: STD_LOGIC;
-	----------------------------------------------------------------
-
-begin
-	
-	---------DIRECT ASSIGNMENT----------
-	FIFO_DATA_clk			<= M_AXIS_ACLK;
-	--FIFO_DATA_rst 			<= not M_AXIS_ARESETN;
-	
-	M_AXIS_TDATA			<= FIFO_DATA_dout;
-	
-	FIFO_DATA_rd_en			<= M_AXIS_TREADY and M_AXIS_TVALID_int;
-	
-	M_AXIS_TVALID_int		<= not FIFO_DATA_empty and M_AXIS_ARESETN;
-	M_AXIS_TVALID			<= M_AXIS_TVALID_int;
-
-	------------------------------------
-
-end implementation;

LAB2/src/pak_depak/ipshared/453d/hdl/AXI4Stream_UART_v1_0_S00_AXIS_TX.vhd

@@ -1,90 +0,0 @@
-							-------------------------------------------------------------------------------------------------
-							-------------------------------------------------------------------------------------------------
-							-------------------------------------------------------------------------------------------------
-							----  *   )                                                                                  ----
-							----` )  /( (      )      (    (           (  (  (            (    (   (   (          (  (   ----
-							---- ( )(_)))\    (      ))\   )\    (     )\))( )\   (      ))\  ))\  )(  )\   (     )\))(  ----
-							----(_(_())((_)   )\  ' /((_) ((_)   )\ ) ((_))\((_)  )\ )  /((_)/((_)(()\((_)  )\ ) ((_))\  ----
-							----|_   _| (_) _((_)) (_))   | __| _(_/(  (()(_)(_) _(_/( (_)) (_))   ((_)(_) _(_/(  (()(_) ----
-							----  | |   | || '  \()/ -_)  | _| | ' \))/ _` | | || ' \))/ -_)/ -_) | '_|| || ' \))/ _` |  ----
-							----  |_|   |_||_|_|_| \___|  |___||_||_| \__, | |_||_||_| \___|\___| |_|  |_||_||_| \__, |  ----
-							----                                      |___/                                      |___/   ----
-							-------------------------------------------------------------------------------------------------
-							-------------------------------------------------------------------------------------------------
-							-------------------------------------------------------------------------------------------------
-
-------------------------------------------------------------------------------------------------------------------------------------------
-------------------------------------------------------------------------------------------------------------------------------------------
-------------------------------------------------------------------------------------------------------------------------------------------
-----           _____     _                      ___             __ _     _                                       _              __ _  ----
-----    o O O |_   _|   (_)    _ __     ___    | __|   _ _     / _` |   (_)    _ _      ___     ___      _ _    (_)    _ _     / _` | ----
-----   o        | |     | |   | '  \   / -_)   | _|   | ' \    \__, |   | |   | ' \    / -_)   / -_)    | '_|   | |   | ' \    \__, | ----
-----  TS__[O]  _|_|_   _|_|_  |_|_|_|  \___|   |___|  |_||_|   |___/   _|_|_  |_||_|   \___|   \___|   _|_|_   _|_|_  |_||_|   |___/  ----
----- {======|_|"""""|_|"""""|_|"""""|_|"""""|_|"""""|_|"""""|_|"""""|_|"""""|_|"""""|_|"""""|_|"""""|_|"""""|_|"""""|_|"""""|_|"""""| ----
-----./o--000'"`-0-0-'"`-0-0-'"`-0-0-'"`-0-0-'"`-0-0-'"`-0-0-'"`-0-0-'"`-0-0-'"`-0-0-'"`-0-0-'"`-0-0-'"`-0-0-'"`-0-0-'"`-0-0-'"`-0-0-' ----
-------------------------------------------------------------------------------------------------------------------------------------------
-------------------------------------------------------------------------------------------------------------------------------------------
-------------------------------------------------------------------------------------------------------------------------------------------
-
--------------------------------------DESCRIPTION------------------------------------------
-------------------------------------------------------------------------------------------
--- Bridge da FIFO 8bit to AXI4 Stream.													--
-------------------------------------------------------------------------------------------
-------------------------------------------------------------------------------------------
-
-library ieee;
-	use ieee.std_logic_1164.all;
-	use ieee.numeric_std.all;
-
-entity AXI4Stream_UART_v1_0_S00_AXIS_TX is
-	generic (
-		-- AXI4Stream sink: Data Width
-		C_S_AXIS_TDATA_WIDTH	: integer	:= 8
-	);
-	port (
-
-		--------------FIFO_DATA (32bit)-------------
-		FIFO_DATA_rst 				: OUT 	STD_LOGIC;
-		FIFO_DATA_clk 				: OUT 	STD_LOGIC;
-		FIFO_DATA_din 				: OUT 	STD_LOGIC_VECTOR(C_S_AXIS_TDATA_WIDTH-1 DOWNTO 0);
-		FIFO_DATA_wr_en 			: OUT 	STD_LOGIC;
-		FIFO_DATA_full 				: IN 	STD_LOGIC;
-		FIFO_DATA_almost_full 		: IN 	STD_LOGIC;
-		--------------------------------------------
-
-		----------------AXI4-Stream-----------------
-		-- AXI4Stream sink: Clock
-		S_AXIS_ACLK		: IN 	STD_LOGIC;
-		-- AXI4Stream sink: Reset
-		S_AXIS_ARESETN	: IN 	STD_LOGIC;
-		-- Ready to accept data in
-		S_AXIS_TREADY	: OUT 	STD_LOGIC;
-		-- Data in
-		S_AXIS_TDATA	: IN 	STD_LOGIC_VECTOR(C_S_AXIS_TDATA_WIDTH-1 DOWNTO 0);
-		-- Data is in valid
-		S_AXIS_TVALID	: IN 	STD_LOGIC
-		--------------------------------------------
-	);
-end AXI4Stream_UART_v1_0_S00_AXIS_TX;
-
-architecture arch_imp of AXI4Stream_UART_v1_0_S00_AXIS_TX is
-
-	-----------------------------SIGNALS----------------------------
-	signal S_AXIS_TREADY_int	: STD_LOGIC;
-	----------------------------------------------------------------
-
-begin
-
-	---------DIRECT ASSIGNMENT----------
-	FIFO_DATA_clk			<= S_AXIS_ACLK;
-	FIFO_DATA_rst 			<= not S_AXIS_ARESETN;
-
-	FIFO_DATA_din 			<= S_AXIS_TDATA;
-
-	FIFO_DATA_wr_en			<= S_AXIS_TREADY_int and S_AXIS_TVALID;
-
-	S_AXIS_TREADY_int		<= not FIFO_DATA_almost_full and S_AXIS_ARESETN;
-	S_AXIS_TREADY			<= S_AXIS_TREADY_int;
-	------------------------------------
-
-end arch_imp;

LAB2/src/pak_depak/ipshared/453d/hdl/UART_Engine.vhd

@@ -1,343 +0,0 @@
-----------------------------------------------------------------------------------
--- Company:
--- Engineer:
---
--- Create Date:    12:02:15 01/23/2016
--- Design Name:
--- Module Name:    uart - Behavioral
--- Project Name:
--- Target Devices:
--- Tool versions:
--- Description:
---
--- Dependencies:
---
--- Revision:
--- Revision 0.01 - File Created
--- Additional Comments:
---
-----------------------------------------------------------------------------------
-------------------------------------------------------------------------------
--- UART
--- Implements a universal asynchronous receiver transmitter
--------------------------------------------------------------------------------
--- clock
---      Input clock, must match frequency value given on clock_frequency
---      generic input.
--- reset
---      Synchronous reset.
--- data_stream_in
---      Input data bus for bytes to transmit.
--- data_stream_in_stb
---      Input strobe to qualify the input data bus.
--- data_stream_in_ack
---      Output acknowledge to indicate the UART has begun sending the byte
---      provided on the data_stream_in port.
--- data_stream_in_done
---		  Output pulse che arriva quando fine tx
--- data_stream_out
---      Data output port for received bytes.
--- data_stream_out_stb
---      Output strobe to qualify the received byte. Will be valid for one clock
---      cycle only.
--- tx
---      Serial transmit.
--- rx
---      Serial receive
--------------------------------------------------------------------------------
-library ieee;
-    use ieee.std_logic_1164.all;
-    use ieee.numeric_std.all;
-    use ieee.math_real.all;
-
--- Uncomment the following library declaration if using
--- arithmetic functions with Signed or Unsigned values
---use IEEE.NUMERIC_STD.ALL;
-
--- Uncomment the following library declaration if instantiating
--- any Xilinx primitives in this code.
---library UNISIM;
---use UNISIM.VComponents.all;
-
-entity UART_Engine is
-    generic (
-        BAUD_RATE           : integer range 110 to 2000000;
-        CLOCK_FREQUENCY     : positive
-    );
-    port (
-        clock               :   in  std_logic;
-        reset               :   in  std_logic;
-        data_stream_in      :   in  std_logic_vector(7 downto 0);
-        data_stream_in_stb  :   in  std_logic;
-        data_stream_in_ack  :   out std_logic;
-		  data_stream_in_done :   out std_logic;
-        data_stream_out     :   out std_logic_vector(7 downto 0);
-        data_stream_out_stb :   out std_logic;
-        tx                  :   out std_logic;
-        rx                  :   in  std_logic
-    );
-end UART_Engine;
-
-architecture rtl of UART_Engine is
-    ---------------------------------------------------------------------------
-    -- Baud generation constants
-    ---------------------------------------------------------------------------
-    constant c_tx_div       : integer := integer(round(real(CLOCK_FREQUENCY) / real(BAUD_RATE)));
-    constant c_rx_div       : integer := integer(round(real(CLOCK_FREQUENCY) / real(BAUD_RATE * 16)));
-    ---------------------------------------------------------------------------
-    -- Baud generation signals
-    ---------------------------------------------------------------------------
-    signal tx_baud_counter : integer range 0 to c_tx_div-1 := 0;
-    signal tx_baud_tick : std_logic := '0';
-    signal rx_baud_counter : integer range 0 to c_rx_div-1 := 0;
-    signal rx_baud_tick : std_logic := '0';
-    ---------------------------------------------------------------------------
-    -- Transmitter signals
-    ---------------------------------------------------------------------------
-    type uart_tx_states is (
-        tx_send_start_bit,
-        tx_send_data,
-        tx_send_stop_bit
-    );
-    signal uart_tx_state : uart_tx_states := tx_send_start_bit;
-    signal uart_tx_data_vec : std_logic_vector(7 downto 0) := (others => '0');
-    signal uart_tx_data : std_logic := '1';
-    signal uart_tx_count : unsigned(2 downto 0) := (others => '0');
-    signal uart_rx_data_in_ack : std_logic := '0';
-	 signal uart_rx_data_in_done : std_logic := '0';
-    ---------------------------------------------------------------------------
-    -- Receiver signals
-    ---------------------------------------------------------------------------
-    type uart_rx_states is (
-        rx_get_start_bit,
-        rx_get_data,
-        rx_get_stop_bit
-    );
-    signal uart_rx_state : uart_rx_states := rx_get_start_bit;
-    signal uart_rx_bit : std_logic := '1';
-    signal uart_rx_data_vec : std_logic_vector(7 downto 0) := (others => '0');
-    signal uart_rx_data_sr : std_logic_vector(1 downto 0) := (others => '1');
-    signal uart_rx_filter : unsigned(1 downto 0) := (others => '1');
-    signal uart_rx_count : unsigned(2 downto 0) := (others => '0');
-    signal uart_rx_data_out_stb : std_logic := '0';
-    signal uart_rx_bit_spacing : unsigned (3 downto 0) := (others => '0');
-    signal uart_rx_bit_tick : std_logic := '0';
-begin
-    -- Connect IO
-    data_stream_in_ack  <= uart_rx_data_in_ack;
-	 data_stream_in_done  <= uart_rx_data_in_done;
-    data_stream_out     <= uart_rx_data_vec;
-    data_stream_out_stb <= uart_rx_data_out_stb;
-    tx                  <= uart_tx_data;
-    ---------------------------------------------------------------------------
-    -- OVERSAMPLE_CLOCK_DIVIDER
-    -- generate an oversampled tick (baud * 16)
-    ---------------------------------------------------------------------------
-    oversample_clock_divider : process (clock)
-    begin
-        if rising_edge (clock) then
-            if reset = '1' then
-                rx_baud_counter <= 0;
-                rx_baud_tick <= '0';
-            else
-                if rx_baud_counter = c_rx_div - 1 then
-                    rx_baud_counter <= 0;
-                    rx_baud_tick <= '1';
-                else
-                    rx_baud_counter <= rx_baud_counter + 1;
-                    rx_baud_tick <= '0';
-                end if;
-            end if;
-        end if;
-    end process oversample_clock_divider;
-    ---------------------------------------------------------------------------
-    -- RXD_SYNCHRONISE
-    -- Synchronise rxd to the oversampled baud
-    ---------------------------------------------------------------------------
-    rxd_synchronise : process(clock)
-    begin
-        if rising_edge(clock) then
-            if reset = '1' then
-                uart_rx_data_sr <= (others => '1');
-            else
-                if rx_baud_tick = '1' then
-                    uart_rx_data_sr(0) <= rx;
-                    uart_rx_data_sr(1) <= uart_rx_data_sr(0);
-                end if;
-            end if;
-        end if;
-    end process rxd_synchronise;
-    ---------------------------------------------------------------------------
-    -- RXD_FILTER
-    -- Filter rxd with a 2 bit counter.
-    ---------------------------------------------------------------------------
-    rxd_filter : process(clock)
-    begin
-        if rising_edge(clock) then
-            if reset = '1' then
-                uart_rx_filter <= (others => '1');
-                uart_rx_bit <= '1';
-            else
-                if rx_baud_tick = '1' then
-                    -- filter rxd.
-                    if uart_rx_data_sr(1) = '1' and uart_rx_filter < 3 then
-                        uart_rx_filter <= uart_rx_filter + 1;
-                    elsif uart_rx_data_sr(1) = '0' and uart_rx_filter > 0 then
-                        uart_rx_filter <= uart_rx_filter - 1;
-                    end if;
-                    -- set the rx bit.
-                    if uart_rx_filter = 3 then
-                        uart_rx_bit <= '1';
-                    elsif uart_rx_filter = 0 then
-                        uart_rx_bit <= '0';
-                    end if;
-                end if;
-            end if;
-        end if;
-    end process rxd_filter;
-    ---------------------------------------------------------------------------
-    -- RX_BIT_SPACING
-    ---------------------------------------------------------------------------
-    rx_bit_spacing : process (clock)
-    begin
-        if rising_edge(clock) then
-            uart_rx_bit_tick <= '0';
-            if rx_baud_tick = '1' then
-                if uart_rx_bit_spacing = 15 then
-                    uart_rx_bit_tick <= '1';
-                    uart_rx_bit_spacing <= (others => '0');
-                else
-                    uart_rx_bit_spacing <= uart_rx_bit_spacing + 1;
-                end if;
-                if uart_rx_state = rx_get_start_bit then
-                    uart_rx_bit_spacing <= (others => '0');
-                end if;
-            end if;
-        end if;
-    end process rx_bit_spacing;
-    ---------------------------------------------------------------------------
-    -- UART_RECEIVE_DATA
-    ---------------------------------------------------------------------------
-    uart_receive_data   : process(clock)
-    begin
-        if rising_edge(clock) then
-            if reset = '1' then
-                uart_rx_state <= rx_get_start_bit;
-                uart_rx_data_vec <= (others => '0');
-                uart_rx_count <= (others => '0');
-                uart_rx_data_out_stb <= '0';
-            else
-                uart_rx_data_out_stb <= '0';
-                case uart_rx_state is
-                    when rx_get_start_bit =>
-                        if rx_baud_tick = '1' and uart_rx_bit = '0' then
-                            uart_rx_state <= rx_get_data;
-                        end if;
-                    when rx_get_data =>
-                        if uart_rx_bit_tick = '1' then
-                            uart_rx_data_vec(uart_rx_data_vec'high)
-                                <= uart_rx_bit;
-                            uart_rx_data_vec(
-                                uart_rx_data_vec'high-1 downto 0
-                            ) <= uart_rx_data_vec(
-                                uart_rx_data_vec'high downto 1
-                            );
-                            if uart_rx_count < 7 then
-                                uart_rx_count   <= uart_rx_count + 1;
-                            else
-                                uart_rx_count <= (others => '0');
-                                uart_rx_state <= rx_get_stop_bit;
-                            end if;
-                        end if;
-                    when rx_get_stop_bit =>
-                        if uart_rx_bit_tick = '1' then
-                            if uart_rx_bit = '1' then
-                                uart_rx_state <= rx_get_start_bit;
-                                uart_rx_data_out_stb <= '1';
-                            end if;
-                        end if;
-                    when others =>
-                        uart_rx_state <= rx_get_start_bit;
-                end case;
-            end if;
-        end if;
-    end process uart_receive_data;
-    ---------------------------------------------------------------------------
-    -- TX_CLOCK_DIVIDER
-    -- Generate baud ticks at the required rate based on the input clock
-    -- frequency and baud rate
-    ---------------------------------------------------------------------------
-    tx_clock_divider : process (clock)
-    begin
-        if rising_edge (clock) then
-            if reset = '1' then
-                tx_baud_counter <= 0;
-                tx_baud_tick <= '0';
-            else
-                if tx_baud_counter = c_tx_div - 1 then
-                    tx_baud_counter <= 0;
-                    tx_baud_tick <= '1';
-                else
-                    tx_baud_counter <= tx_baud_counter + 1;
-                    tx_baud_tick <= '0';
-                end if;
-            end if;
-        end if;
-    end process tx_clock_divider;
-    ---------------------------------------------------------------------------
-    -- UART_SEND_DATA
-    -- Get data from data_stream_in and send it one bit at a time upon each
-    -- baud tick. Send data lsb first.
-    -- wait 1 tick, send start bit (0), send data 0-7, send stop bit (1)
-    ---------------------------------------------------------------------------
-    uart_send_data : process(clock)
-    begin
-        if rising_edge(clock) then
-            if reset = '1' then
-                uart_tx_data <= '1';
-                uart_tx_data_vec <= (others => '0');
-                uart_tx_count <= (others => '0');
-                uart_tx_state <= tx_send_start_bit;
-                uart_rx_data_in_ack <= '0';
-					 uart_rx_data_in_done <= '0';
-            else
-               uart_rx_data_in_ack <= '0';
-					uart_rx_data_in_done <= '0';	--new
-                case uart_tx_state is
-                    when tx_send_start_bit =>
-                        if tx_baud_tick = '1' and data_stream_in_stb = '1' then
-                            uart_tx_data  <= '0';
-                            uart_tx_state <= tx_send_data;
-                            uart_tx_count <= (others => '0');
-                            uart_rx_data_in_ack <= '1';
-                            uart_tx_data_vec <= data_stream_in;
-                        end if;
-                    when tx_send_data =>
-                        if tx_baud_tick = '1' then
-                            uart_tx_data <= uart_tx_data_vec(0);
-                            uart_tx_data_vec(
-                                uart_tx_data_vec'high-1 downto 0
-                            ) <= uart_tx_data_vec(
-                                uart_tx_data_vec'high downto 1
-                            );
-                            if uart_tx_count < 7 then
-                                uart_tx_count <= uart_tx_count + 1;
-                            else
-                                uart_tx_count <= (others => '0');
-                                uart_tx_state <= tx_send_stop_bit;
-                            end if;
-                        end if;
-                    when tx_send_stop_bit =>
-                        if tx_baud_tick = '1' then
-                            uart_tx_data <= '1';
-                            uart_tx_state <= tx_send_start_bit;
-									 uart_rx_data_in_done <= '1';	--new
-                        end if;
-                    when others =>
-                        uart_tx_data <= '1';
-                        uart_tx_state <= tx_send_start_bit;
-                end case;
-            end if;
-        end if;
-    end process uart_send_data;
-end rtl;

LAB2/src/pak_depak/ipshared/453d/hdl/UART_Manager.vhd

@@ -1,238 +0,0 @@
-							-------------------------------------------------------------------------------------------------
-							-------------------------------------------------------------------------------------------------
-							-------------------------------------------------------------------------------------------------
-							----  *   )                                                                                  ----
-							----` )  /( (      )      (    (           (  (  (            (    (   (   (          (  (   ----
-							---- ( )(_)))\    (      ))\   )\    (     )\))( )\   (      ))\  ))\  )(  )\   (     )\))(  ----
-							----(_(_())((_)   )\  ' /((_) ((_)   )\ ) ((_))\((_)  )\ )  /((_)/((_)(()\((_)  )\ ) ((_))\  ----
-							----|_   _| (_) _((_)) (_))   | __| _(_/(  (()(_)(_) _(_/( (_)) (_))   ((_)(_) _(_/(  (()(_) ----
-							----  | |   | || '  \()/ -_)  | _| | ' \))/ _` | | || ' \))/ -_)/ -_) | '_|| || ' \))/ _` |  ----
-							----  |_|   |_||_|_|_| \___|  |___||_||_| \__, | |_||_||_| \___|\___| |_|  |_||_||_| \__, |  ----
-							----                                      |___/                                      |___/   ----
-							-------------------------------------------------------------------------------------------------
-							-------------------------------------------------------------------------------------------------
-							-------------------------------------------------------------------------------------------------
-
-------------------------------------------------------------------------------------------------------------------------------------------
-------------------------------------------------------------------------------------------------------------------------------------------
-------------------------------------------------------------------------------------------------------------------------------------------
-----           _____     _                      ___             __ _     _                                       _              __ _  ----
-----    o O O |_   _|   (_)    _ __     ___    | __|   _ _     / _` |   (_)    _ _      ___     ___      _ _    (_)    _ _     / _` | ----
-----   o        | |     | |   | '  \   / -_)   | _|   | ' \    \__, |   | |   | ' \    / -_)   / -_)    | '_|   | |   | ' \    \__, | ----
-----  TS__[O]  _|_|_   _|_|_  |_|_|_|  \___|   |___|  |_||_|   |___/   _|_|_  |_||_|   \___|   \___|   _|_|_   _|_|_  |_||_|   |___/  ----
----- {======|_|"""""|_|"""""|_|"""""|_|"""""|_|"""""|_|"""""|_|"""""|_|"""""|_|"""""|_|"""""|_|"""""|_|"""""|_|"""""|_|"""""|_|"""""| ----
-----./o--000'"`-0-0-'"`-0-0-'"`-0-0-'"`-0-0-'"`-0-0-'"`-0-0-'"`-0-0-'"`-0-0-'"`-0-0-'"`-0-0-'"`-0-0-'"`-0-0-'"`-0-0-'"`-0-0-'"`-0-0-' ----
-------------------------------------------------------------------------------------------------------------------------------------------
-------------------------------------------------------------------------------------------------------------------------------------------
-------------------------------------------------------------------------------------------------------------------------------------------
-
--------------------------------------DESCRIPTION------------------------------------------
-------------------------------------------------------------------------------------------
--- Modulo di pi<70> basso livello per la gestione dei dati tra FIFO in e FIFO out ed il	--
--- modulo FTDI 2232H in modalita FT245 Asynchronous. La priorit<69> <20> data ai dati in 		--
--- arrivo dal PC verso FPGA.															--
--- Il clock in ingresso deve avere un periodo di 10 ns per garantire i tempi 			--
--- rischiesti dal 2232H																	--
-------------------------------------------------------------------------------------------
-------------------------------------------------------------------------------------------
-
-library IEEE;
-	use IEEE.STD_LOGIC_1164.ALL;
-
-entity UART_Manager is
-	generic(
-		UART_BAUD_RATE           : positive;
-		UART_CLOCK_FREQUENCY     : positive	--The associated clock frequency
-	);
-	Port (	
-		---------Global---------
-		clk_uart 	: IN  STD_LOGIC;
-		reset 		: IN  STD_LOGIC;
-		------------------------
-		
-		---------Connessioni comunicazione UART-----------
-		UART_TX  : OUT STD_LOGIC;
-		UART_RX  : IN  STD_LOGIC;
-		---------------------------------------------------
-		
-		------------FIFO_DATA_RX (8bit)-------------
-		FIFO_DATA_RX_rst 			: OUT 	STD_LOGIC;
-		FIFO_DATA_RX_clk 			: OUT 	STD_LOGIC;
-		FIFO_DATA_RX_din 			: OUT 	STD_LOGIC_VECTOR(8-1 DOWNTO 0);
-		FIFO_DATA_RX_wr_en 			: OUT 	STD_LOGIC;
-		FIFO_DATA_RX_full			: IN 	STD_LOGIC;
-		FIFO_DATA_RX_almost_full 	: IN 	STD_LOGIC;
-		--------------------------------------------
-		
-		------------FIFO_DATA_TX (8bit)-------------
-		--FIFO_DATA_RX_rst 			: OUT 	STD_LOGIC;
-		FIFO_DATA_TX_clk 			: OUT 	STD_LOGIC;
-		FIFO_DATA_TX_dout 			: IN 	STD_LOGIC_VECTOR(8-1 DOWNTO 0);
-		FIFO_DATA_TX_rd_en 			: OUT 	STD_LOGIC;
-		FIFO_DATA_TX_empty			: IN 	STD_LOGIC;
-		FIFO_DATA_TX_almost_empty 	: IN 	STD_LOGIC
-		--------------------------------------------
-	);
-end UART_Manager;
-
-architecture Behavioral of UART_Manager is
-	
-	-------------------COMPONENT------------------
-	COMPONENT UART_engine
-	   GENERIC(
-        BAUD_RATE           : positive;
-        CLOCK_FREQUENCY     : positive
-		);
-		PORT(
-			--SYSTEM UART
-			clock 			: IN std_logic;
-			reset 			: IN std_logic;
-			
-			--	FPGA-->PC
-			data_stream_in 		: IN std_logic_vector(7 downto 0);
-			data_stream_in_stb 	: IN std_logic;
-			data_stream_in_ack 	: OUT std_logic;
-			data_stream_in_done 	: OUT std_logic;
-			tx 						: OUT std_logic;
-			
-			--	PC-->FPGA
-			data_stream_out 		: OUT std_logic_vector(7 downto 0);
-			data_stream_out_stb 	: OUT std_logic;
-			rx 						: IN std_logic
-			
-		);
-	END COMPONENT;	
-	----------------------------------------------
-	
-	--------------------SIGNALS-------------------
-	signal state			: STD_LOGIC_VECTOR(7 DOWNTO 0):=x"00";
-	
-	--TX:fromFPGAtoPC
-	signal data_stream_in		: STD_LOGIC_VECTOR(7 DOWNTO 0) := (others=>'0');
-	signal data_stream_in_stb	: STD_LOGIC := '0'; 	
-	signal data_stream_in_ack	: STD_LOGIC := '0'; 	
-	signal data_stream_in_done	: STD_LOGIC := '0'; 	
-		
-	signal state_TX			: STD_LOGIC_VECTOR(7 DOWNTO 0):=x"FF";
-
-	--RX:fromPCtoFPGA
-	signal data_stream_out		: STD_LOGIC_VECTOR(7 DOWNTO 0) := (others=>'0');
-	signal data_stream_out_stb	: STD_LOGIC := '0';
-	----------------------------------------------
-	
-begin
-		
-	Inst_uart: UART_engine 
-		GENERIC MAP (
-			BAUD_RATE		=> UART_BAUD_RATE,
-			CLOCK_FREQUENCY	=> UART_CLOCK_FREQUENCY
-		)
-		PORT MAP(
-			clock => clk_uart,
-			reset => reset,
-			
-			--	FPGA-->PC
-			data_stream_in 	  	=> data_stream_in,			--byte FPGA->PC, (in)
-			data_stream_in_stb  => data_stream_in_stb,	--'1' per 1 clock inizia la fase di trasmisisone a PC di data_stream_in (in)
-			data_stream_in_ack  => data_stream_in_ack,	--'1' per 1 clock vuol dire che START TX (data_stream_in_stb='1') <20> stata capita (in)	
-			data_stream_in_done => data_stream_in_done,	--'1' indica la fine della trasmisione (out)
-			tx 					=> UART_TX,
-			
-			--	PC-->FPGA
-			data_stream_out 		=> data_stream_out,		--byte PC->FPGA, (out)
-			data_stream_out_stb	=> data_stream_out_stb,	--'1' per 1 clock indica che su data_stream_out c'<27> un nuovo dato (out)
---			data_stream_out 		=> FIFO_RX_din,
---			data_stream_out_stb	=> FIFO_RX_wr_en,
-			rx 					 	=> UART_RX
-			
-		);	
-	
-	fromFPGAtoPC : process(clk_uart, reset)
-		begin
-			if (reset = '1') then
-				state_TX 		<= x"00";
-				--UART
-				data_stream_in <= (others => '0');
-				data_stream_in_stb		<= '0';
-				--FIFO_TX
-				FIFO_DATA_TX_rd_en	<= '0';
-
-			elsif rising_edge(clk_uart) then
-				case state_TX is
-				
-					when x"FF" =>
-						if(reset = '0') then                    
-							 state_TX <= x"00";                          
-						else
-							 state_TX <= x"FF";               
-						end if;
-						--UART
-						data_stream_in <= (others => '0');
-						data_stream_in_stb		<= '0';
-						--FIFO_TX
-						FIFO_DATA_TX_rd_en	<= '0';
-					
-					
-					when x"00" =>
-						FIFO_DATA_TX_rd_en			<= '0';
-						data_stream_in_stb	<= '0';
-						
-						if (FIFO_DATA_TX_empty = '0') then				--nessun dato da trasmettere al PC
-							state_TX 		    <= x"01";			--si hanno dati in FIFO TX da passare al PC
-							FIFO_DATA_TX_rd_en  	 <= '1';				--abilita lettura FIFO
-							data_stream_in 	 <= FIFO_DATA_TX_dout;	--dai alla UART il byte in uscita dalla fifo gi<67> pronto
-							data_stream_in_stb <= '1';				--abilita TX della UART
-						end if;
-						
-						
-					when x"01" =>
-						FIFO_DATA_TX_rd_en			<= '0';				--blocca la lettura FIFO
-						--tieni data_stream_in_stb attivo finche la UART non inizia a trasferire data_stream_in_ack='0'
-						if (data_stream_in_ack = '1') then
-							state_TX					<= x"02";
-							data_stream_in_stb	<= '0';
-						end if;						
-						
-						
-					when x"02" =>
-						-- data_stream_in_done = '1' significa fin trasmisisone UART
-						if (data_stream_in_done = '1') then
-							state_TX <= x"00";
-						end if;				
-					
-					
-					when others =>
-						state_TX <= x"00";
-	
-				
-				end case;
-			end if;
-		end process;
-
-
-
-	fromPCtoFPGA : process(clk_uart, reset)
-		begin
-			if (reset = '1') then
-				FIFO_DATA_RX_din		<= (others => '0');
-				FIFO_DATA_RX_wr_en	<= '0';
-
-			elsif rising_edge(clk_uart) then
-				FIFO_DATA_RX_wr_en	<= '0';
-				if (data_stream_out_stb = '1') then		--arrivato nuovo dato sulla UART, caricalo in FIGO RX
-					FIFO_DATA_RX_wr_en	<= '1';
-					FIFO_DATA_RX_din 	<= data_stream_out;
-				end if;
-			end if;
-			
-		end process;		
-	
-	--------------------ASSIGMENT------------------
-	FIFO_DATA_RX_clk	<= clk_uart;
-	FIFO_DATA_TX_clk	<= clk_uart;
-	
-	FIFO_DATA_RX_rst	<= reset;
-	-----------------------------------------------
-	
-end Behavioral;
-

LAB2/src/pak_depak/ipshared/d0f7/mmcm_pll_drp_func_7s_mmcm.vh

@@ -1,671 +0,0 @@
-///////////////////////////////////////////////////////////////////////////////
-//    
-//    Company:          Xilinx
-//    Engineer:         Jim Tatsukawa, Karl Kurbjun and Carl Ribbing
-//    Date:             7/30/2014
-//    Design Name:      MMCME2 DRP
-//    Module Name:      mmcme2_drp_func.h
-//    Version:          1.04
-//    Target Devices:   7 Series || MMCM
-//    Tool versions:    2014.3
-//    Description:      This header provides the functions necessary to  
-//                      calculate the DRP register values for the V6 MMCM.
-//                      
-//	Revision Notes:	3/12 - Updating lookup_low/lookup_high (CR)
-//			4/13 - Fractional divide function in mmcm_frac_count_calc function. CRS610807
-// 
-//    Disclaimer:  XILINX IS PROVIDING THIS DESIGN, CODE, OR
-//                 INFORMATION "AS IS" SOLELY FOR USE IN DEVELOPING
-//                 PROGRAMS AND SOLUTIONS FOR XILINX DEVICES.  BY
-//                 PROVIDING THIS DESIGN, CODE, OR INFORMATION AS
-//                 ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE,
-//                 APPLICATION OR STANDARD, XILINX IS MAKING NO
-//                 REPRESENTATION THAT THIS IMPLEMENTATION IS FREE
-//                 FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE
-//                 RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY
-//                 REQUIRE FOR YOUR IMPLEMENTATION.  XILINX
-//                 EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH
-//                 RESPECT TO THE ADEQUACY OF THE IMPLEMENTATION,
-//                 INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR
-//                 REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE
-//                 FROM CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES
-//                 OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-//                 PURPOSE.
-// 
-//                 (c) Copyright 2009-2010 Xilinx, Inc.
-//                 All rights reserved.
-// 
-///////////////////////////////////////////////////////////////////////////////
-
-// These are user functions that should not be modified.  Changes to the defines
-// or code within the functions may alter the accuracy of the calculations.
-
-// Define debug to provide extra messages durring elaboration
-//`define DEBUG 1
-
-// FRAC_PRECISION describes the width of the fractional portion of the fixed
-//    point numbers.  These should not be modified, they are for development 
-//    only
-`define FRAC_PRECISION  10
-// FIXED_WIDTH describes the total size for fixed point calculations(int+frac).
-// Warning: L.50 and below will not calculate properly with FIXED_WIDTHs 
-//    greater than 32
-`define FIXED_WIDTH     32 
-
-// This function takes a fixed point number and rounds it to the nearest
-//    fractional precision bit.
-function [`FIXED_WIDTH:1] round_frac
-   (
-      // Input is (FIXED_WIDTH-FRAC_PRECISION).FRAC_PRECISION fixed point number
-      input [`FIXED_WIDTH:1] decimal,  
-
-      // This describes the precision of the fraction, for example a value
-      //    of 1 would modify the fractional so that instead of being a .16
-      //    fractional, it would be a .1 (rounded to the nearest 0.5 in turn)
-      input [`FIXED_WIDTH:1] precision 
-   );
-
-   begin
-   
-   `ifdef DEBUG
-      $display("round_frac - decimal: %h, precision: %h", decimal, precision);
-   `endif
-      // If the fractional precision bit is high then round up
-      if( decimal[(`FRAC_PRECISION-precision)] == 1'b1) begin
-         round_frac = decimal + (1'b1 << (`FRAC_PRECISION-precision));
-      end else begin
-         round_frac = decimal;
-      end
-   `ifdef DEBUG
-      $display("round_frac: %h", round_frac);
-   `endif
-   end
-endfunction
-
-// This function calculates high_time, low_time, w_edge, and no_count
-//    of a non-fractional counter based on the divide and duty cycle
-//
-// NOTE: high_time and low_time are returned as integers between 0 and 63 
-//    inclusive.  64 should equal 6'b000000 (in other words it is okay to 
-//    ignore the overflow)
-function [13:0] mmcm_pll_divider
-   (
-      input [7:0] divide,        // Max divide is 128
-      input [31:0] duty_cycle    // Duty cycle is multiplied by 100,000
-   );
-
-   reg [`FIXED_WIDTH:1]    duty_cycle_fix;
-   
-   // High/Low time is initially calculated with a wider integer to prevent a
-   // calculation error when it overflows to 64.
-   reg [6:0]               high_time;
-   reg [6:0]               low_time;
-   reg                     w_edge;
-   reg                     no_count;
-
-   reg [`FIXED_WIDTH:1]    temp;
-
-   begin
-      // Duty Cycle must be between 0 and 1,000
-      if(duty_cycle <=0 || duty_cycle >= 100000) begin
-`ifndef SYNTHESIS
-         $display("ERROR: duty_cycle: %d is invalid", duty_cycle);
-   `endif
-         $finish;
-      end
-
-      // Convert to FIXED_WIDTH-FRAC_PRECISION.FRAC_PRECISION fixed point
-      duty_cycle_fix = (duty_cycle << `FRAC_PRECISION) / 100_000;
-      
-   `ifdef DEBUG
-      $display("duty_cycle_fix: %h", duty_cycle_fix);
-   `endif
-
-      // If the divide is 1 nothing needs to be set except the no_count bit.
-      //    Other values are dummies
-      if(divide == 7'h01) begin
-         high_time   = 7'h01;
-         w_edge      = 1'b0;
-         low_time    = 7'h01;
-         no_count    = 1'b1;
-      end else begin
-         temp = round_frac(duty_cycle_fix*divide, 1);
-
-         // comes from above round_frac
-         high_time   = temp[`FRAC_PRECISION+7:`FRAC_PRECISION+1]; 
-         // If the duty cycle * divide rounded is .5 or greater then this bit
-         //    is set.
-         w_edge      = temp[`FRAC_PRECISION]; // comes from round_frac
-         
-         // If the high time comes out to 0, it needs to be set to at least 1
-         // and w_edge set to 0
-         if(high_time == 7'h00) begin
-            high_time   = 7'h01;
-            w_edge      = 1'b0;
-         end
-
-         if(high_time == divide) begin
-            high_time   = divide - 1;
-            w_edge      = 1'b1;
-         end
-         
-         // Calculate low_time based on the divide setting and set no_count to
-         //    0 as it is only used when divide is 1.
-         low_time    = divide - high_time; 
-         no_count    = 1'b0;
-      end
-
-      // Set the return value.
-      mmcm_pll_divider = {w_edge,no_count,high_time[5:0],low_time[5:0]};
-   end
-endfunction
-
-// This function calculates mx, delay_time, and phase_mux 
-//  of a non-fractional counter based on the divide and phase
-//
-// NOTE: The only valid value for the MX bits is 2'b00 to ensure the coarse mux
-//    is used.
-function [10:0] mmcm_pll_phase
-   (
-      // divide must be an integer (use fractional if not)
-      //  assumed that divide already checked to be valid
-      input [7:0] divide, // Max divide is 128
-
-      // Phase is given in degrees (-360,000 to 360,000)
-      input signed [31:0] phase
-   );
-
-   reg [`FIXED_WIDTH:1] phase_in_cycles;
-   reg [`FIXED_WIDTH:1] phase_fixed;
-   reg [1:0]            mx;
-   reg [5:0]            delay_time;
-   reg [2:0]            phase_mux;
-
-   reg [`FIXED_WIDTH:1] temp;
-
-   begin
-`ifdef DEBUG
-      $display("mmcm_pll_phase-divide:%d,phase:%d",
-         divide, phase);
-`endif
-   
-      if ((phase < -360000) || (phase > 360000)) begin
-`ifndef SYNTHESIS
-      $display("ERROR: phase of $phase is not between -360000 and 360000");
-	`endif
-         $finish;
-      end
-
-      // If phase is less than 0, convert it to a positive phase shift
-      // Convert to (FIXED_WIDTH-FRAC_PRECISION).FRAC_PRECISION fixed point
-      if(phase < 0) begin
-         phase_fixed = ( (phase + 360000) << `FRAC_PRECISION ) / 1000;
-      end else begin
-         phase_fixed = ( phase << `FRAC_PRECISION ) / 1000;
-      end
-
-      // Put phase in terms of decimal number of vco clock cycles
-      phase_in_cycles = ( phase_fixed * divide ) / 360;
-
-`ifdef DEBUG
-      $display("phase_in_cycles: %h", phase_in_cycles);
-`endif  
-      
-
-	 temp  =  round_frac(phase_in_cycles, 3);
-
-	 // set mx to 2'b00 that the phase mux from the VCO is enabled
-	 mx    			=  2'b00; 
-	 phase_mux      =  temp[`FRAC_PRECISION:`FRAC_PRECISION-2];
-	 delay_time     =  temp[`FRAC_PRECISION+6:`FRAC_PRECISION+1];
-      
-   `ifdef DEBUG
-      $display("temp: %h", temp);
-   `endif
-
-      // Setup the return value
-      mmcm_pll_phase={mx, phase_mux, delay_time};
-   end
-endfunction
-
-// This function takes the divide value and outputs the necessary lock values
-function [39:0] mmcm_pll_lock_lookup
-   (
-      input [6:0] divide // Max divide is 64
-   );
-   
-   reg [2559:0]   lookup;
-   
-   begin
-      lookup = {
-         // This table is composed of:
-         // LockRefDly_LockFBDly_LockCnt_LockSatHigh_UnlockCnt
-         40'b00110_00110_1111101000_1111101001_0000000001,
-         40'b00110_00110_1111101000_1111101001_0000000001,
-         40'b01000_01000_1111101000_1111101001_0000000001,
-         40'b01011_01011_1111101000_1111101001_0000000001,
-         40'b01110_01110_1111101000_1111101001_0000000001,
-         40'b10001_10001_1111101000_1111101001_0000000001,
-         40'b10011_10011_1111101000_1111101001_0000000001,
-         40'b10110_10110_1111101000_1111101001_0000000001,
-         40'b11001_11001_1111101000_1111101001_0000000001,
-         40'b11100_11100_1111101000_1111101001_0000000001,
-         40'b11111_11111_1110000100_1111101001_0000000001,
-         40'b11111_11111_1100111001_1111101001_0000000001,
-         40'b11111_11111_1011101110_1111101001_0000000001,
-         40'b11111_11111_1010111100_1111101001_0000000001,
-         40'b11111_11111_1010001010_1111101001_0000000001,
-         40'b11111_11111_1001110001_1111101001_0000000001,
-         40'b11111_11111_1000111111_1111101001_0000000001,
-         40'b11111_11111_1000100110_1111101001_0000000001,
-         40'b11111_11111_1000001101_1111101001_0000000001,
-         40'b11111_11111_0111110100_1111101001_0000000001,
-         40'b11111_11111_0111011011_1111101001_0000000001,
-         40'b11111_11111_0111000010_1111101001_0000000001,
-         40'b11111_11111_0110101001_1111101001_0000000001,
-         40'b11111_11111_0110010000_1111101001_0000000001,
-         40'b11111_11111_0110010000_1111101001_0000000001,
-         40'b11111_11111_0101110111_1111101001_0000000001,
-         40'b11111_11111_0101011110_1111101001_0000000001,
-         40'b11111_11111_0101011110_1111101001_0000000001,
-         40'b11111_11111_0101000101_1111101001_0000000001,
-         40'b11111_11111_0101000101_1111101001_0000000001,
-         40'b11111_11111_0100101100_1111101001_0000000001,
-         40'b11111_11111_0100101100_1111101001_0000000001,
-         40'b11111_11111_0100101100_1111101001_0000000001,
-         40'b11111_11111_0100010011_1111101001_0000000001,
-         40'b11111_11111_0100010011_1111101001_0000000001,
-         40'b11111_11111_0100010011_1111101001_0000000001,
-         40'b11111_11111_0011111010_1111101001_0000000001,
-         40'b11111_11111_0011111010_1111101001_0000000001,
-         40'b11111_11111_0011111010_1111101001_0000000001,
-         40'b11111_11111_0011111010_1111101001_0000000001,
-         40'b11111_11111_0011111010_1111101001_0000000001,
-         40'b11111_11111_0011111010_1111101001_0000000001,
-         40'b11111_11111_0011111010_1111101001_0000000001,
-         40'b11111_11111_0011111010_1111101001_0000000001,
-         40'b11111_11111_0011111010_1111101001_0000000001,
-         40'b11111_11111_0011111010_1111101001_0000000001,
-         40'b11111_11111_0011111010_1111101001_0000000001,
-         40'b11111_11111_0011111010_1111101001_0000000001,
-         40'b11111_11111_0011111010_1111101001_0000000001,
-         40'b11111_11111_0011111010_1111101001_0000000001,
-         40'b11111_11111_0011111010_1111101001_0000000001,
-         40'b11111_11111_0011111010_1111101001_0000000001,
-         40'b11111_11111_0011111010_1111101001_0000000001,
-         40'b11111_11111_0011111010_1111101001_0000000001,
-         40'b11111_11111_0011111010_1111101001_0000000001,
-         40'b11111_11111_0011111010_1111101001_0000000001,
-         40'b11111_11111_0011111010_1111101001_0000000001,
-         40'b11111_11111_0011111010_1111101001_0000000001,
-         40'b11111_11111_0011111010_1111101001_0000000001,
-         40'b11111_11111_0011111010_1111101001_0000000001,
-         40'b11111_11111_0011111010_1111101001_0000000001,
-         40'b11111_11111_0011111010_1111101001_0000000001,
-         40'b11111_11111_0011111010_1111101001_0000000001,
-         40'b11111_11111_0011111010_1111101001_0000000001
-      };
-      
-      // Set lookup_entry with the explicit bits from lookup with a part select
-      mmcm_pll_lock_lookup = lookup[ ((64-divide)*40) +: 40];
-   `ifdef DEBUG
-      $display("lock_lookup: %b", mmcm_pll_lock_lookup);
-   `endif
-   end
-endfunction
-
-// This function takes the divide value and the bandwidth setting of the MMCM
-//  and outputs the digital filter settings necessary.
-function [9:0] mmcm_pll_filter_lookup
-   (
-      input [6:0] divide, // Max divide is 64
-      input [8*9:0] BANDWIDTH
-   );
-   
-   reg [639:0] lookup_low;
-   reg [639:0] lookup_high;
-   
-   reg [9:0] lookup_entry;
-   
-   begin
-      lookup_low = {
-         // CP_RES_LFHF
-         10'b0010_1111_00,
-         10'b0010_1111_00,
-         10'b0010_1111_00,
-         10'b0010_1111_00,
-         10'b0010_0111_00,
-         10'b0010_1011_00,
-         10'b0010_1101_00,
-         10'b0010_0011_00,
-         10'b0010_0101_00,
-         10'b0010_0101_00,
-         10'b0010_1001_00,
-         10'b0010_1110_00,
-         10'b0010_1110_00,
-         10'b0010_1110_00,
-         10'b0010_1110_00,
-         10'b0010_0001_00,
-         10'b0010_0001_00,
-         10'b0010_0001_00,
-         10'b0010_0110_00,
-         10'b0010_0110_00,
-         10'b0010_0110_00,
-         10'b0010_0110_00,
-         10'b0010_0110_00,
-         10'b0010_0110_00,
-         10'b0010_0110_00,
-         10'b0010_1010_00,
-         10'b0010_1010_00,
-         10'b0010_1010_00,
-         10'b0010_1010_00,
-         10'b0010_1010_00,
-         10'b0010_1100_00,
-         10'b0010_1100_00,
-         10'b0010_1100_00,
-         10'b0010_1100_00,
-         10'b0010_1100_00,
-         10'b0010_1100_00,
-         10'b0010_1100_00,
-         10'b0010_1100_00,
-         10'b0010_1100_00,
-         10'b0010_1100_00,
-         10'b0010_1100_00,
-         10'b0010_1100_00,
-         10'b0010_1100_00,
-         10'b0010_1100_00,
-         10'b0010_1100_00,
-         10'b0010_1100_00,
-         10'b0010_1100_00,
-         10'b0010_0010_00,
-         10'b0010_0010_00,
-         10'b0010_0010_00,
-         10'b0010_0010_00,
-         10'b0010_0010_00,
-         10'b0010_0010_00,
-         10'b0010_0010_00,
-         10'b0010_0010_00,
-         10'b0010_0010_00,
-         10'b0010_0010_00,
-         10'b0010_0010_00,
-         10'b0010_0010_00,
-         10'b0010_0010_00,
-         10'b0010_0010_00,
-         10'b0010_0010_00,
-         10'b0010_0010_00,
-         10'b0010_0010_00
-      };
-      
-      lookup_high = {
-         // CP_RES_LFHF
-         10'b0010_1111_00,
-         10'b0100_1111_00,
-         10'b0101_1011_00,
-         10'b0111_0111_00,
-         10'b1101_0111_00,
-         10'b1110_1011_00,
-         10'b1110_1101_00,
-         10'b1111_0011_00,
-         10'b1110_0101_00,
-         10'b1111_0101_00,
-         10'b1111_1001_00,
-         10'b1101_0001_00,
-         10'b1111_1001_00,
-         10'b1111_1001_00,
-         10'b1111_1001_00,
-         10'b1111_1001_00,
-         10'b1111_0101_00,
-         10'b1111_0101_00,
-         10'b1100_0001_00,
-         10'b1100_0001_00,
-         10'b1100_0001_00,
-         10'b0101_1100_00,
-         10'b0101_1100_00,
-         10'b0101_1100_00,
-         10'b0101_1100_00,
-         10'b0011_0100_00,
-         10'b0011_0100_00,
-         10'b0011_0100_00,
-         10'b0011_0100_00,
-         10'b0011_0100_00,
-         10'b0011_0100_00,
-         10'b0011_0100_00,
-         10'b0011_0100_00,
-         10'b0011_0100_00,
-         10'b0011_0100_00,
-         10'b0011_0100_00,
-         10'b0011_0100_00,
-         10'b0011_0100_00,
-         10'b0011_0100_00,
-         10'b0011_0100_00,
-         10'b0011_0100_00,
-         10'b0010_1000_00,
-         10'b0010_1000_00,
-         10'b0010_1000_00,
-         10'b0010_1000_00,
-         10'b0010_1000_00,
-         10'b0111_0001_00,
-         10'b0111_0001_00,
-         10'b0100_1100_00,
-         10'b0100_1100_00,
-         10'b0100_1100_00,
-         10'b0100_1100_00,
-         10'b0110_0001_00,
-         10'b0110_0001_00,
-         10'b0101_0110_00,
-         10'b0101_0110_00,
-         10'b0101_0110_00,
-         10'b0010_0100_00,
-         10'b0010_0100_00,
-         10'b0010_0100_00,
-         10'b0010_0100_00,
-         10'b0100_1010_00,
-         10'b0011_1100_00,
-         10'b0011_1100_00
-      };
-      
-      // Set lookup_entry with the explicit bits from lookup with a part select
-      if(BANDWIDTH == "LOW") begin
-         // Low Bandwidth
-         mmcm_pll_filter_lookup = lookup_low[ ((64-divide)*10) +: 10];
-      end else begin
-         // High or optimized bandwidth
-         mmcm_pll_filter_lookup = lookup_high[ ((64-divide)*10) +: 10];
-      end
-      
-   `ifdef DEBUG
-      $display("filter_lookup: %b", mmcm_pll_filter_lookup);
-   `endif
-   end
-endfunction
-
-// This function takes in the divide, phase, and duty cycle
-// setting to calculate the upper and lower counter registers.
-function [37:0] mmcm_pll_count_calc
-   (
-      input [7:0] divide, // Max divide is 128
-      input signed [31:0] phase,
-      input [31:0] duty_cycle // Multiplied by 100,000
-   );
-   
-   reg [13:0] div_calc;
-   reg [16:0] phase_calc;
-   
-   begin
-   `ifdef DEBUG
-      $display("mmcm_pll_count_calc- divide:%h, phase:%d, duty_cycle:%d",
-         divide, phase, duty_cycle);
-   `endif
-   
-      // w_edge[13], no_count[12], high_time[11:6], low_time[5:0]
-      div_calc = mmcm_pll_divider(divide, duty_cycle);
-      // mx[10:9], pm[8:6], dt[5:0]
-      phase_calc = mmcm_pll_phase(divide, phase);
-
-      // Return value is the upper and lower address of counter
-      //    Upper address is:
-      //       RESERVED    [31:26]
-      //       MX          [25:24]
-      //       EDGE        [23]
-      //       NOCOUNT     [22]
-      //       DELAY_TIME  [21:16]
-      //    Lower Address is:
-      //       PHASE_MUX   [15:13]
-      //       RESERVED    [12]
-      //       HIGH_TIME   [11:6]
-      //       LOW_TIME    [5:0]
-      
-   `ifdef DEBUG
-      $display("div:%d dc:%d phase:%d ht:%d lt:%d ed:%d nc:%d mx:%d dt:%d pm:%d",
-         divide, duty_cycle, phase, div_calc[11:6], div_calc[5:0], 
-         div_calc[13], div_calc[12], 
-         phase_calc[16:15], phase_calc[5:0], phase_calc[14:12]);
-   `endif
-      
-      mmcm_pll_count_calc =
-         {
-            // Upper Address
-            6'h00, phase_calc[10:9], div_calc[13:12], phase_calc[5:0], 
-            // Lower Address
-            phase_calc[8:6], 1'b0, div_calc[11:0]
-         };
-   end
-endfunction
-
-
-// This function takes in the divide, phase, and duty cycle
-// setting to calculate the upper and lower counter registers.
-// for fractional multiply/divide functions.
-//
-// 
-function [37:0] mmcm_frac_count_calc
-   (
-      input [7:0] divide, // Max divide is 128
-      input signed [31:0] phase,
-      input [31:0] duty_cycle, // Multiplied by 1,000
-      input [9:0] frac // Multiplied by 1000
-   );
-   
-	//Required for fractional divide calculations
-			  reg	[7:0]			lt_frac;
-			  reg	[7:0]			ht_frac;
-			
-			  reg	/*[7:0]*/			wf_fall_frac;
-			  reg	/*[7:0]*/			wf_rise_frac;
-
-			  reg [31:0] a;
-			  reg	[7:0]			pm_rise_frac_filtered ;
-			  reg	[7:0]			pm_fall_frac_filtered ;	
-			  reg [7:0]			clkout0_divide_int;
-			  reg [2:0]			clkout0_divide_frac;
-			  reg	[7:0]			even_part_high;
-			  reg	[7:0]			even_part_low;
-
-			  reg	[7:0]			odd;
-			  reg	[7:0]			odd_and_frac;
-
-			  reg	[7:0]			pm_fall;
-			  reg	[7:0]			pm_rise;
-			  reg	[7:0]			dt;
-			  reg	[7:0]			dt_int; 
-			  reg [63:0]		dt_calc;
-
-			  reg	[7:0]			pm_rise_frac; 
-			  reg	[7:0]			pm_fall_frac;
-	 
-			  reg [31:0] a_per_in_octets;
-			  reg [31:0] a_phase_in_cycles;
-
-				parameter precision = 0.125;
-
-			  reg [31:0] phase_fixed; // changed to 31:0 from 32:1 jt 5/2/11
-			  reg [31: 0] phase_pos;
-			  reg [31: 0] phase_vco;
-			  reg [31:0] temp;// changed to 31:0 from 32:1 jt 5/2/11
-			  reg [13:0] div_calc;
-			  reg [16:0] phase_calc;
-
-   begin
-	`ifdef DEBUG
-			$display("mmcm_frac_count_calc- divide:%h, phase:%d, duty_cycle:%d",
-				divide, phase, duty_cycle);
-	`endif
-   
-   //convert phase to fixed
-   if ((phase < -360000) || (phase > 360000)) begin
-`ifndef SYNTHESIS
-      $display("ERROR: phase of $phase is not between -360000 and 360000");
-	`endif
-      $finish;
-   end
-
-
-      // Return value is
-      //    Transfer data
-      //       RESERVED     [37:36]
-      //       FRAC_TIME    [35:33]
-      //       FRAC_WF_FALL [32]
-      //    Upper address is:
-      //       RESERVED     [31:26]
-      //       MX           [25:24]
-      //       EDGE         [23]
-      //       NOCOUNT      [22]
-      //       DELAY_TIME   [21:16]
-      //    Lower Address is:
-      //       PHASE_MUX    [15:13]
-      //       RESERVED     [12]
-      //       HIGH_TIME    [11:6]
-      //       LOW_TIME     [5:0]
-      
-      
-
-	clkout0_divide_frac = frac / 125;
-	clkout0_divide_int = divide;
-
-	even_part_high = clkout0_divide_int >> 1;//$rtoi(clkout0_divide_int / 2);
-	even_part_low = even_part_high;
-									
-	odd = clkout0_divide_int - even_part_high - even_part_low;
-	odd_and_frac = (8*odd) + clkout0_divide_frac;
-
-	lt_frac = even_part_high - (odd_and_frac <= 9);//IF(odd_and_frac>9,even_part_high, even_part_high - 1)
-	ht_frac = even_part_low  - (odd_and_frac <= 8);//IF(odd_and_frac>8,even_part_low, even_part_low- 1)
-
-	pm_fall =  {odd[6:0],2'b00} + {6'h00, clkout0_divide_frac[2:1]}; // using >> instead of clkout0_divide_frac / 2 
-	pm_rise = 0; //0
-    
-	wf_fall_frac = ((odd_and_frac >=2) && (odd_and_frac <=9)) || ((clkout0_divide_frac == 1) && (clkout0_divide_int == 2));//CRS610807
-	wf_rise_frac = (odd_and_frac >=1) && (odd_and_frac <=8);//IF(odd_and_frac>=1,IF(odd_and_frac <= 8,1,0),0)
-
-
-
-	//Calculate phase in fractional cycles
-	a_per_in_octets		= (8 * divide) + (frac / 125) ;
-	a_phase_in_cycles	= (phase+10) * a_per_in_octets / 360000 ;//Adding 1 due to rounding errors
-	pm_rise_frac		= (a_phase_in_cycles[7:0] ==8'h00)?8'h00:a_phase_in_cycles[7:0] - {a_phase_in_cycles[7:3],3'b000};
-
-	dt_calc 	= ((phase+10) * a_per_in_octets / 8 )/360000 ;//TRUNC(phase* divide / 360); //or_simply (a_per_in_octets / 8)
-	dt 	= dt_calc[7:0];
-
-	pm_rise_frac_filtered = (pm_rise_frac >=8) ? (pm_rise_frac ) - 8: pm_rise_frac ;				//((phase_fixed * (divide + frac / 1000)) / 360) - {pm_rise_frac[7:3],3'b000};//$rtoi(clkout0_phase * clkout0_divide / 45);//a;
-
-	dt_int			= dt + (& pm_rise_frac[7:4]); //IF(pm_rise_overwriting>7,dt+1,dt)
-	pm_fall_frac		= pm_fall + pm_rise_frac;
-	pm_fall_frac_filtered	= pm_fall + pm_rise_frac - {pm_fall_frac[7:3], 3'b000};
-
-	div_calc	= mmcm_pll_divider(divide, duty_cycle); //Use to determine edge[7], no count[6]
-	phase_calc	= mmcm_pll_phase(divide, phase);// returns{mx[1:0], phase_mux[2:0], delay_time[5:0]}
-		
-      mmcm_frac_count_calc[37:0] =
-         {		2'b00, pm_fall_frac_filtered[2:0], wf_fall_frac,
-			1'b0, clkout0_divide_frac[2:0], 1'b1, wf_rise_frac, phase_calc[10:9], div_calc[13:12], dt[5:0], 
-			pm_rise_frac_filtered[2], pm_rise_frac_filtered[1], pm_rise_frac_filtered[0], 1'b0, ht_frac[5:0], lt_frac[5:0]
-		} ;
-
-   `ifdef DEBUG
-      $display("-%d.%d p%d>>  :DADDR_9_15 frac30to28.frac_en.wf_r_frac.dt:%b%d%d_%b:DADDR_7_13 pm_f_frac_filtered_29to27.wf_f_frac_26:%b%d:DADDR_8_14.pm_r_frac_filt_15to13.ht_frac.lt_frac:%b%b%b:", divide, frac, phase, clkout0_divide_frac, 1, wf_rise_frac, dt, pm_fall_frac_filtered, wf_fall_frac, pm_rise_frac_filtered, ht_frac, lt_frac);
-   `endif
-
-   end
-endfunction
-

LAB2/src/pak_depak/ipshared/d0f7/mmcm_pll_drp_func_7s_pll.vh

@@ -1,531 +0,0 @@
-///////////////////////////////////////////////////////////////////////////////
-//    
-//    Company:          Xilinx
-//    Engineer:         Jim Tatsukawa, Karl Kurbjun and Carl Ribbing
-//    Date:             7/30/2014
-//    Design Name:      PLLE2 DRP
-//    Module Name:      plle2_drp_func.h
-//    Version:          2.00
-//    Target Devices:   7 Series || PLL
-//    Tool versions:    2014.3
-//    Description:      This header provides the functions necessary to  
-//                      calculate the DRP register values for the V6 PLL.
-//                      Updated for CR663854.
-// 
-//    Disclaimer:  XILINX IS PROVIDING THIS DESIGN, CODE, OR
-//                 INFORMATION "AS IS" SOLELY FOR USE IN DEVELOPING
-//                 PROGRAMS AND SOLUTIONS FOR XILINX DEVICES.  BY
-//                 PROVIDING THIS DESIGN, CODE, OR INFORMATION AS
-//                 ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE,
-//                 APPLICATION OR STANDARD, XILINX IS MAKING NO
-//                 REPRESENTATION THAT THIS IMPLEMENTATION IS FREE
-//                 FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE
-//                 RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY
-//                 REQUIRE FOR YOUR IMPLEMENTATION.  XILINX
-//                 EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH
-//                 RESPECT TO THE ADEQUACY OF THE IMPLEMENTATION,
-//                 INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR
-//                 REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE
-//                 FROM CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES
-//                 OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-//                 PURPOSE.
-// 
-//                 (c) Copyright 2009-2010 Xilinx, Inc.
-//                 All rights reserved.
-// 
-///////////////////////////////////////////////////////////////////////////////
-
-// These are user functions that should not be modified.  Changes to the defines
-// or code within the functions may alter the accuracy of the calculations.
-
-// Define debug to provide extra messages durring elaboration
-//`define DEBUG 1
-
-// FRAC_PRECISION describes the width of the fractional portion of the fixed
-//    point numbers.  These should not be modified, they are for development 
-//    only
-`define FRAC_PRECISION  10
-// FIXED_WIDTH describes the total size for fixed point calculations(int+frac).
-// Warning: L.50 and below will not calculate properly with FIXED_WIDTHs 
-//    greater than 32
-`define FIXED_WIDTH     32 
-
-// This function takes a fixed point number and rounds it to the nearest
-//    fractional precision bit.
-function [`FIXED_WIDTH:1] round_frac
-   (
-      // Input is (FIXED_WIDTH-FRAC_PRECISION).FRAC_PRECISION fixed point number
-      input [`FIXED_WIDTH:1] decimal,  
-
-      // This describes the precision of the fraction, for example a value
-      //    of 1 would modify the fractional so that instead of being a .16
-      //    fractional, it would be a .1 (rounded to the nearest 0.5 in turn)
-      input [`FIXED_WIDTH:1] precision 
-   );
-
-   begin
-   
-`ifdef DEBUG
-      $display("round_frac - decimal: %h, precision: %h", decimal, precision);
-`endif
-      // If the fractional precision bit is high then round up
-      if( decimal[(`FRAC_PRECISION-precision)] == 1'b1) begin
-         round_frac = decimal + (1'b1 << (`FRAC_PRECISION-precision));
-      end else begin
-         round_frac = decimal;
-      end
-`ifdef DEBUG
-      $display("round_frac: %h", round_frac);
-`endif
-   end
-endfunction
-
-// This function calculates high_time, low_time, w_edge, and no_count
-//    of a non-fractional counter based on the divide and duty cycle
-//
-// NOTE: high_time and low_time are returned as integers between 0 and 63 
-//    inclusive.  64 should equal 6'b000000 (in other words it is okay to 
-//    ignore the overflow)
-function [13:0] mmcm_pll_divider
-   (
-      input [7:0] divide,        // Max divide is 128
-      input [31:0] duty_cycle    // Duty cycle is multiplied by 100,000
-   );
-
-   reg [`FIXED_WIDTH:1]    duty_cycle_fix;
-   
-   // High/Low time is initially calculated with a wider integer to prevent a
-   // calculation error when it overflows to 64.
-   reg [6:0]               high_time;
-   reg [6:0]               low_time;
-   reg                     w_edge;
-   reg                     no_count;
-
-   reg [`FIXED_WIDTH:1]    temp;
-
-   begin
-      // Duty Cycle must be between 0 and 1,000
-      if(duty_cycle <=0 || duty_cycle >= 100000) begin
-`ifndef SYNTHESIS
-         $display("ERROR: duty_cycle: %d is invalid", duty_cycle);
-   `endif
-         $finish;
-      end
-
-      // Convert to FIXED_WIDTH-FRAC_PRECISION.FRAC_PRECISION fixed point
-      duty_cycle_fix = (duty_cycle << `FRAC_PRECISION) / 100_000;
-      
-`ifdef DEBUG
-      $display("duty_cycle_fix: %h", duty_cycle_fix);
-`endif
-
-      // If the divide is 1 nothing needs to be set except the no_count bit.
-      //    Other values are dummies
-      if(divide == 7'h01) begin
-         high_time   = 7'h01;
-         w_edge      = 1'b0;
-         low_time    = 7'h01;
-         no_count    = 1'b1;
-      end else begin
-         temp = round_frac(duty_cycle_fix*divide, 1);
-
-         // comes from above round_frac
-         high_time   = temp[`FRAC_PRECISION+7:`FRAC_PRECISION+1]; 
-         // If the duty cycle * divide rounded is .5 or greater then this bit
-         //    is set.
-         w_edge      = temp[`FRAC_PRECISION]; // comes from round_frac
-         
-         // If the high time comes out to 0, it needs to be set to at least 1
-         // and w_edge set to 0
-         if(high_time == 7'h00) begin
-            high_time   = 7'h01;
-            w_edge      = 1'b0;
-         end
-
-         if(high_time == divide) begin
-            high_time   = divide - 1;
-            w_edge      = 1'b1;
-         end
-         
-         // Calculate low_time based on the divide setting and set no_count to
-         //    0 as it is only used when divide is 1.
-         low_time    = divide - high_time; 
-         no_count    = 1'b0;
-      end
-
-      // Set the return value.
-      mmcm_pll_divider = {w_edge,no_count,high_time[5:0],low_time[5:0]};
-   end
-endfunction
-
-// This function calculates mx, delay_time, and phase_mux 
-//  of a non-fractional counter based on the divide and phase
-//
-// NOTE: The only valid value for the MX bits is 2'b00 to ensure the coarse mux
-//    is used.
-function [10:0] mmcm_pll_phase
-   (
-      // divide must be an integer (use fractional if not)
-      //  assumed that divide already checked to be valid
-      input [7:0] divide, // Max divide is 128
-
-      // Phase is given in degrees (-360,000 to 360,000)
-      input signed [31:0] phase
-   );
-
-   reg [`FIXED_WIDTH:1] phase_in_cycles;
-   reg [`FIXED_WIDTH:1] phase_fixed;
-   reg [1:0]            mx;
-   reg [5:0]            delay_time;
-   reg [2:0]            phase_mux;
-
-   reg [`FIXED_WIDTH:1] temp;
-
-   begin
-`ifdef DEBUG
-      $display("mmcm_pll_phase-divide:%d,phase:%d",
-         divide, phase);
-`endif
-   
-      if ((phase < -360000) || (phase > 360000)) begin
-`ifndef SYNTHESIS
-      $display("ERROR: phase of $phase is not between -360000 and 360000");
-	`endif
-         $finish;
-      end
-
-      // If phase is less than 0, convert it to a positive phase shift
-      // Convert to (FIXED_WIDTH-FRAC_PRECISION).FRAC_PRECISION fixed point
-      if(phase < 0) begin
-         phase_fixed = ( (phase + 360000) << `FRAC_PRECISION ) / 1000;
-      end else begin
-         phase_fixed = ( phase << `FRAC_PRECISION ) / 1000;
-      end
-
-      // Put phase in terms of decimal number of vco clock cycles
-      phase_in_cycles = ( phase_fixed * divide ) / 360;
-
-`ifdef DEBUG
-      $display("phase_in_cycles: %h", phase_in_cycles);
-`endif  
-      
-
-	 temp  =  round_frac(phase_in_cycles, 3);
-
-	 // set mx to 2'b00 that the phase mux from the VCO is enabled
-	 mx    			=  2'b00; 
-	 phase_mux      =  temp[`FRAC_PRECISION:`FRAC_PRECISION-2];
-	 delay_time     =  temp[`FRAC_PRECISION+6:`FRAC_PRECISION+1];
-      
-`ifdef DEBUG
-      $display("temp: %h", temp);
-`endif
-
-      // Setup the return value
-      mmcm_pll_phase={mx, phase_mux, delay_time};
-   end
-endfunction
-
-// This function takes the divide value and outputs the necessary lock values
-function [39:0] mmcm_pll_lock_lookup
-   (
-      input [6:0] divide // Max divide is 64
-   );
-   
-   reg [2559:0]   lookup;
-   
-   begin
-      lookup = {
-         // This table is composed of:
-         // LockRefDly_LockFBDly_LockCnt_LockSatHigh_UnlockCnt
-         40'b00110_00110_1111101000_1111101001_0000000001,
-         40'b00110_00110_1111101000_1111101001_0000000001,
-         40'b01000_01000_1111101000_1111101001_0000000001,
-         40'b01011_01011_1111101000_1111101001_0000000001,
-         40'b01110_01110_1111101000_1111101001_0000000001,
-         40'b10001_10001_1111101000_1111101001_0000000001,
-         40'b10011_10011_1111101000_1111101001_0000000001,
-         40'b10110_10110_1111101000_1111101001_0000000001,
-         40'b11001_11001_1111101000_1111101001_0000000001,
-         40'b11100_11100_1111101000_1111101001_0000000001,
-         40'b11111_11111_1110000100_1111101001_0000000001,
-         40'b11111_11111_1100111001_1111101001_0000000001,
-         40'b11111_11111_1011101110_1111101001_0000000001,
-         40'b11111_11111_1010111100_1111101001_0000000001,
-         40'b11111_11111_1010001010_1111101001_0000000001,
-         40'b11111_11111_1001110001_1111101001_0000000001,
-         40'b11111_11111_1000111111_1111101001_0000000001,
-         40'b11111_11111_1000100110_1111101001_0000000001,
-         40'b11111_11111_1000001101_1111101001_0000000001,
-         40'b11111_11111_0111110100_1111101001_0000000001,
-         40'b11111_11111_0111011011_1111101001_0000000001,
-         40'b11111_11111_0111000010_1111101001_0000000001,
-         40'b11111_11111_0110101001_1111101001_0000000001,
-         40'b11111_11111_0110010000_1111101001_0000000001,
-         40'b11111_11111_0110010000_1111101001_0000000001,
-         40'b11111_11111_0101110111_1111101001_0000000001,
-         40'b11111_11111_0101011110_1111101001_0000000001,
-         40'b11111_11111_0101011110_1111101001_0000000001,
-         40'b11111_11111_0101000101_1111101001_0000000001,
-         40'b11111_11111_0101000101_1111101001_0000000001,
-         40'b11111_11111_0100101100_1111101001_0000000001,
-         40'b11111_11111_0100101100_1111101001_0000000001,
-         40'b11111_11111_0100101100_1111101001_0000000001,
-         40'b11111_11111_0100010011_1111101001_0000000001,
-         40'b11111_11111_0100010011_1111101001_0000000001,
-         40'b11111_11111_0100010011_1111101001_0000000001,
-         40'b11111_11111_0011111010_1111101001_0000000001,
-         40'b11111_11111_0011111010_1111101001_0000000001,
-         40'b11111_11111_0011111010_1111101001_0000000001,
-         40'b11111_11111_0011111010_1111101001_0000000001,
-         40'b11111_11111_0011111010_1111101001_0000000001,
-         40'b11111_11111_0011111010_1111101001_0000000001,
-         40'b11111_11111_0011111010_1111101001_0000000001,
-         40'b11111_11111_0011111010_1111101001_0000000001,
-         40'b11111_11111_0011111010_1111101001_0000000001,
-         40'b11111_11111_0011111010_1111101001_0000000001,
-         40'b11111_11111_0011111010_1111101001_0000000001,
-         40'b11111_11111_0011111010_1111101001_0000000001,
-         40'b11111_11111_0011111010_1111101001_0000000001,
-         40'b11111_11111_0011111010_1111101001_0000000001,
-         40'b11111_11111_0011111010_1111101001_0000000001,
-         40'b11111_11111_0011111010_1111101001_0000000001,
-         40'b11111_11111_0011111010_1111101001_0000000001,
-         40'b11111_11111_0011111010_1111101001_0000000001,
-         40'b11111_11111_0011111010_1111101001_0000000001,
-         40'b11111_11111_0011111010_1111101001_0000000001,
-         40'b11111_11111_0011111010_1111101001_0000000001,
-         40'b11111_11111_0011111010_1111101001_0000000001,
-         40'b11111_11111_0011111010_1111101001_0000000001,
-         40'b11111_11111_0011111010_1111101001_0000000001,
-         40'b11111_11111_0011111010_1111101001_0000000001,
-         40'b11111_11111_0011111010_1111101001_0000000001,
-         40'b11111_11111_0011111010_1111101001_0000000001,
-         40'b11111_11111_0011111010_1111101001_0000000001
-      };
-      
-      // Set lookup_entry with the explicit bits from lookup with a part select
-      mmcm_pll_lock_lookup = lookup[ ((64-divide)*40) +: 40];
-   `ifdef DEBUG
-      $display("lock_lookup: %b", mmcm_pll_lock_lookup);
-   `endif
-   end
-endfunction
-
-// This function takes the divide value and the bandwidth setting of the PLL
-//  and outputs the digital filter settings necessary.
-function [9:0] mmcm_pll_filter_lookup
-   (
-      input [6:0] divide, // Max divide is 64
-      input [8*9:0] BANDWIDTH
-   );
-   
-   reg [639:0] lookup_low;
-   reg [639:0] lookup_high;
-   
-   reg [9:0] lookup_entry;
-   
-   begin
-      lookup_low = {
-         // CP_RES_LFHF
-         10'b0010_1111_00,
-         10'b0010_1111_00,
-         10'b0010_0111_00,
-         10'b0010_1101_00,
-         10'b0010_0101_00,
-         10'b0010_0101_00,
-         10'b0010_1001_00,
-         10'b0010_1110_00,
-         10'b0010_1110_00,
-         10'b0010_0001_00,
-         10'b0010_0001_00,
-         10'b0010_0110_00,
-         10'b0010_0110_00,
-         10'b0010_0110_00,
-         10'b0010_0110_00,
-         10'b0010_1010_00,
-         10'b0010_1010_00,
-         10'b0010_1010_00,
-         10'b0010_1010_00,
-         10'b0010_1100_00,
-         10'b0010_1100_00,
-         10'b0010_1100_00,
-         10'b0010_1100_00,
-         10'b0010_1100_00,
-         10'b0010_1100_00,
-         10'b0010_1100_00,
-         10'b0010_1100_00,
-         10'b0010_1100_00,
-         10'b0010_1100_00,
-         10'b0010_1100_00,
-         10'b0010_0010_00,
-         10'b0010_0010_00,
-         10'b0010_0010_00,
-         10'b0010_0010_00,
-         10'b0010_0010_00,
-         10'b0010_0010_00,
-         10'b0010_0010_00,
-         10'b0010_0010_00,
-         10'b0010_0010_00,
-         10'b0010_0010_00,
-         10'b0011_1100_00,
-         10'b0011_1100_00,
-         10'b0011_1100_00,
-         10'b0011_1100_00,
-         10'b0011_1100_00,
-         10'b0011_1100_00,
-         10'b0011_1100_00,
-         10'b0010_0100_00,
-         10'b0010_0100_00,
-         10'b0010_0100_00,
-         10'b0010_0100_00,
-         10'b0010_0100_00,
-         10'b0010_0100_00,
-         10'b0010_0100_00,
-         10'b0010_0100_00,
-         10'b0010_0100_00,
-         10'b0010_0100_00,
-         10'b0010_0100_00,
-         10'b0010_0100_00,
-         10'b0010_0100_00,
-         10'b0010_0100_00,
-         10'b0010_0100_00,
-         10'b0010_0100_00,
-         10'b0010_0100_00
-      };
-      
-      lookup_high = {
-         // CP_RES_LFHF
-         10'b0011_0111_00,
-         10'b0011_0111_00,
-         10'b0101_1111_00,
-         10'b0111_1111_00,
-         10'b0111_1011_00,
-         10'b1101_0111_00,
-         10'b1110_1011_00,
-         10'b1110_1101_00,
-         10'b1111_1101_00,
-         10'b1111_0111_00,
-         10'b1111_1011_00,
-         10'b1111_1101_00,
-         10'b1111_0011_00,
-         10'b1110_0101_00,
-         10'b1111_0101_00,
-         10'b1111_0101_00,
-         10'b1111_0101_00,
-         10'b1111_0101_00,
-         10'b0111_0110_00,
-         10'b0111_0110_00,
-         10'b0111_0110_00,
-         10'b0111_0110_00,
-         10'b0101_1100_00,
-         10'b0101_1100_00,
-         10'b0101_1100_00,
-         10'b1100_0001_00,
-         10'b1100_0001_00,
-         10'b1100_0001_00,
-         10'b1100_0001_00,
-         10'b1100_0001_00,
-         10'b1100_0001_00,
-         10'b1100_0001_00,
-         10'b1100_0001_00,
-         10'b0100_0010_00,
-         10'b0100_0010_00,
-         10'b0100_0010_00,
-         10'b0010_1000_00,
-         10'b0010_1000_00,
-         10'b0010_1000_00,
-         10'b0011_0100_00,
-         10'b0010_1000_00,
-         10'b0010_1000_00,
-         10'b0010_1000_00,
-         10'b0010_1000_00,
-         10'b0010_1000_00,
-         10'b0010_1000_00,
-         10'b0010_1000_00,
-         10'b0010_1000_00,
-         10'b0010_1000_00,
-         10'b0010_1000_00,
-         10'b0010_1000_00,
-         10'b0010_1000_00,
-         10'b0010_1000_00,
-         10'b0100_1100_00,
-         10'b0100_1100_00,
-         10'b0100_1100_00,
-         10'b0100_1100_00,
-         10'b0100_1100_00,
-         10'b0100_1100_00,
-         10'b0100_1100_00,
-         10'b0010_0100_00,
-         10'b0010_0100_00,
-         10'b0010_0100_00,
-         10'b0010_0100_00
-      };
-      
-      // Set lookup_entry with the explicit bits from lookup with a part select
-      if(BANDWIDTH == "LOW") begin
-         // Low Bandwidth
-         mmcm_pll_filter_lookup = lookup_low[ ((64-divide)*10) +: 10];
-      end else begin
-         // High or optimized bandwidth
-         mmcm_pll_filter_lookup = lookup_high[ ((64-divide)*10) +: 10];
-      end
-      
-   `ifdef DEBUG
-      $display("filter_lookup: %b", mmcm_pll_filter_lookup);
-   `endif
-   end
-endfunction
-
-// This function takes in the divide, phase, and duty cycle
-// setting to calculate the upper and lower counter registers.
-function [37:0] mmcm_pll_count_calc
-   (
-      input [7:0] divide, // Max divide is 128
-      input signed [31:0] phase,
-      input [31:0] duty_cycle // Multiplied by 100,000
-   );
-   
-   reg [13:0] div_calc;
-   reg [16:0] phase_calc;
-   
-   begin
-   `ifdef DEBUG
-      $display("mmcm_pll_count_calc- divide:%h, phase:%d, duty_cycle:%d",
-         divide, phase, duty_cycle);
-`endif
-   
-      // w_edge[13], no_count[12], high_time[11:6], low_time[5:0]
-      div_calc = mmcm_pll_divider(divide, duty_cycle);
-      // mx[10:9], pm[8:6], dt[5:0]
-      phase_calc = mmcm_pll_phase(divide, phase);
-
-      // Return value is the upper and lower address of counter
-      //    Upper address is:
-      //       RESERVED    [31:26]
-      //       MX          [25:24]
-      //       EDGE        [23]
-      //       NOCOUNT     [22]
-      //       DELAY_TIME  [21:16]
-      //    Lower Address is:
-      //       PHASE_MUX   [15:13]
-      //       RESERVED    [12]
-      //       HIGH_TIME   [11:6]
-      //       LOW_TIME    [5:0]
-      
-`ifdef DEBUG
-      $display("div:%d dc:%d phase:%d ht:%d lt:%d ed:%d nc:%d mx:%d dt:%d pm:%d",
-         divide, duty_cycle, phase, div_calc[11:6], div_calc[5:0], 
-         div_calc[13], div_calc[12], 
-         phase_calc[16:15], phase_calc[5:0], phase_calc[14:12]);
-`endif
-      
-      mmcm_pll_count_calc =
-         {
-            // Upper Address
-            6'h00, phase_calc[10:9], div_calc[13:12], phase_calc[5:0], 
-            // Lower Address
-            phase_calc[8:6], 1'b0, div_calc[11:0]
-         };
-   end
-endfunction

LAB2/src/pak_depak/ipshared/d0f7/mmcm_pll_drp_func_us_mmcm.vh

@@ -1,671 +0,0 @@
-///////////////////////////////////////////////////////////////////////////////
-//    
-//    Company:          Xilinx
-//    Engineer:         Jim Tatsukawa
-//    Date:             7/30/2014
-//    Design Name:      MMCME2 DRP
-//    Module Name:      mmcme2_drp_func.h
-//    Version:          1.04
-//    Target Devices:   UltraScale Architecture || MMCM 
-//    Tool versions:    2014.3
-//    Description:      This header provides the functions necessary to  
-//                      calculate the DRP register values for the V6 MMCM.
-//                      
-//	Revision Notes:	3/22 - Updating lookup_low/lookup_high (CR)
-//				4/13 - Fractional divide function in mmcm_frac_count_calc function. CRS610807
-// 
-//    Disclaimer:  XILINX IS PROVIDING THIS DESIGN, CODE, OR
-//                 INFORMATION "AS IS" SOLELY FOR USE IN DEVELOPING
-//                 PROGRAMS AND SOLUTIONS FOR XILINX DEVICES.  BY
-//                 PROVIDING THIS DESIGN, CODE, OR INFORMATION AS
-//                 ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE,
-//                 APPLICATION OR STANDARD, XILINX IS MAKING NO
-//                 REPRESENTATION THAT THIS IMPLEMENTATION IS FREE
-//                 FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE
-//                 RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY
-//                 REQUIRE FOR YOUR IMPLEMENTATION.  XILINX
-//                 EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH
-//                 RESPECT TO THE ADEQUACY OF THE IMPLEMENTATION,
-//                 INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR
-//                 REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE
-//                 FROM CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES
-//                 OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-//                 PURPOSE.
-// 
-//                 (c) Copyright 2009-2010 Xilinx, Inc.
-//                 All rights reserved.
-// 
-///////////////////////////////////////////////////////////////////////////////
-
-// These are user functions that should not be modified.  Changes to the defines
-// or code within the functions may alter the accuracy of the calculations.
-
-// Define debug to provide extra messages durring elaboration
-//`define DEBUG 1
-
-// FRAC_PRECISION describes the width of the fractional portion of the fixed
-//    point numbers.  These should not be modified, they are for development 
-//    only
-`define FRAC_PRECISION  10
-// FIXED_WIDTH describes the total size for fixed point calculations(int+frac).
-// Warning: L.50 and below will not calculate properly with FIXED_WIDTHs 
-//    greater than 32
-`define FIXED_WIDTH     32 
-
-// This function takes a fixed point number and rounds it to the nearest
-//    fractional precision bit.
-function [`FIXED_WIDTH:1] round_frac
-   (
-      // Input is (FIXED_WIDTH-FRAC_PRECISION).FRAC_PRECISION fixed point number
-      input [`FIXED_WIDTH:1] decimal,  
-
-      // This describes the precision of the fraction, for example a value
-      //    of 1 would modify the fractional so that instead of being a .16
-      //    fractional, it would be a .1 (rounded to the nearest 0.5 in turn)
-      input [`FIXED_WIDTH:1] precision 
-   );
-
-   begin
-   
-   `ifdef DEBUG
-      $display("round_frac - decimal: %h, precision: %h", decimal, precision);
-   `endif
-      // If the fractional precision bit is high then round up
-      if( decimal[(`FRAC_PRECISION-precision)] == 1'b1) begin
-         round_frac = decimal + (1'b1 << (`FRAC_PRECISION-precision));
-      end else begin
-         round_frac = decimal;
-      end
-   `ifdef DEBUG
-      $display("round_frac: %h", round_frac);
-   `endif
-   end
-endfunction
-
-// This function calculates high_time, low_time, w_edge, and no_count
-//    of a non-fractional counter based on the divide and duty cycle
-//
-// NOTE: high_time and low_time are returned as integers between 0 and 63 
-//    inclusive.  64 should equal 6'b000000 (in other words it is okay to 
-//    ignore the overflow)
-function [13:0] mmcm_pll_divider
-   (
-      input [7:0] divide,        // Max divide is 128
-      input [31:0] duty_cycle    // Duty cycle is multiplied by 100,000
-   );
-
-   reg [`FIXED_WIDTH:1]    duty_cycle_fix;
-   
-   // High/Low time is initially calculated with a wider integer to prevent a
-   // calculation error when it overflows to 64.
-   reg [6:0]               high_time;
-   reg [6:0]               low_time;
-   reg                     w_edge;
-   reg                     no_count;
-
-   reg [`FIXED_WIDTH:1]    temp;
-
-   begin
-      // Duty Cycle must be between 0 and 1,000
-      if(duty_cycle <=0 || duty_cycle >= 100000) begin
-`ifndef SYNTHESIS
-         $display("ERROR: duty_cycle: %d is invalid", duty_cycle);
-   `endif
-         $finish;
-      end
-
-      // Convert to FIXED_WIDTH-FRAC_PRECISION.FRAC_PRECISION fixed point
-      duty_cycle_fix = (duty_cycle << `FRAC_PRECISION) / 100_000;
-      
-   `ifdef DEBUG
-      $display("duty_cycle_fix: %h", duty_cycle_fix);
-   `endif
-
-      // If the divide is 1 nothing needs to be set except the no_count bit.
-      //    Other values are dummies
-      if(divide == 7'h01) begin
-         high_time   = 7'h01;
-         w_edge      = 1'b0;
-         low_time    = 7'h01;
-         no_count    = 1'b1;
-      end else begin
-         temp = round_frac(duty_cycle_fix*divide, 1);
-
-         // comes from above round_frac
-         high_time   = temp[`FRAC_PRECISION+7:`FRAC_PRECISION+1]; 
-         // If the duty cycle * divide rounded is .5 or greater then this bit
-         //    is set.
-         w_edge      = temp[`FRAC_PRECISION]; // comes from round_frac
-         
-         // If the high time comes out to 0, it needs to be set to at least 1
-         // and w_edge set to 0
-         if(high_time == 7'h00) begin
-            high_time   = 7'h01;
-            w_edge      = 1'b0;
-         end
-
-         if(high_time == divide) begin
-            high_time   = divide - 1;
-            w_edge      = 1'b1;
-         end
-         
-         // Calculate low_time based on the divide setting and set no_count to
-         //    0 as it is only used when divide is 1.
-         low_time    = divide - high_time; 
-         no_count    = 1'b0;
-      end
-
-      // Set the return value.
-      mmcm_pll_divider = {w_edge,no_count,high_time[5:0],low_time[5:0]};
-   end
-endfunction
-
-// This function calculates mx, delay_time, and phase_mux 
-//  of a non-fractional counter based on the divide and phase
-//
-// NOTE: The only valid value for the MX bits is 2'b00 to ensure the coarse mux
-//    is used.
-function [10:0] mmcm_pll_phase
-   (
-      // divide must be an integer (use fractional if not)
-      //  assumed that divide already checked to be valid
-      input [7:0] divide, // Max divide is 128
-
-      // Phase is given in degrees (-360,000 to 360,000)
-      input signed [31:0] phase
-   );
-
-   reg [`FIXED_WIDTH:1] phase_in_cycles;
-   reg [`FIXED_WIDTH:1] phase_fixed;
-   reg [1:0]            mx;
-   reg [5:0]            delay_time;
-   reg [2:0]            phase_mux;
-
-   reg [`FIXED_WIDTH:1] temp;
-
-   begin
-`ifdef DEBUG
-      $display("mmcm_pll_phase-divide:%d,phase:%d",
-         divide, phase);
-`endif
-   
-      if ((phase < -360000) || (phase > 360000)) begin
-`ifndef SYNTHESIS
-      $display("ERROR: phase of $phase is not between -360000 and 360000");
-	`endif
-         $finish;
-      end
-
-      // If phase is less than 0, convert it to a positive phase shift
-      // Convert to (FIXED_WIDTH-FRAC_PRECISION).FRAC_PRECISION fixed point
-      if(phase < 0) begin
-         phase_fixed = ( (phase + 360000) << `FRAC_PRECISION ) / 1000;
-      end else begin
-         phase_fixed = ( phase << `FRAC_PRECISION ) / 1000;
-      end
-
-      // Put phase in terms of decimal number of vco clock cycles
-      phase_in_cycles = ( phase_fixed * divide ) / 360;
-
-`ifdef DEBUG
-      $display("phase_in_cycles: %h", phase_in_cycles);
-`endif  
-      
-
-	 temp  =  round_frac(phase_in_cycles, 3);
-
-	 // set mx to 2'b00 that the phase mux from the VCO is enabled
-	 mx    			=  2'b00; 
-	 phase_mux      =  temp[`FRAC_PRECISION:`FRAC_PRECISION-2];
-	 delay_time     =  temp[`FRAC_PRECISION+6:`FRAC_PRECISION+1];
-      
-   `ifdef DEBUG
-      $display("temp: %h", temp);
-   `endif
-
-      // Setup the return value
-      mmcm_pll_phase={mx, phase_mux, delay_time};
-   end
-endfunction
-
-// This function takes the divide value and outputs the necessary lock values
-function [39:0] mmcm_pll_lock_lookup
-   (
-      input [6:0] divide // Max divide is 64
-   );
-   
-   reg [2559:0]   lookup;
-   
-   begin
-      lookup = {
-         // This table is composed of:
-         // LockRefDly_LockFBDly_LockCnt_LockSatHigh_UnlockCnt
-         40'b00110_00110_1111101000_1111101001_0000000001,
-         40'b00110_00110_1111101000_1111101001_0000000001,
-         40'b01000_01000_1111101000_1111101001_0000000001,
-         40'b01011_01011_1111101000_1111101001_0000000001,
-         40'b01110_01110_1111101000_1111101001_0000000001,
-         40'b10001_10001_1111101000_1111101001_0000000001,
-         40'b10011_10011_1111101000_1111101001_0000000001,
-         40'b10110_10110_1111101000_1111101001_0000000001,
-         40'b11001_11001_1111101000_1111101001_0000000001,
-         40'b11100_11100_1111101000_1111101001_0000000001,
-         40'b11111_11111_1110000100_1111101001_0000000001,
-         40'b11111_11111_1100111001_1111101001_0000000001,
-         40'b11111_11111_1011101110_1111101001_0000000001,
-         40'b11111_11111_1010111100_1111101001_0000000001,
-         40'b11111_11111_1010001010_1111101001_0000000001,
-         40'b11111_11111_1001110001_1111101001_0000000001,
-         40'b11111_11111_1000111111_1111101001_0000000001,
-         40'b11111_11111_1000100110_1111101001_0000000001,
-         40'b11111_11111_1000001101_1111101001_0000000001,
-         40'b11111_11111_0111110100_1111101001_0000000001,
-         40'b11111_11111_0111011011_1111101001_0000000001,
-         40'b11111_11111_0111000010_1111101001_0000000001,
-         40'b11111_11111_0110101001_1111101001_0000000001,
-         40'b11111_11111_0110010000_1111101001_0000000001,
-         40'b11111_11111_0110010000_1111101001_0000000001,
-         40'b11111_11111_0101110111_1111101001_0000000001,
-         40'b11111_11111_0101011110_1111101001_0000000001,
-         40'b11111_11111_0101011110_1111101001_0000000001,
-         40'b11111_11111_0101000101_1111101001_0000000001,
-         40'b11111_11111_0101000101_1111101001_0000000001,
-         40'b11111_11111_0100101100_1111101001_0000000001,
-         40'b11111_11111_0100101100_1111101001_0000000001,
-         40'b11111_11111_0100101100_1111101001_0000000001,
-         40'b11111_11111_0100010011_1111101001_0000000001,
-         40'b11111_11111_0100010011_1111101001_0000000001,
-         40'b11111_11111_0100010011_1111101001_0000000001,
-         40'b11111_11111_0011111010_1111101001_0000000001,
-         40'b11111_11111_0011111010_1111101001_0000000001,
-         40'b11111_11111_0011111010_1111101001_0000000001,
-         40'b11111_11111_0011111010_1111101001_0000000001,
-         40'b11111_11111_0011111010_1111101001_0000000001,
-         40'b11111_11111_0011111010_1111101001_0000000001,
-         40'b11111_11111_0011111010_1111101001_0000000001,
-         40'b11111_11111_0011111010_1111101001_0000000001,
-         40'b11111_11111_0011111010_1111101001_0000000001,
-         40'b11111_11111_0011111010_1111101001_0000000001,
-         40'b11111_11111_0011111010_1111101001_0000000001,
-         40'b11111_11111_0011111010_1111101001_0000000001,
-         40'b11111_11111_0011111010_1111101001_0000000001,
-         40'b11111_11111_0011111010_1111101001_0000000001,
-         40'b11111_11111_0011111010_1111101001_0000000001,
-         40'b11111_11111_0011111010_1111101001_0000000001,
-         40'b11111_11111_0011111010_1111101001_0000000001,
-         40'b11111_11111_0011111010_1111101001_0000000001,
-         40'b11111_11111_0011111010_1111101001_0000000001,
-         40'b11111_11111_0011111010_1111101001_0000000001,
-         40'b11111_11111_0011111010_1111101001_0000000001,
-         40'b11111_11111_0011111010_1111101001_0000000001,
-         40'b11111_11111_0011111010_1111101001_0000000001,
-         40'b11111_11111_0011111010_1111101001_0000000001,
-         40'b11111_11111_0011111010_1111101001_0000000001,
-         40'b11111_11111_0011111010_1111101001_0000000001,
-         40'b11111_11111_0011111010_1111101001_0000000001,
-         40'b11111_11111_0011111010_1111101001_0000000001
-      };
-      
-      // Set lookup_entry with the explicit bits from lookup with a part select
-      mmcm_pll_lock_lookup = lookup[ ((64-divide)*40) +: 40];
-   `ifdef DEBUG
-      $display("lock_lookup: %b", mmcm_pll_lock_lookup);
-   `endif
-   end
-endfunction
-
-// This function takes the divide value and the bandwidth setting of the MMCM
-//  and outputs the digital filter settings necessary.
-function [9:0] mmcm_pll_filter_lookup
-   (
-      input [6:0] divide, // Max divide is 64
-      input [8*9:0] BANDWIDTH
-   );
-   
-   reg [639:0] lookup_low;
-   reg [639:0] lookup_high;
-   
-   reg [9:0] lookup_entry;
-   
-   begin
-      lookup_low = {
-         // CP_RES_LFHF
-         10'b0010_1111_11,
-         10'b0010_1111_11,
-         10'b0010_1111_11,
-         10'b0010_1111_11,
-         10'b0010_1111_11,
-         10'b0010_1111_11,
-         10'b0010_0111_11,
-         10'b0010_0111_11,
-         10'b0010_0111_11,
-         10'b0010_1101_11,
-         10'b0010_1101_11,
-         10'b0010_1101_11,
-         10'b0010_0011_11,
-         10'b0010_0101_11,
-         10'b0010_0101_11,
-         10'b0010_0101_11,
-         10'b0010_1001_11,
-         10'b0010_1001_11,
-         10'b0010_1110_11,
-         10'b0010_1110_11,
-         10'b0010_1110_11,
-         10'b0010_1110_11,
-         10'b0010_1110_11,
-         10'b0010_1110_11,
-         10'b0010_0001_11,
-         10'b0010_0001_11,
-         10'b0010_0001_11,
-         10'b0010_0001_11,
-         10'b0010_0001_11,
-         10'b0010_0110_11,
-         10'b0010_0110_11,
-         10'b0010_0110_11,
-         10'b0010_0110_11,
-         10'b0010_0110_11,
-         10'b0010_0110_11,
-         10'b0010_0110_11,
-         10'b0010_0110_11,
-         10'b0010_0110_11,
-         10'b0010_0110_11,
-         10'b0010_1010_11,
-         10'b0010_1010_11,
-         10'b0010_1010_11,
-         10'b0010_1010_11,
-         10'b0010_1010_11,
-         10'b0010_1010_11,
-         10'b0010_1010_11,
-         10'b0010_1010_11,
-         10'b0010_1100_11,
-         10'b0010_1100_11,
-         10'b0010_1100_11,
-         10'b0010_1100_11,
-         10'b0010_1100_11,
-         10'b0010_1100_11,
-         10'b0010_1100_11,
-         10'b0010_1100_11,
-         10'b0010_1100_11,
-         10'b0010_1100_11,
-         10'b0010_1100_11,
-         10'b0010_1100_11,
-         10'b0010_1100_11,
-         10'b0010_1100_11,
-         10'b0010_1100_11,
-         10'b0010_1100_11,
-         10'b0010_1100_11
-      };
-      
-      lookup_high = {
-         // CP_RES_LFHF
-         10'b0010_1111_11,
-         10'b0010_1111_11,
-         10'b0010_1011_11,
-         10'b0011_1111_11,
-         10'b0100_1111_11,
-         10'b0100_1111_11,
-         10'b0101_1111_11,
-         10'b0110_1111_11,
-         10'b0111_1111_11,
-         10'b0111_1111_11,
-         10'b1100_1111_11,
-         10'b1101_1111_11,
-         10'b1110_1111_11,
-         10'b1111_1111_11,
-         10'b1111_1111_11,
-         10'b1110_0111_11,
-         10'b1110_1011_11,
-         10'b1111_0111_11,
-         10'b1111_1011_11,
-         10'b1111_1011_11,
-         10'b1110_1101_11,
-         10'b1111_1101_11,
-         10'b1111_1101_11,
-         10'b1111_0011_11,
-         10'b1111_0011_11,
-         10'b1111_0011_11,
-         10'b1110_0101_11,
-         10'b1110_0101_11,
-         10'b1110_0101_11,
-         10'b1111_0101_11,
-         10'b1111_0101_11,
-         10'b1111_0101_11,
-         10'b1111_1001_11,
-         10'b1111_1001_11,
-         10'b1111_1001_11,
-         10'b1111_1001_11,
-         10'b1111_1001_11,
-         10'b1110_1110_11,
-         10'b1110_1110_11,
-         10'b1110_1110_11,
-         10'b1110_1110_11,
-         10'b1111_1110_11,
-         10'b1111_1110_11,
-         10'b1111_1110_11,
-         10'b1111_1110_11,
-         10'b1111_1110_11,
-         10'b1111_1110_11,
-         10'b1111_1110_11,
-         10'b1110_0001_11,
-         10'b1110_0001_11,
-         10'b1110_0001_11,
-         10'b1110_0001_11,
-         10'b1110_0001_11,
-         10'b1100_0110_11,
-         10'b1100_0110_11,
-         10'b1100_0110_11,
-         10'b1100_0110_11,
-         10'b1100_0110_11,
-         10'b1100_0110_11,
-         10'b1100_0110_11,
-         10'b1100_1010_11,
-         10'b1100_1010_11,
-         10'b1100_1010_11,
-         10'b1100_1010_11
-      };
-      
-      // Set lookup_entry with the explicit bits from lookup with a part select
-      if(BANDWIDTH == "LOW") begin
-         // Low Bandwidth
-         mmcm_pll_filter_lookup = lookup_low[ ((64-divide)*10) +: 10];
-      end else begin
-         // High or optimized bandwidth
-         mmcm_pll_filter_lookup = lookup_high[ ((64-divide)*10) +: 10];
-      end
-      
-   `ifdef DEBUG
-      $display("filter_lookup: %b", mmcm_pll_filter_lookup);
-   `endif
-   end
-endfunction
-
-// This function takes in the divide, phase, and duty cycle
-// setting to calculate the upper and lower counter registers.
-function [37:0] mmcm_pll_count_calc
-   (
-      input [7:0] divide, // Max divide is 128
-      input signed [31:0] phase,
-      input [31:0] duty_cycle // Multiplied by 100,000
-   );
-   
-   reg [13:0] div_calc;
-   reg [16:0] phase_calc;
-   
-   begin
-   `ifdef DEBUG
-      $display("mmcm_pll_count_calc- divide:%h, phase:%d, duty_cycle:%d",
-         divide, phase, duty_cycle);
-   `endif
-   
-      // w_edge[13], no_count[12], high_time[11:6], low_time[5:0]
-      div_calc = mmcm_pll_divider(divide, duty_cycle);
-      // mx[10:9], pm[8:6], dt[5:0]
-      phase_calc = mmcm_pll_phase(divide, phase);
-
-      // Return value is the upper and lower address of counter
-      //    Upper address is:
-      //       RESERVED    [31:26]
-      //       MX          [25:24]
-      //       EDGE        [23]
-      //       NOCOUNT     [22]
-      //       DELAY_TIME  [21:16]
-      //    Lower Address is:
-      //       PHASE_MUX   [15:13]
-      //       RESERVED    [12]
-      //       HIGH_TIME   [11:6]
-      //       LOW_TIME    [5:0]
-      
-   `ifdef DEBUG
-      $display("div:%d dc:%d phase:%d ht:%d lt:%d ed:%d nc:%d mx:%d dt:%d pm:%d",
-         divide, duty_cycle, phase, div_calc[11:6], div_calc[5:0], 
-         div_calc[13], div_calc[12], 
-         phase_calc[16:15], phase_calc[5:0], phase_calc[14:12]);
-   `endif
-      
-      mmcm_pll_count_calc =
-         {
-            // Upper Address
-            6'h00, phase_calc[10:9], div_calc[13:12], phase_calc[5:0], 
-            // Lower Address
-            phase_calc[8:6], 1'b0, div_calc[11:0]
-         };
-   end
-endfunction
-
-
-// This function takes in the divide, phase, and duty cycle
-// setting to calculate the upper and lower counter registers.
-// for fractional multiply/divide functions.
-//
-// 
-function [37:0] mmcm_frac_count_calc
-   (
-      input [7:0] divide, // Max divide is 128
-      input signed [31:0] phase,
-      input [31:0] duty_cycle, // Multiplied by 1,000
-      input [9:0] frac // Multiplied by 1000
-   );
-   
-	//Required for fractional divide calculations
-			  reg	[7:0]			lt_frac;
-			  reg	[7:0]			ht_frac;
-			
-			  reg	/*[7:0]*/			wf_fall_frac;
-			  reg	/*[7:0]*/			wf_rise_frac;
-
-			  reg [31:0] a;
-			  reg	[7:0]			pm_rise_frac_filtered ;
-			  reg	[7:0]			pm_fall_frac_filtered ;	
-			  reg [7:0]			clkout0_divide_int;
-			  reg [2:0]			clkout0_divide_frac;
-			  reg	[7:0]			even_part_high;
-			  reg	[7:0]			even_part_low;
-
-			  reg	[7:0]			odd;
-			  reg	[7:0]			odd_and_frac;
-
-			  reg	[7:0]			pm_fall;
-			  reg	[7:0]			pm_rise;
-			  reg	[7:0]			dt;
-			  reg	[7:0]			dt_int; 
-			  reg [63:0]		dt_calc;
-
-			  reg	[7:0]			pm_rise_frac; 
-			  reg	[7:0]			pm_fall_frac;
-	 
-			  reg [31:0] a_per_in_octets;
-			  reg [31:0] a_phase_in_cycles;
-
-				parameter precision = 0.125;
-
-			  reg [31:0] phase_fixed; // changed to 31:0 from 32:1 jt 5/2/11
-			  reg [31: 0] phase_pos;
-			  reg [31: 0] phase_vco;
-			  reg [31:0] temp;// changed to 31:0 from 32:1 jt 5/2/11
-			  reg [13:0] div_calc;
-			  reg [16:0] phase_calc;
-
-   begin
-	`ifdef DEBUG
-			$display("mmcm_frac_count_calc- divide:%h, phase:%d, duty_cycle:%d",
-				divide, phase, duty_cycle);
-	`endif
-   
-   //convert phase to fixed
-   if ((phase < -360000) || (phase > 360000)) begin
-`ifndef SYNTHESIS
-      $display("ERROR: phase of $phase is not between -360000 and 360000");
-	`endif
-      $finish;
-   end
-
-
-      // Return value is
-      //    Transfer data
-      //       RESERVED     [37:36]
-      //       FRAC_TIME    [35:33]
-      //       FRAC_WF_FALL [32]
-      //    Upper address is:
-      //       RESERVED     [31:26]
-      //       MX           [25:24]
-      //       EDGE         [23]
-      //       NOCOUNT      [22]
-      //       DELAY_TIME   [21:16]
-      //    Lower Address is:
-      //       PHASE_MUX    [15:13]
-      //       RESERVED     [12]
-      //       HIGH_TIME    [11:6]
-      //       LOW_TIME     [5:0]
-      
-      
-
-	clkout0_divide_frac = frac / 125;
-	clkout0_divide_int = divide;
-
-	even_part_high = clkout0_divide_int >> 1;//$rtoi(clkout0_divide_int / 2);
-	even_part_low = even_part_high;
-									
-	odd = clkout0_divide_int - even_part_high - even_part_low;
-	odd_and_frac = (8*odd) + clkout0_divide_frac;
-
-	lt_frac = even_part_high - (odd_and_frac <= 9);//IF(odd_and_frac>9,even_part_high, even_part_high - 1)
-	ht_frac = even_part_low  - (odd_and_frac <= 8);//IF(odd_and_frac>8,even_part_low, even_part_low- 1)
-
-	pm_fall =  {odd[6:0],2'b00} + {6'h00, clkout0_divide_frac[2:1]}; // using >> instead of clkout0_divide_frac / 2 
-	pm_rise = 0; //0
-    
-	wf_fall_frac = ((odd_and_frac >=2) && (odd_and_frac <=9)) || ((clkout0_divide_frac == 1) && (clkout0_divide_int == 2));//CRS610807
-	wf_rise_frac = (odd_and_frac >=1) && (odd_and_frac <=8);//IF(odd_and_frac>=1,IF(odd_and_frac <= 8,1,0),0)
-
-
-
-	//Calculate phase in fractional cycles
-	a_per_in_octets		= (8 * divide) + (frac / 125) ;
-	a_phase_in_cycles	= (phase+10) * a_per_in_octets / 360000 ;//Adding 1 due to rounding errors
-	pm_rise_frac		= (a_phase_in_cycles[7:0] ==8'h00)?8'h00:a_phase_in_cycles[7:0] - {a_phase_in_cycles[7:3],3'b000};
-
-	dt_calc 	= ((phase+10) * a_per_in_octets / 8 )/360000 ;//TRUNC(phase* divide / 360); //or_simply (a_per_in_octets / 8)
-	dt 	= dt_calc[7:0];
-
-	pm_rise_frac_filtered = (pm_rise_frac >=8) ? (pm_rise_frac ) - 8: pm_rise_frac ;				//((phase_fixed * (divide + frac / 1000)) / 360) - {pm_rise_frac[7:3],3'b000};//$rtoi(clkout0_phase * clkout0_divide / 45);//a;
-
-	dt_int			= dt + (& pm_rise_frac[7:4]); //IF(pm_rise_overwriting>7,dt+1,dt)
-	pm_fall_frac		= pm_fall + pm_rise_frac;
-	pm_fall_frac_filtered	= pm_fall + pm_rise_frac - {pm_fall_frac[7:3], 3'b000};
-
-	div_calc	= mmcm_pll_divider(divide, duty_cycle); //Use to determine edge[7], no count[6]
-	phase_calc	= mmcm_pll_phase(divide, phase);// returns{mx[1:0], phase_mux[2:0], delay_time[5:0]}
-		
-      mmcm_frac_count_calc[37:0] =
-         {		2'b00, pm_fall_frac_filtered[2:0], wf_fall_frac,
-			1'b0, clkout0_divide_frac[2:0], 1'b1, wf_rise_frac, phase_calc[10:9], div_calc[13:12], dt[5:0], 
-			pm_rise_frac_filtered[2], pm_rise_frac_filtered[1], pm_rise_frac_filtered[0], 1'b0, ht_frac[5:0], lt_frac[5:0]
-		} ;
-
-   `ifdef DEBUG
-      $display("-%d.%d p%d>>  :DADDR_9_15 frac30to28.frac_en.wf_r_frac.dt:%b%d%d_%b:DADDR_7_13 pm_f_frac_filtered_29to27.wf_f_frac_26:%b%d:DADDR_8_14.pm_r_frac_filt_15to13.ht_frac.lt_frac:%b%b%b:", divide, frac, phase, clkout0_divide_frac, 1, wf_rise_frac, dt, pm_fall_frac_filtered, wf_fall_frac, pm_rise_frac_filtered, ht_frac, lt_frac);
-   `endif
-
-   end
-endfunction
-

LAB2/src/pak_depak/ipshared/d0f7/mmcm_pll_drp_func_us_pll.vh

@@ -1,530 +0,0 @@
-///////////////////////////////////////////////////////////////////////////////
-//    
-//    Company:          Xilinx
-//    Engineer:         Jim Tatsukawa
-//    Date:             6/15/2015
-//    Design Name:      PLLE3 DRP
-//    Module Name:      plle3_drp_func.h
-//    Version:          1.10
-//    Target Devices:   UltraScale Architecture
-//    Tool versions:    2015.1
-//    Description:      This header provides the functions necessary to  
-//                      calculate the DRP register values for the V6 PLL.
-//                      
-//	Revision Notes:	8/11 - PLLE3 updated for PLLE3 file 4564419
-//	Revision Notes:	6/15 - pll_filter_lookup fixed for max M of 19
-//                         PM_Rise bits have been removed for PLLE3
-// 
-//    Disclaimer:  XILINX IS PROVIDING THIS DESIGN, CODE, OR
-//                 INFORMATION "AS IS" SOLELY FOR USE IN DEVELOPING
-//                 PROGRAMS AND SOLUTIONS FOR XILINX DEVICES.  BY
-//                 PROVIDING THIS DESIGN, CODE, OR INFORMATION AS
-//                 ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE,
-//                 APPLICATION OR STANDARD, XILINX IS MAKING NO
-//                 REPRESENTATION THAT THIS IMPLEMENTATION IS FREE
-//                 FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE
-//                 RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY
-//                 REQUIRE FOR YOUR IMPLEMENTATION.  XILINX
-//                 EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH
-//                 RESPECT TO THE ADEQUACY OF THE IMPLEMENTATION,
-//                 INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR
-//                 REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE
-//                 FROM CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES
-//                 OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-//                 PURPOSE.
-// 
-//                 (c) Copyright 2009-2010 Xilinx, Inc.
-//                 All rights reserved.
-// 
-///////////////////////////////////////////////////////////////////////////////
-
-// These are user functions that should not be modified.  Changes to the defines
-// or code within the functions may alter the accuracy of the calculations.
-
-// Define debug to provide extra messages durring elaboration
-//`define DEBUG 1
-
-// FRAC_PRECISION describes the width of the fractional portion of the fixed
-//    point numbers.  These should not be modified, they are for development 
-//    only
-`define FRAC_PRECISION  10
-// FIXED_WIDTH describes the total size for fixed point calculations(int+frac).
-// Warning: L.50 and below will not calculate properly with FIXED_WIDTHs 
-//    greater than 32
-`define FIXED_WIDTH     32 
-
-// This function takes a fixed point number and rounds it to the nearest
-//    fractional precision bit.
-function [`FIXED_WIDTH:1] round_frac
-   (
-      // Input is (FIXED_WIDTH-FRAC_PRECISION).FRAC_PRECISION fixed point number
-      input [`FIXED_WIDTH:1] decimal,  
-
-      // This describes the precision of the fraction, for example a value
-      //    of 1 would modify the fractional so that instead of being a .16
-      //    fractional, it would be a .1 (rounded to the nearest 0.5 in turn)
-      input [`FIXED_WIDTH:1] precision 
-   );
-
-   begin
-   
-   `ifdef DEBUG
-      $display("round_frac - decimal: %h, precision: %h", decimal, precision);
-   `endif
-      // If the fractional precision bit is high then round up
-      if( decimal[(`FRAC_PRECISION-precision)] == 1'b1) begin
-         round_frac = decimal + (1'b1 << (`FRAC_PRECISION-precision));
-      end else begin
-         round_frac = decimal;
-      end
-   `ifdef DEBUG
-      $display("round_frac: %h", round_frac);
-   `endif
-   end
-endfunction
-
-// This function calculates high_time, low_time, w_edge, and no_count
-//    of a non-fractional counter based on the divide and duty cycle
-//
-// NOTE: high_time and low_time are returned as integers between 0 and 63 
-//    inclusive.  64 should equal 6'b000000 (in other words it is okay to 
-//    ignore the overflow)
-function [13:0] mmcm_pll_divider
-   (
-      input [7:0] divide,        // Max divide is 128
-      input [31:0] duty_cycle    // Duty cycle is multiplied by 100,000
-   );
-
-   reg [`FIXED_WIDTH:1]    duty_cycle_fix;
-   
-   // High/Low time is initially calculated with a wider integer to prevent a
-   // calculation error when it overflows to 64.
-   reg [6:0]               high_time;
-   reg [6:0]               low_time;
-   reg                     w_edge;
-   reg                     no_count;
-
-   reg [`FIXED_WIDTH:1]    temp;
-
-   begin
-      // Duty Cycle must be between 0 and 1,000
-      if(duty_cycle <=0 || duty_cycle >= 100000) begin
-`ifndef SYNTHESIS
-         $display("ERROR: duty_cycle: %d is invalid", duty_cycle);
-   `endif
-         $finish;
-      end
-
-      // Convert to FIXED_WIDTH-FRAC_PRECISION.FRAC_PRECISION fixed point
-      duty_cycle_fix = (duty_cycle << `FRAC_PRECISION) / 100_000;
-      
-   `ifdef DEBUG
-      $display("duty_cycle_fix: %h", duty_cycle_fix);
-   `endif
-
-      // If the divide is 1 nothing needs to be set except the no_count bit.
-      //    Other values are dummies
-      if(divide == 7'h01) begin
-         high_time   = 7'h01;
-         w_edge      = 1'b0;
-         low_time    = 7'h01;
-         no_count    = 1'b1;
-      end else begin
-         temp = round_frac(duty_cycle_fix*divide, 1);
-
-         // comes from above round_frac
-         high_time   = temp[`FRAC_PRECISION+7:`FRAC_PRECISION+1]; 
-         // If the duty cycle * divide rounded is .5 or greater then this bit
-         //    is set.
-         w_edge      = temp[`FRAC_PRECISION]; // comes from round_frac
-         
-         // If the high time comes out to 0, it needs to be set to at least 1
-         // and w_edge set to 0
-         if(high_time == 7'h00) begin
-            high_time   = 7'h01;
-            w_edge      = 1'b0;
-         end
-
-         if(high_time == divide) begin
-            high_time   = divide - 1;
-            w_edge      = 1'b1;
-         end
-         
-         // Calculate low_time based on the divide setting and set no_count to
-         //    0 as it is only used when divide is 1.
-         low_time    = divide - high_time; 
-         no_count    = 1'b0;
-      end
-
-      // Set the return value.
-      mmcm_pll_divider = {w_edge,no_count,high_time[5:0],low_time[5:0]};
-   end
-endfunction
-
-// This function calculates mx, delay_time, and phase_mux 
-//  of a non-fractional counter based on the divide and phase
-//
-// NOTE: The only valid value for the MX bits is 2'b00 to ensure the coarse mux
-//    is used.
-function [10:0] mmcm_pll_phase
-   (
-      // divide must be an integer (use fractional if not)
-      //  assumed that divide already checked to be valid
-      input [7:0] divide, // Max divide is 128
-
-      // Phase is given in degrees (-360,000 to 360,000)
-      input signed [31:0] phase
-   );
-
-   reg [`FIXED_WIDTH:1] phase_in_cycles;
-   reg [`FIXED_WIDTH:1] phase_fixed;
-   reg [1:0]            mx;
-   reg [5:0]            delay_time;
-   reg [2:0]            phase_mux;
-
-   reg [`FIXED_WIDTH:1] temp;
-
-   begin
-`ifdef DEBUG
-      $display("mmcm_pll_phase-divide:%d,phase:%d",
-         divide, phase);
-`endif
-   
-      if ((phase < -360000) || (phase > 360000)) begin
-`ifndef SYNTHESIS
-      $display("ERROR: phase of $phase is not between -360000 and 360000");
-	`endif
-         $finish;
-      end
-
-      // If phase is less than 0, convert it to a positive phase shift
-      // Convert to (FIXED_WIDTH-FRAC_PRECISION).FRAC_PRECISION fixed point
-      if(phase < 0) begin
-         phase_fixed = ( (phase + 360000) << `FRAC_PRECISION ) / 1000;
-      end else begin
-         phase_fixed = ( phase << `FRAC_PRECISION ) / 1000;
-      end
-
-      // Put phase in terms of decimal number of vco clock cycles
-      phase_in_cycles = ( phase_fixed * divide ) / 360;
-
-`ifdef DEBUG
-      $display("phase_in_cycles: %h", phase_in_cycles);
-`endif  
-      
-
-	 temp  =  round_frac(phase_in_cycles, 3);
-
-	 // set mx to 2'b00 that the phase mux from the VCO is enabled
-	 mx    			=  2'b00; 
-	 phase_mux      =  temp[`FRAC_PRECISION:`FRAC_PRECISION-2];
-	 delay_time     =  temp[`FRAC_PRECISION+6:`FRAC_PRECISION+1];
-      
-   `ifdef DEBUG
-      $display("temp: %h", temp);
-   `endif
-
-      // Setup the return value
-      mmcm_pll_phase={mx, phase_mux, delay_time};
-   end
-endfunction
-
-// This function takes the divide value and outputs the necessary lock values
-function [39:0] mmcm_pll_lock_lookup
-   (
-      input [6:0] divide // Max divide is 64
-   );
-   
-   reg [759:0]   lookup;
-   
-   begin
-      lookup = {
-         // This table is composed of:
-         // LockRefDly_LockFBDly_LockCnt_LockSatHigh_UnlockCnt
-         40'b00110_00110_1111101000_1111101001_0000000001, //1  
-         40'b00110_00110_1111101000_1111101001_0000000001, //2
-         40'b01000_01000_1111101000_1111101001_0000000001, //3
-         40'b01011_01011_1111101000_1111101001_0000000001, //4
-         40'b01110_01110_1111101000_1111101001_0000000001, //5
-         40'b10001_10001_1111101000_1111101001_0000000001, //6
-         40'b10011_10011_1111101000_1111101001_0000000001, //7
-         40'b10110_10110_1111101000_1111101001_0000000001, //8
-         40'b11001_11001_1111101000_1111101001_0000000001, //9
-         40'b11100_11100_1111101000_1111101001_0000000001, //10
-         40'b11111_11111_1110000100_1111101001_0000000001, //11
-         40'b11111_11111_1100111001_1111101001_0000000001, //12
-         40'b11111_11111_1011101110_1111101001_0000000001, //13
-         40'b11111_11111_1010111100_1111101001_0000000001, //14
-         40'b11111_11111_1010001010_1111101001_0000000001, //15
-         40'b11111_11111_1001110001_1111101001_0000000001, //16
-         40'b11111_11111_1000111111_1111101001_0000000001, //17
-         40'b11111_11111_1000100110_1111101001_0000000001, //18
-         40'b11111_11111_1000001101_1111101001_0000000001 //19
-         
-      };
-      
-      // Set lookup_entry with the explicit bits from lookup with a part select
-      mmcm_pll_lock_lookup = lookup[ ((19-divide)*40) +: 40];
-   `ifdef DEBUG
-      $display("lock_lookup: %b", mmcm_pll_lock_lookup);
-   `endif
-   end
-endfunction
-
-// This function takes the divide value and the bandwidth setting of the PLL
-//  and outputs the digital filter settings necessary. Removing bandwidth setting for PLLE3.
-function [9:0] mmcm_pll_filter_lookup
-   (
-      input [6:0] divide // Max divide is 19
-   );
-   
-   reg [639:0] lookup;
-   reg [9:0] lookup_entry;
-   
-   begin
-
-      lookup = {
-         // CP_RES_LFHF
-         10'b0010_1111_01, //1
-         10'b0010_0011_11, //2
-         10'b0011_0011_11, //3
-         10'b0010_0001_11, //4
-         10'b0010_0110_11, //5
-         10'b0010_1010_11, //6
-         10'b0010_1010_11, //7
-         10'b0011_0110_11, //8
-         10'b0010_1100_11, //9
-         10'b0010_1100_11, //10
-         10'b0010_1100_11, //11
-         10'b0010_0010_11, //12
-         10'b0011_1100_11, //13
-         10'b0011_1100_11, //14
-         10'b0011_1100_11, //15
-         10'b0011_1100_11, //16
-         10'b0011_0010_11, //17
-         10'b0011_0010_11, //18
-         10'b0011_0010_11 //19
-      };
-      
-         mmcm_pll_filter_lookup = lookup [ ((19-divide)*10) +: 10];
-      
-   `ifdef DEBUG
-      $display("filter_lookup: %b", mmcm_pll_filter_lookup);
-   `endif
-   end
-endfunction
-
-// This function set the CLKOUTPHY divide settings to match
-// the desired CLKOUTPHY_MODE setting. To create VCO_X2, then
-// the CLKOUTPHY will be set to 2'b00 since the VCO is internally
-// doubled and 2'b00 will represent divide by 1. Similarly "VCO" // will need to divide the doubled clock VCO clock frequency by // 2 therefore 2'b01 will match a divide by 2.And VCO_HALF will // need to divide the doubled VCO by 4, therefore 2'b10
-function [9:0] mmcm_pll_clkoutphy_calc
-   (
-      input [8*9:0] CLKOUTPHY_MODE
-   );
-
-      if(CLKOUTPHY_MODE == "VCO_X2") begin
-         mmcm_pll_clkoutphy_calc= 2'b00;
-      end else if(CLKOUTPHY_MODE == "VCO") begin
-         mmcm_pll_clkoutphy_calc= 2'b01;
-      end else if(CLKOUTPHY_MODE == "CLKIN") begin
-         mmcm_pll_clkoutphy_calc= 2'b11;
-      end else begin // Assume "VCO_HALF"
-         mmcm_pll_clkoutphy_calc= 2'b10;
-      end
-      
-endfunction
-
-
-// This function takes in the divide, phase, and duty cycle
-// setting to calculate the upper and lower counter registers.
-function [37:0] mmcm_pll_count_calc
-   (
-      input [7:0] divide, // Max divide is 128
-      input signed [31:0] phase,
-      input [31:0] duty_cycle // Multiplied by 100,000
-   );
-   
-   reg [13:0] div_calc;
-   reg [16:0] phase_calc;
-   
-   begin
-   `ifdef DEBUG
-      $display("mmcm_pll_count_calc- divide:%h, phase:%d, duty_cycle:%d",
-         divide, phase, duty_cycle);
-   `endif
-   
-      // w_edge[13], no_count[12], high_time[11:6], low_time[5:0]
-      div_calc = mmcm_pll_divider(divide, duty_cycle);
-      // mx[10:9], pm[8:6], dt[5:0]
-      phase_calc = mmcm_pll_phase(divide, phase);
-
-      // Return value is the upper and lower address of counter
-      //    Upper address is:
-      //       RESERVED    [31:26]
-      //       MX          [25:24]
-      //       EDGE        [23]
-      //       NOCOUNT     [22]
-      //       DELAY_TIME  [21:16]
-      //    Lower Address is:
-      //       PHASE_MUX   [15:13]
-      //       RESERVED    [12]
-      //       HIGH_TIME   [11:6]
-      //       LOW_TIME    [5:0]
-      
-   `ifdef DEBUG
-      $display("div:%d dc:%d phase:%d ht:%d lt:%d ed:%d nc:%d mx:%d dt:%d pm:%d",
-         divide, duty_cycle, phase, div_calc[11:6], div_calc[5:0], 
-         div_calc[13], div_calc[12], 
-         phase_calc[16:15], phase_calc[5:0], 3'b000);//Removed PM_Rise bits
-   `endif
-      
-      mmcm_pll_count_calc =
-         {
-            // Upper Address
-            6'h00, phase_calc[10:9], div_calc[13:12], phase_calc[5:0], 
-            // Lower Address
-            phase_calc[8:6], 1'b0, div_calc[11:0]
-         };
-   end
-endfunction
-
-
-// This function takes in the divide, phase, and duty cycle
-// setting to calculate the upper and lower counter registers.
-// for fractional multiply/divide functions.
-//
-// 
-function [37:0] mmcm_pll_frac_count_calc
-   (
-      input [7:0] divide, // Max divide is 128
-      input signed [31:0] phase,
-      input [31:0] duty_cycle, // Multiplied by 1,000
-      input [9:0] frac // Multiplied by 1000
-   );
-   
-	//Required for fractional divide calculations
-			  reg	[7:0]			lt_frac;
-			  reg	[7:0]			ht_frac;
-			
-			  reg	/*[7:0]*/			wf_fall_frac;
-			  reg	/*[7:0]*/			wf_rise_frac;
-
-			  reg [31:0] a;
-			  reg	[7:0]			pm_rise_frac_filtered ;
-			  reg	[7:0]			pm_fall_frac_filtered ;	
-			  reg [7:0]			clkout0_divide_int;
-			  reg [2:0]			clkout0_divide_frac;
-			  reg	[7:0]			even_part_high;
-			  reg	[7:0]			even_part_low;
-
-			  reg	[7:0]			odd;
-			  reg	[7:0]			odd_and_frac;
-
-			  reg	[7:0]			pm_fall;
-			  reg	[7:0]			pm_rise;
-			  reg	[7:0]			dt;
-			  reg	[7:0]			dt_int; 
-			  reg [63:0]		dt_calc;
-
-			  reg	[7:0]			pm_rise_frac; 
-			  reg	[7:0]			pm_fall_frac;
-	 
-			  reg [31:0] a_per_in_octets;
-			  reg [31:0] a_phase_in_cycles;
-
-				parameter precision = 0.125;
-
-			  reg [31:0] phase_fixed; // changed to 31:0 from 32:1 jt 5/2/11
-			  reg [31: 0] phase_pos;
-			  reg [31: 0] phase_vco;
-			  reg [31:0] temp;// changed to 31:0 from 32:1 jt 5/2/11
-			  reg [13:0] div_calc;
-			  reg [16:0] phase_calc;
-
-   begin
-	`ifdef DEBUG
-			$display("mmcm_pll_frac_count_calc- divide:%h, phase:%d, duty_cycle:%d",
-				divide, phase, duty_cycle);
-	`endif
-   
-   //convert phase to fixed
-   if ((phase < -360000) || (phase > 360000)) begin
-`ifndef SYNTHESIS
-      $display("ERROR: phase of $phase is not between -360000 and 360000");
-	`endif
-      $finish;
-   end
-
-
-      // Return value is
-      //    Transfer data
-      //       RESERVED     [37:36]
-      //       FRAC_TIME    [35:33]
-      //       FRAC_WF_FALL [32]
-      //    Upper address is:
-      //       RESERVED     [31:26]
-      //       MX           [25:24]
-      //       EDGE         [23]
-      //       NOCOUNT      [22]
-      //       DELAY_TIME   [21:16]
-      //    Lower Address is:
-      //       PHASE_MUX    [15:13]
-      //       RESERVED     [12]
-      //       HIGH_TIME    [11:6]
-      //       LOW_TIME     [5:0]
-      
-      
-
-	clkout0_divide_frac = frac / 125;
-	clkout0_divide_int = divide;
-
-	even_part_high = clkout0_divide_int >> 1;//$rtoi(clkout0_divide_int / 2);
-	even_part_low = even_part_high;
-									
-	odd = clkout0_divide_int - even_part_high - even_part_low;
-	odd_and_frac = (8*odd) + clkout0_divide_frac;
-
-	lt_frac = even_part_high - (odd_and_frac <= 9);//IF(odd_and_frac>9,even_part_high, even_part_high - 1)
-	ht_frac = even_part_low  - (odd_and_frac <= 8);//IF(odd_and_frac>8,even_part_low, even_part_low- 1)
-
-	pm_fall =  {odd[6:0],2'b00} + {6'h00, clkout0_divide_frac[2:1]}; // using >> instead of clkout0_divide_frac / 2 
-	pm_rise = 0; //0
-    
-	wf_fall_frac = (odd_and_frac >=2) && (odd_and_frac <=9);//IF(odd_and_frac>=2,IF(odd_and_frac <= 9,1,0),0)
-	wf_rise_frac = (odd_and_frac >=1) && (odd_and_frac <=8);//IF(odd_and_frac>=1,IF(odd_and_frac <= 8,1,0),0)
-
-
-
-	//Calculate phase in fractional cycles
-	a_per_in_octets		= (8 * divide) + (frac / 125) ;
-	a_phase_in_cycles	= (phase+10) * a_per_in_octets / 360000 ;//Adding 1 due to rounding errors
-	pm_rise_frac		= (a_phase_in_cycles[7:0] ==8'h00)?8'h00:a_phase_in_cycles[7:0] - {a_phase_in_cycles[7:3],3'b000};
-
-	dt_calc 	= ((phase+10) * a_per_in_octets / 8 )/360000 ;//TRUNC(phase* divide / 360); //or_simply (a_per_in_octets / 8)
-	dt 	= dt_calc[7:0];
-
-	pm_rise_frac_filtered = (pm_rise_frac >=8) ? (pm_rise_frac ) - 8: pm_rise_frac ;				//((phase_fixed * (divide + frac / 1000)) / 360) - {pm_rise_frac[7:3],3'b000};//$rtoi(clkout0_phase * clkout0_divide / 45);//a;
-
-	dt_int			= dt + (& pm_rise_frac[7:4]); //IF(pm_rise_overwriting>7,dt+1,dt)
-	pm_fall_frac		= pm_fall + pm_rise_frac;
-	pm_fall_frac_filtered	= pm_fall + pm_rise_frac - {pm_fall_frac[7:3], 3'b000};
-
-	div_calc	= mmcm_pll_divider(divide, duty_cycle); //Use to determine edge[7], no count[6]
-	phase_calc	= mmcm_pll_phase(divide, phase);// returns{mx[1:0], phase_mux[2:0], delay_time[5:0]}
-		
-      mmcm_pll_frac_count_calc[37:0] =
-         {		2'b00, pm_fall_frac_filtered[2:0], wf_fall_frac,
-			1'b0, clkout0_divide_frac[2:0], 1'b1, wf_rise_frac, phase_calc[10:9], div_calc[13:12], dt[5:0], 
-			3'b000, 1'b0, ht_frac[5:0], lt_frac[5:0] //Removed PM_Rise bits
-//			pm_rise_frac_filtered[2], pm_rise_frac_filtered[1], pm_rise_frac_filtered[0], 1'b0, ht_frac[5:0], lt_frac[5:0]
-		} ;
-
-   `ifdef DEBUG
-      $display("-%d.%d p%d>>  :DADDR_9_15 frac30to28.frac_en.wf_r_frac.dt:%b%d%d_%b:DADDR_7_13 pm_f_frac_filtered_29to27.wf_f_frac_26:%b%d:DADDR_8_14.pm_r_frac_filt_15to13.ht_frac.lt_frac:%b%b%b:", divide, frac, phase, clkout0_divide_frac, 1, wf_rise_frac, dt, pm_fall_frac_filtered, wf_fall_frac, 3'b000, ht_frac, lt_frac);
-   `endif
-
-   end
-endfunction
-
-

LAB2/src/pak_depak/ipshared/d0f7/mmcm_pll_drp_func_us_plus_mmcm.vh

@@ -1,861 +0,0 @@
-///////////////////////////////////////////////////////////////////////////////
-//    
-//    Company:          Xilinx
-//    Engineer:         Jim Tatsukawa. Updated by Ralf Krueger
-//    Date:             7/30/2014
-//    Design Name:      MMCME4 DRP
-//    Module Name:      mmcme4_drp_func.h
-//    Version:          1.31
-//    Target Devices:   UltraScale Plus Architecture
-//    Tool versions:    2017.1
-//    Description:      This header provides the functions necessary to  
-//                      calculate the DRP register values for UltraScal+ MMCM.
-//                      
-//	Revision Notes:	3/22 - Updating lookup_low/lookup_high (CR)
-//				4/13 - Fractional divide function in mmcm_frac_count_calc function
-//              2/28/17 - Updated for Ultrascale Plus
-// 
-//    Disclaimer:  XILINX IS PROVIDING THIS DESIGN, CODE, OR
-//                 INFORMATION "AS IS" SOLELY FOR USE IN DEVELOPING
-//                 PROGRAMS AND SOLUTIONS FOR XILINX DEVICES.  BY
-//                 PROVIDING THIS DESIGN, CODE, OR INFORMATION AS
-//                 ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE,
-//                 APPLICATION OR STANDARD, XILINX IS MAKING NO
-//                 REPRESENTATION THAT THIS IMPLEMENTATION IS FREE
-//                 FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE
-//                 RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY
-//                 REQUIRE FOR YOUR IMPLEMENTATION.  XILINX
-//                 EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH
-//                 RESPECT TO THE ADEQUACY OF THE IMPLEMENTATION,
-//                 INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR
-//                 REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE
-//                 FROM CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES
-//                 OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-//                 PURPOSE.
-// 
-//                 (c) Copyright 2009-2017 Xilinx, Inc.
-//                 All rights reserved.
-// 
-///////////////////////////////////////////////////////////////////////////////
-
-// These are user functions that should not be modified.  Changes to the defines
-// or code within the functions may alter the accuracy of the calculations.
-
-// Define debug to provide extra messages during elaboration
-//`define DEBUG 1
-
-// FRAC_PRECISION describes the width of the fractional portion of the fixed
-// point numbers.  These should not be modified, they are for development only
-`define FRAC_PRECISION  10
-// FIXED_WIDTH describes the total size for fixed point calculations(int+frac).
-// Warning: L.50 and below will not calculate properly with FIXED_WIDTHs 
-// greater than 32
-`define FIXED_WIDTH     32 
-
-// This function takes a fixed point number and rounds it to the nearest
-// fractional precision bit.
-function [`FIXED_WIDTH:1] round_frac
-   (
-      // Input is (FIXED_WIDTH-FRAC_PRECISION).FRAC_PRECISION fixed point number
-      input [`FIXED_WIDTH:1] decimal,  
-
-      // This describes the precision of the fraction, for example a value
-      // of 1 would modify the fractional so that instead of being a .16
-      // fractional, it would be a .1 (rounded to the nearest 0.5 in turn)
-      input [`FIXED_WIDTH:1] precision 
-   );
-
-   begin
-   
-   `ifdef DEBUG
-      $display("round_frac - decimal: %h, precision: %h", decimal, precision);
-   `endif
-      // If the fractional precision bit is high then round up
-      if( decimal[(`FRAC_PRECISION-precision)] == 1'b1) begin
-         round_frac = decimal + (1'b1 << (`FRAC_PRECISION-precision));
-      end else begin
-         round_frac = decimal;
-      end
-   `ifdef DEBUG
-      $display("round_frac: %h", round_frac);
-   `endif
-   end
-endfunction
-
-// This function calculates high_time, low_time, w_edge, and no_count
-//    of a non-fractional counter based on the divide and duty cycle
-//
-// NOTE: high_time and low_time are returned as integers between 0 and 63 
-//    inclusive.  64 should equal 6'b000000 (in other words it is okay to 
-//    ignore the overflow)
-function [13:0] mmcm_pll_divider
-   (
-      input [7:0] divide,        // Max divide is 128
-      input [31:0] duty_cycle    // Duty cycle is multiplied by 100,000
-   );
-
-   reg [`FIXED_WIDTH:1]    duty_cycle_fix;
-   
-   // High/Low time is initially calculated with a wider integer to prevent a
-   // calculation error when it overflows to 64.
-   reg [6:0]               high_time;
-   reg [6:0]               low_time;
-   reg                     w_edge;
-   reg                     no_count;
-
-   reg [`FIXED_WIDTH:1]    temp;
-
-   begin
-      // Duty Cycle must be between 0 and 1,000
-      if(duty_cycle <=0 || duty_cycle >= 100000) begin
-`ifndef SYNTHESIS
-         $display("ERROR: duty_cycle: %d is invalid", duty_cycle);
-   `endif
-         $finish;
-      end
-
-      // Convert to FIXED_WIDTH-FRAC_PRECISION.FRAC_PRECISION fixed point
-      duty_cycle_fix = (duty_cycle << `FRAC_PRECISION) / 100_000;
-      
-   `ifdef DEBUG
-      $display("duty_cycle_fix: %h", duty_cycle_fix);
-   `endif
-
-      // If the divide is 1 nothing needs to be set except the no_count bit.
-      //    Other values are dummies
-      if(divide == 7'h01) begin
-         high_time   = 7'h01;
-         w_edge      = 1'b0;
-         low_time    = 7'h01;
-         no_count    = 1'b1;
-      end else begin
-         temp = round_frac(duty_cycle_fix*divide, 1);
-
-         // comes from above round_frac
-         high_time   = temp[`FRAC_PRECISION+7:`FRAC_PRECISION+1]; 
-         // If the duty cycle * divide rounded is .5 or greater then this bit
-         //    is set.
-         w_edge      = temp[`FRAC_PRECISION]; // comes from round_frac
-         
-         // If the high time comes out to 0, it needs to be set to at least 1
-         // and w_edge set to 0
-         if(high_time == 7'h00) begin
-            high_time   = 7'h01;
-            w_edge      = 1'b0;
-         end
-
-         if(high_time == divide) begin
-            high_time   = divide - 1;
-            w_edge      = 1'b1;
-         end
-         
-         // Calculate low_time based on the divide setting and set no_count to
-         //    0 as it is only used when divide is 1.
-         low_time    = divide - high_time; 
-         no_count    = 1'b0;
-      end
-
-      // Set the return value.
-      mmcm_pll_divider = {w_edge,no_count,high_time[5:0],low_time[5:0]};
-   end
-endfunction
-
-// This function calculates mx, delay_time, and phase_mux 
-// of a non-fractional counter based on the divide and phase
-//
-// NOTE: The only valid value for the MX bits is 2'b00 to ensure the coarse mux
-//       is used.
-function [10:0] mmcm_pll_phase
-   (
-      // divide must be an integer (use fractional if not)
-      // assumed that divide already checked to be valid
-      input [7:0] divide, // Max divide is 128
-
-      // Phase is given in degrees (-360,000 to 360,000)
-      input signed [31:0] phase
-   );
-
-   reg [`FIXED_WIDTH:1] phase_in_cycles;
-   reg [`FIXED_WIDTH:1] phase_fixed;
-   reg [1:0]            mx;
-   reg [5:0]            delay_time;
-   reg [2:0]            phase_mux;
-
-   reg [`FIXED_WIDTH:1] temp;
-
-   begin
-`ifdef DEBUG
-      $display("mmcm_phase-divide:%d,phase:%d", divide, phase);
-`endif
-   
-      if ((phase < -360000) || (phase > 360000)) begin
-`ifndef SYNTHESIS
-      $display("ERROR: phase of $phase is not between -360000 and 360000");
-	`endif
-         $finish;
-      end
-
-      // If phase is less than 0, convert it to a positive phase shift
-      // Convert to (FIXED_WIDTH-FRAC_PRECISION).FRAC_PRECISION fixed point
-      if(phase < 0) begin
-         phase_fixed = ( (phase + 360000) << `FRAC_PRECISION ) / 1000;
-      end else begin
-         phase_fixed = ( phase << `FRAC_PRECISION ) / 1000;
-      end
-
-      // Put phase in terms of decimal number of vco clock cycles
-      phase_in_cycles = ( phase_fixed * divide ) / 360;
-
-`ifdef DEBUG
-      $display("phase_in_cycles: %h", phase_in_cycles);
-`endif  
-      
-	 temp  =  round_frac(phase_in_cycles, 3);
-
-	 // set mx to 2'b00 that the phase mux from the VCO is enabled
-	 mx    			=  2'b00; 
-	 phase_mux      =  temp[`FRAC_PRECISION:`FRAC_PRECISION-2];
-	 delay_time     =  temp[`FRAC_PRECISION+6:`FRAC_PRECISION+1];
-      
-   `ifdef DEBUG
-      $display("temp: %h", temp);
-   `endif
-
-      // Setup the return value
-      mmcm_pll_phase={mx, phase_mux, delay_time};
-   end
-endfunction
-
-// This function takes the divide value and outputs the necessary lock values
-function [39:0] mmcm_pll_lock_lookup
-   (
-      input [7:0] divide // Max M divide is 128 in UltrascalePlus
-   );
-   
-   reg [5119:0]   lookup;
-   
-   begin
-      lookup = {
-         // This table is composed of:
-         // LockRefDly_LockFBDly_LockCnt_LockSatHigh_UnlockCnt
-         40'b00110_00110_1111101000_1111101001_0000000001,      // M=1 (not allowed)
-         40'b00110_00110_1111101000_1111101001_0000000001,      // M=2
-         40'b01000_01000_1111101000_1111101001_0000000001,      // M=3
-         40'b01011_01011_1111101000_1111101001_0000000001,      // M=4
-         40'b01110_01110_1111101000_1111101001_0000000001,      // M=5
-         40'b10001_10001_1111101000_1111101001_0000000001,      // M=6
-         40'b10011_10011_1111101000_1111101001_0000000001,      // M=7
-         40'b10110_10110_1111101000_1111101001_0000000001,
-         40'b11001_11001_1111101000_1111101001_0000000001,
-         40'b11100_11100_1111101000_1111101001_0000000001,
-         40'b11111_11111_1110000100_1111101001_0000000001,
-         40'b11111_11111_1100111001_1111101001_0000000001,
-         40'b11111_11111_1011101110_1111101001_0000000001,
-         40'b11111_11111_1010111100_1111101001_0000000001,
-         40'b11111_11111_1010001010_1111101001_0000000001,
-         40'b11111_11111_1001110001_1111101001_0000000001,
-         40'b11111_11111_1000111111_1111101001_0000000001,
-         40'b11111_11111_1000100110_1111101001_0000000001,
-         40'b11111_11111_1000001101_1111101001_0000000001,
-         40'b11111_11111_0111110100_1111101001_0000000001,
-         40'b11111_11111_0111011011_1111101001_0000000001,
-         40'b11111_11111_0111000010_1111101001_0000000001,
-         40'b11111_11111_0110101001_1111101001_0000000001,
-         40'b11111_11111_0110010000_1111101001_0000000001,
-         40'b11111_11111_0110010000_1111101001_0000000001,
-         40'b11111_11111_0101110111_1111101001_0000000001,
-         40'b11111_11111_0101011110_1111101001_0000000001,
-         40'b11111_11111_0101011110_1111101001_0000000001,
-         40'b11111_11111_0101000101_1111101001_0000000001,
-         40'b11111_11111_0101000101_1111101001_0000000001,
-         40'b11111_11111_0100101100_1111101001_0000000001,
-         40'b11111_11111_0100101100_1111101001_0000000001,
-         40'b11111_11111_0100101100_1111101001_0000000001,
-         40'b11111_11111_0100010011_1111101001_0000000001,
-         40'b11111_11111_0100010011_1111101001_0000000001,
-         40'b11111_11111_0100010011_1111101001_0000000001,
-         40'b11111_11111_0011111010_1111101001_0000000001,
-         40'b11111_11111_0011111010_1111101001_0000000001,
-         40'b11111_11111_0011111010_1111101001_0000000001,
-         40'b11111_11111_0011111010_1111101001_0000000001,
-         40'b11111_11111_0011111010_1111101001_0000000001,
-         40'b11111_11111_0011111010_1111101001_0000000001,
-         40'b11111_11111_0011111010_1111101001_0000000001,
-         40'b11111_11111_0011111010_1111101001_0000000001,
-         40'b11111_11111_0011111010_1111101001_0000000001,
-         40'b11111_11111_0011111010_1111101001_0000000001,
-         40'b11111_11111_0011111010_1111101001_0000000001,
-         40'b11111_11111_0011111010_1111101001_0000000001,
-         40'b11111_11111_0011111010_1111101001_0000000001,
-         40'b11111_11111_0011111010_1111101001_0000000001,
-         40'b11111_11111_0011111010_1111101001_0000000001,
-         40'b11111_11111_0011111010_1111101001_0000000001,
-         40'b11111_11111_0011111010_1111101001_0000000001,
-         40'b11111_11111_0011111010_1111101001_0000000001,
-         40'b11111_11111_0011111010_1111101001_0000000001,
-         40'b11111_11111_0011111010_1111101001_0000000001,
-         40'b11111_11111_0011111010_1111101001_0000000001,
-         40'b11111_11111_0011111010_1111101001_0000000001,
-         40'b11111_11111_0011111010_1111101001_0000000001,
-         40'b11111_11111_0011111010_1111101001_0000000001,
-         40'b11111_11111_0011111010_1111101001_0000000001,
-         40'b11111_11111_0011111010_1111101001_0000000001,
-         40'b11111_11111_0011111010_1111101001_0000000001,
-         40'b11111_11111_0011111010_1111101001_0000000001,
-         40'b11111_11111_0011111010_1111101001_0000000001,
-         40'b11111_11111_0011111010_1111101001_0000000001,
-         40'b11111_11111_0011111010_1111101001_0000000001,
-         40'b11111_11111_0011111010_1111101001_0000000001,
-         40'b11111_11111_0011111010_1111101001_0000000001,
-         40'b11111_11111_0011111010_1111101001_0000000001,
-         40'b11111_11111_0011111010_1111101001_0000000001,
-         40'b11111_11111_0011111010_1111101001_0000000001,
-         40'b11111_11111_0011111010_1111101001_0000000001,
-         40'b11111_11111_0011111010_1111101001_0000000001,
-         40'b11111_11111_0011111010_1111101001_0000000001,
-         40'b11111_11111_0011111010_1111101001_0000000001,
-         40'b11111_11111_0011111010_1111101001_0000000001,
-         40'b11111_11111_0011111010_1111101001_0000000001,
-         40'b11111_11111_0011111010_1111101001_0000000001,
-         40'b11111_11111_0011111010_1111101001_0000000001,
-         40'b11111_11111_0011111010_1111101001_0000000001,
-         40'b11111_11111_0011111010_1111101001_0000000001,
-         40'b11111_11111_0011111010_1111101001_0000000001,
-         40'b11111_11111_0011111010_1111101001_0000000001,
-         40'b11111_11111_0011111010_1111101001_0000000001,
-         40'b11111_11111_0011111010_1111101001_0000000001,
-         40'b11111_11111_0011111010_1111101001_0000000001,
-         40'b11111_11111_0011111010_1111101001_0000000001,
-         40'b11111_11111_0011111010_1111101001_0000000001,
-         40'b11111_11111_0011111010_1111101001_0000000001,
-         40'b11111_11111_0011111010_1111101001_0000000001,
-         40'b11111_11111_0011111010_1111101001_0000000001,
-         40'b11111_11111_0011111010_1111101001_0000000001,
-         40'b11111_11111_0011111010_1111101001_0000000001,
-         40'b11111_11111_0011111010_1111101001_0000000001,
-         40'b11111_11111_0011111010_1111101001_0000000001,
-         40'b11111_11111_0011111010_1111101001_0000000001,
-         40'b11111_11111_0011111010_1111101001_0000000001,
-         40'b11111_11111_0011111010_1111101001_0000000001,
-         40'b11111_11111_0011111010_1111101001_0000000001,
-         40'b11111_11111_0011111010_1111101001_0000000001,
-         40'b11111_11111_0011111010_1111101001_0000000001,
-         40'b11111_11111_0011111010_1111101001_0000000001,
-         40'b11111_11111_0011111010_1111101001_0000000001,
-         40'b11111_11111_0011111010_1111101001_0000000001,
-         40'b11111_11111_0011111010_1111101001_0000000001,
-         40'b11111_11111_0011111010_1111101001_0000000001,
-         40'b11111_11111_0011111010_1111101001_0000000001,                                                                    
-         40'b11111_11111_0011111010_1111101001_0000000001,
-         40'b11111_11111_0011111010_1111101001_0000000001,
-         40'b11111_11111_0011111010_1111101001_0000000001,
-         40'b11111_11111_0011111010_1111101001_0000000001,
-         40'b11111_11111_0011111010_1111101001_0000000001,
-         40'b11111_11111_0011111010_1111101001_0000000001,
-         40'b11111_11111_0011111010_1111101001_0000000001,
-         40'b11111_11111_0011111010_1111101001_0000000001,
-         40'b11111_11111_0011111010_1111101001_0000000001,
-         40'b11111_11111_0011111010_1111101001_0000000001,
-         40'b11111_11111_0011111010_1111101001_0000000001,
-         40'b11111_11111_0011111010_1111101001_0000000001,                                                                    
-         40'b11111_11111_0011111010_1111101001_0000000001,
-         40'b11111_11111_0011111010_1111101001_0000000001,
-         40'b11111_11111_0011111010_1111101001_0000000001,
-         40'b11111_11111_0011111010_1111101001_0000000001,
-         40'b11111_11111_0011111010_1111101001_0000000001,
-         40'b11111_11111_0011111010_1111101001_0000000001,
-         40'b11111_11111_0011111010_1111101001_0000000001,      // M=127
-         40'b11111_11111_0011111010_1111101001_0000000001       // M=128
-      };
-      
-      // Set lookup_entry with the explicit bits from lookup with a part select
-      mmcm_pll_lock_lookup = lookup[ ((128-divide)*40) +: 40];
-   `ifdef DEBUG
-      $display("lock_lookup: %b", mmcm_pll_lock_lookup);
-   `endif
-   end
-endfunction
-
-// This function takes the divide value and the bandwidth setting of the MMCM
-//  and outputs the digital filter settings necessary.
-function [9:0] mmcm_pll_filter_lookup
-   (
-      input [7:0] divide, //  input [7:0] divide // Max M divide is 128 in UltraScalePlus
-      input [8*9:0] BANDWIDTH
-   );
-   
-   reg [1279:0] lookup_low;
-   reg [1279:0] lookup_high;
-   
-   reg [9:0] lookup_entry;
-   
-   begin
-      lookup_low = {
-         // CP_RES_LFHF
-       	10'b0011_1111_11,    // M=1 - not legal
-       	10'b0011_1111_11,    // M=2
-       	10'b0011_1101_11,    // M=3
-       	10'b0011_0101_11,    // M=4
-       	10'b0011_1001_11,    // M=5
-       	10'b0011_1110_11,    // M=6
-       	10'b0011_1110_11,    // M=7
-       	10'b0011_0001_11,
-       	10'b0011_0110_11,
-       	10'b0011_0110_11,
-       	10'b0011_0110_11,
-       	10'b0011_1010_11,
-       	10'b0011_1010_11,
-       	10'b0011_1010_11,
-       	10'b0100_0110_11,
-       	10'b0011_1100_11,
-       	10'b1110_0110_11,
-       	10'b1111_0110_11,
-       	10'b1110_1010_11,
-       	10'b1110_1010_11,
-       	10'b1111_1010_11,
-       	10'b1111_1010_11,
-       	10'b1111_1010_11,
-       	10'b1111_1010_11,
-       	10'b1111_1010_11,
-       	10'b1101_1100_11,
-       	10'b1101_1100_11,
-       	10'b1101_1100_11,
-       	10'b1110_1100_11,
-       	10'b1110_1100_11,
-       	10'b1110_1100_11,
-       	10'b1111_1100_11,
-       	10'b1111_1100_11,
-       	10'b1111_1100_11,
-       	10'b1111_1100_11,
-       	10'b1111_1100_11,
-       	10'b1111_1100_11,
-       	10'b1110_0010_11,
-       	10'b1110_0010_11,
-       	10'b1110_0010_11,
-       	10'b1110_0010_11,
-       	10'b1111_0010_11,
-       	10'b1111_0010_11,
-       	10'b1111_0010_11,
-       	10'b1111_0010_11,
-       	10'b1111_0010_11,
-       	10'b1111_0010_11,
-       	10'b1111_0010_11,
-       	10'b1111_0010_11,
-       	10'b1111_0010_11,
-       	10'b1111_0010_11,
-       	10'b1111_0010_11,
-       	10'b1111_0010_11,
-       	10'b1111_0010_11,
-       	10'b1111_0010_11,
-       	10'b1111_0010_11,
-       	10'b1111_0010_11,
-       	10'b1111_0010_11,
-       	10'b1111_0010_11,
-       	10'b1111_0010_11,
-       	10'b1111_0010_11,
-       	10'b1111_0010_11,
-       	10'b1100_0100_11,
-       	10'b1100_0100_11,
-       	10'b1100_0100_11,
-       	10'b1100_0100_11,
-       	10'b1100_0100_11,
-       	10'b1100_0100_11,
-       	10'b1100_0100_11,
-       	10'b1100_0100_11,
-       	10'b1101_0100_11,
-       	10'b1101_0100_11,
-       	10'b1101_0100_11,
-       	10'b1101_0100_11,
-       	10'b1101_0100_11,
-       	10'b1101_0100_11,
-       	10'b1101_0100_11,
-       	10'b1110_0100_11,
-       	10'b1110_0100_11,
-       	10'b1110_0100_11,
-       	10'b1110_0100_11,
-       	10'b1110_0100_11,
-       	10'b1110_0100_11,
-       	10'b1110_0100_11,
-       	10'b1110_0100_11,
-       	10'b1111_0100_11,
-       	10'b1111_0100_11,
-       	10'b1111_0100_11,
-       	10'b1111_0100_11,
-       	10'b1111_0100_11,
-       	10'b1111_0100_11,
-       	10'b1111_0100_11,
-       	10'b1111_0100_11,
-       	10'b1111_0100_11,
-       	10'b1111_0100_11,
-       	10'b1111_0100_11,
-       	10'b1111_0100_11,
-       	10'b1111_0100_11,
-       	10'b1111_0100_11,
-       	10'b1111_0100_11,
-       	10'b1111_0100_11,
-       	10'b1111_0100_11,
-       	10'b1111_0100_11,
-       	10'b1111_0100_11,
-       	10'b1111_0100_11,
-       	10'b1111_0100_11,
-       	10'b1111_0100_11,
-       	10'b1111_0100_11,
-       	10'b1111_0100_11,
-       	10'b1111_0100_11,
-       	10'b1111_0100_11,
-       	10'b1111_0100_11,
-       	10'b1111_0100_11,
-       	10'b1111_0100_11,
-       	10'b1111_0100_11,
-       	10'b1111_0100_11,
-       	10'b1111_0100_11,
-       	10'b1111_0100_11,
-       	10'b1111_0100_11,
-       	10'b1101_1000_11,
-       	10'b1101_1000_11,
-       	10'b1101_1000_11,
-       	10'b1101_1000_11,
-       	10'b1101_1000_11,
-       	10'b1101_1000_11,
-       	10'b1101_1000_11,
-       	10'b1101_1000_11, // M=127
-       	10'b1101_1000_11  // M=128
-};										
-      
-      lookup_high = {
-         // CP_RES_LFHF
-       10'b0111_1111_11,    // M=1 - not legal
-       10'b0111_1111_11,    // M=2
-       10'b1110_1111_11,    // M=3
-       10'b1111_1111_11,    // M=4
-       10'b1111_1011_11,    // M=5
-       10'b1111_1101_11,    // M=6
-       10'b1111_0011_11,    // M=7
-       10'b1110_0101_11,
-       10'b1111_1001_11,
-       10'b1111_1001_11,
-       10'b1110_1110_11,
-       10'b1111_1110_11,
-       10'b1111_0001_11,
-       10'b1111_0001_11,
-       10'b1111_0001_11,
-       10'b1110_0110_11,
-       10'b1110_0110_11,
-       10'b1111_0110_11,
-       10'b1110_1010_11,
-       10'b1110_1010_11,
-       10'b1111_1010_11,
-       10'b1111_1010_11,
-       10'b1111_1010_11,
-       10'b1111_1010_11,
-       10'b1111_1010_11,
-       10'b1101_1100_11,
-       10'b1101_1100_11,
-       10'b1101_1100_11,
-       10'b1110_1100_11,
-       10'b1110_1100_11,
-       10'b1110_1100_11,
-       10'b1111_1100_11,
-       10'b1111_1100_11,
-       10'b1111_1100_11,
-       10'b1111_1100_11,
-       10'b1111_1100_11,
-       10'b1111_1100_11,
-       10'b1110_0010_11,
-       10'b1110_0010_11,
-       10'b1110_0010_11,
-       10'b1110_0010_11,
-       10'b1111_0010_11,
-       10'b1111_0010_11,
-       10'b1111_0010_11,
-       10'b1111_0010_11,
-       10'b1111_0010_11,
-       10'b1111_0010_11,
-       10'b1111_0010_11,
-       10'b1111_0010_11,
-       10'b1111_0010_11,
-       10'b1111_0010_11,
-       10'b1111_0010_11,
-       10'b1111_0010_11,
-       10'b1111_0010_11,
-       10'b1111_0010_11,
-       10'b1111_0010_11,
-       10'b1111_0010_11,
-       10'b1111_0010_11,
-       10'b1111_0010_11,
-       10'b1111_0010_11,
-       10'b1111_0010_11,
-       10'b1111_0010_11,
-       10'b1100_0100_11,
-       10'b1100_0100_11,
-       10'b1100_0100_11,
-       10'b1100_0100_11,
-       10'b1100_0100_11,
-       10'b1100_0100_11,
-       10'b1100_0100_11,
-       10'b1100_0100_11,
-       10'b1101_0100_11,
-       10'b1101_0100_11,
-       10'b1101_0100_11,
-       10'b1101_0100_11,
-       10'b1101_0100_11,
-       10'b1101_0100_11,
-       10'b1101_0100_11,
-       10'b1110_0100_11,
-       10'b1110_0100_11,
-       10'b1110_0100_11,
-       10'b1110_0100_11,
-       10'b1110_0100_11,
-       10'b1110_0100_11,
-       10'b1110_0100_11,
-       10'b1110_0100_11,
-       10'b1111_0100_11,
-       10'b1111_0100_11,
-       10'b1111_0100_11,
-       10'b1111_0100_11,
-       10'b1111_0100_11,
-       10'b1111_0100_11,
-       10'b1111_0100_11,
-       10'b1111_0100_11,
-       10'b1111_0100_11,
-       10'b1111_0100_11,
-       10'b1111_0100_11,
-       10'b1111_0100_11,
-       10'b1111_0100_11,
-       10'b1111_0100_11,
-       10'b1111_0100_11,
-       10'b1111_0100_11,
-       10'b1111_0100_11,
-       10'b1111_0100_11,
-       10'b1111_0100_11,
-       10'b1111_0100_11,
-       10'b1111_0100_11,
-       10'b1111_0100_11,
-       10'b1111_0100_11,
-       10'b1111_0100_11,
-       10'b1111_0100_11,
-       10'b1111_0100_11,
-       10'b1111_0100_11,
-       10'b1111_0100_11,
-       10'b1111_0100_11,
-       10'b1111_0100_11,
-       10'b1111_0100_11,
-       10'b1111_0100_11,
-       10'b1111_0100_11,
-       10'b1111_0100_11,
-       10'b1101_1000_11,
-       10'b1101_1000_11,
-       10'b1101_1000_11,
-       10'b1101_1000_11,
-       10'b1101_1000_11,
-       10'b1101_1000_11,
-       10'b1101_1000_11,
-       10'b1101_1000_11,
-       10'b1101_1000_11     // M=128
-};
-      
-      // Set lookup_entry with the explicit bits from lookup with a part select
-      if(BANDWIDTH == "LOW") begin
-         // Low Bandwidth
-         mmcm_pll_filter_lookup = lookup_low[ ((128-divide)*10) +: 10];
-      end else begin
-         // High or optimized bandwidth
-         mmcm_pll_filter_lookup = lookup_high[ ((128-divide)*10) +: 10];
-      end
-      
-   `ifdef DEBUG
-      $display("filter_lookup: %b", mmcm_pll_filter_lookup);
-   `endif
-   end
-endfunction
-
-// This function takes in the divide, phase, and duty cycle
-// setting to calculate the upper and lower counter registers.
-function [37:0] mmcm_pll_count_calc
-   (
-      input [7:0] divide, // Max divide is 128
-      input signed [31:0] phase,
-      input [31:0] duty_cycle // Multiplied by 100,000
-   );
-   
-   reg [13:0] div_calc;
-   reg [16:0] phase_calc;
-   
-   begin
-   `ifdef DEBUG
-      $display("mmcm_pll_count_calc- divide:%h, phase:%d, duty_cycle:%d",
-         divide, phase, duty_cycle);
-   `endif
-   
-      // w_edge[13], no_count[12], high_time[11:6], low_time[5:0]
-      div_calc = mmcm_pll_divider(divide, duty_cycle);
-      // mx[10:9], pm[8:6], dt[5:0]
-      phase_calc = mmcm_pll_phase(divide, phase);
-
-      // Return value is the upper and lower address of counter
-      //    Upper address is:
-      //       RESERVED    [31:26]
-      //       MX          [25:24]
-      //       EDGE        [23]
-      //       NOCOUNT     [22]
-      //       DELAY_TIME  [21:16]
-      //    Lower Address is:
-      //       PHASE_MUX   [15:13]
-      //       RESERVED    [12]
-      //       HIGH_TIME   [11:6]
-      //       LOW_TIME    [5:0]
-      
-   `ifdef DEBUG
-      $display("div:%d dc:%d phase:%d ht:%d lt:%d ed:%d nc:%d mx:%d dt:%d pm:%d",
-         divide, duty_cycle, phase, div_calc[11:6], div_calc[5:0], 
-         div_calc[13], div_calc[12], 
-         phase_calc[16:15], phase_calc[5:0], phase_calc[14:12]);
-   `endif
-      
-      mmcm_pll_count_calc =
-         {
-            // Upper Address
-            6'h00, phase_calc[10:9], div_calc[13:12], phase_calc[5:0], 
-            // Lower Address
-            phase_calc[8:6], 1'b0, div_calc[11:0]
-         };
-   end
-endfunction
-
-
-// This function takes in the divide, phase, and duty cycle
-// setting to calculate the upper and lower counter registers.
-// for fractional multiply/divide functions.
-//
-// 
-function [37:0] mmcm_frac_count_calc
-   (
-      input [7:0] divide, // Max divide is 128
-      input signed [31:0] phase,
-      input [31:0] duty_cycle, // Multiplied by 100,000. Not programmable in fractional
-      input [9:0] frac // Multiplied by 1000
-   );
-   
-	//Required for fractional divide calculations
-			  reg	[7:0]			lt_frac;
-			  reg	[7:0]			ht_frac;
-			
-			  reg	/*[7:0]*/			wf_fall_frac;
-			  reg	/*[7:0]*/			wf_rise_frac;
-
-			  reg [31:0] a;
-			  reg	[7:0]			pm_rise_frac_filtered ;
-			  reg	[7:0]			pm_fall_frac_filtered ;	
-			  reg [7:0]			clkout0_divide_int;
-			  reg [2:0]			clkout0_divide_frac;
-			  reg	[7:0]			even_part_high;
-			  reg	[7:0]			even_part_low;
-
-			  reg	[7:0]			odd;
-			  reg	[7:0]			odd_and_frac;
-
-			  reg	[7:0]			pm_fall;
-			  reg	[7:0]			pm_rise;
-			  reg	[7:0]			dt;
-			  reg	[7:0]			dt_int; 
-			  reg [63:0]		dt_calc;
-
-			  reg	[7:0]			pm_rise_frac; 
-			  reg	[7:0]			pm_fall_frac;
-	 
-			  reg [31:0] a_per_in_octets;
-			  reg [31:0] a_phase_in_cycles;
-
-				parameter precision = 0.125;
-
-			  reg [31:0] phase_fixed; // changed to 31:0 from 32:1 jt 5/2/11
-			  reg [31: 0] phase_pos;
-			  reg [31: 0] phase_vco;
-			  reg [31:0] temp;// changed to 31:0 from 32:1 jt 5/2/11
-			  reg [13:0] div_calc;
-			  reg [16:0] phase_calc;
-
-   begin
-	`ifdef DEBUG
-			$display("mmcm_frac_count_calc- divide:%h, phase:%d, duty_cycle:%d",
-				divide, phase, duty_cycle);
-	`endif
-   
-   //convert phase to fixed
-   if ((phase < -360000) || (phase > 360000)) begin
-`ifndef SYNTHESIS
-      $display("ERROR: phase of $phase is not between -360000 and 360000");
-	`endif
-      $finish;
-   end
-
-
-      // Return value is
-      //    Transfer data
-      //       RESERVED     [37:36]
-      //       FRAC_TIME    [35:33]
-      //       FRAC_WF_FALL [32]
-      //    Upper address is:
-      //       RESERVED     [31:26]
-      //       MX           [25:24]
-      //       EDGE         [23]
-      //       NOCOUNT      [22]
-      //       DELAY_TIME   [21:16]
-      //    Lower Address is:
-      //       PHASE_MUX    [15:13]
-      //       RESERVED     [12]
-      //       HIGH_TIME    [11:6]
-      //       LOW_TIME     [5:0]
-      
-      
-
-	clkout0_divide_frac = frac / 125;
-	clkout0_divide_int = divide;
-
-	even_part_high = clkout0_divide_int >> 1;//$rtoi(clkout0_divide_int / 2);
-	even_part_low = even_part_high;
-									
-	odd = clkout0_divide_int - even_part_high - even_part_low;
-	odd_and_frac = (8*odd) + clkout0_divide_frac;
-
-	lt_frac = even_part_high - (odd_and_frac <= 9);//IF(odd_and_frac>9,even_part_high, even_part_high - 1)
-	ht_frac = even_part_low  - (odd_and_frac <= 8);//IF(odd_and_frac>8,even_part_low, even_part_low- 1)
-
-	pm_fall =  {odd[6:0],2'b00} + {6'h00, clkout0_divide_frac[2:1]}; // using >> instead of clkout0_divide_frac / 2 
-	pm_rise = 0; //0
-    
-	wf_fall_frac = ((odd_and_frac >=2) && (odd_and_frac <=9)) || (clkout0_divide_int == 2 && clkout0_divide_frac == 1);   //IF(odd_and_frac>=2,IF(odd_and_frac <= 9,1,0),0)
-	wf_rise_frac = (odd_and_frac >=1) && (odd_and_frac <=8);    //IF(odd_and_frac>=1,IF(odd_and_frac <= 8,1,0),0)
-
-
-
-	//Calculate phase in fractional cycles
-	a_per_in_octets		= (8 * divide) + (frac / 125) ;
-	a_phase_in_cycles	= (phase+10) * a_per_in_octets / 360000 ;//Adding 1 due to rounding errors
-	pm_rise_frac		= (a_phase_in_cycles[7:0] ==8'h00)?8'h00:a_phase_in_cycles[7:0] - {a_phase_in_cycles[7:3],3'b000};
-
-	dt_calc 	= ((phase+10) * a_per_in_octets / 8 )/360000 ;//TRUNC(phase* divide / 360); //or_simply (a_per_in_octets / 8)
-	dt 	= dt_calc[7:0];
-
-	pm_rise_frac_filtered = (pm_rise_frac >=8) ? (pm_rise_frac ) - 8: pm_rise_frac ;				//((phase_fixed * (divide + frac / 1000)) / 360) - {pm_rise_frac[7:3],3'b000};//$rtoi(clkout0_phase * clkout0_divide / 45);//a;
-
-	dt_int			= dt + (& pm_rise_frac[7:4]); //IF(pm_rise_overwriting>7,dt+1,dt)
-	pm_fall_frac		= pm_fall + pm_rise_frac;
-	pm_fall_frac_filtered	= pm_fall + pm_rise_frac - {pm_fall_frac[7:3], 3'b000};
-
-	div_calc	= mmcm_pll_divider(divide, duty_cycle); //Use to determine edge[7], no count[6]
-	phase_calc	= mmcm_pll_phase(divide, phase);// returns{mx[1:0], phase_mux[2:0], delay_time[5:0]}
-		
-      mmcm_frac_count_calc[37:0] =
-         {		2'b00, pm_fall_frac_filtered[2:0], wf_fall_frac,
-			1'b0, clkout0_divide_frac[2:0], 1'b1, wf_rise_frac, phase_calc[10:9], 2'b00, dt[5:0], 
-			pm_rise_frac_filtered[2], pm_rise_frac_filtered[1], pm_rise_frac_filtered[0], 1'b0, ht_frac[5:0], lt_frac[5:0]
-		} ;
-
-   `ifdef DEBUG
-      $display("-%d.%d p%d>>  :DADDR_9_15 frac30to28.frac_en.wf_r_frac.dt:%b%d%d_%b:DADDR_7_13 pm_f_frac_filtered_29to27.wf_f_frac_26:%b%d:DADDR_8_14.pm_r_frac_filt_15to13.ht_frac.lt_frac:%b%b%b:", divide, frac, phase, clkout0_divide_frac, 1, wf_rise_frac, dt, pm_fall_frac_filtered, wf_fall_frac, pm_rise_frac_filtered, ht_frac, lt_frac);
-   `endif
-
-   end
-endfunction
-

LAB2/src/pak_depak/ipshared/d0f7/mmcm_pll_drp_func_us_plus_pll.vh

@@ -1,536 +0,0 @@
-///////////////////////////////////////////////////////////////////////////////
-//    
-//    Company:          Xilinx
-//    Engineer:         Jim Tatsukawa, Ralf Krueger, updated for Ultrascale+ 
-//    Date:             6/15/2015
-//    Design Name:      PLLE4 DRP
-//    Module Name:      plle4_drp_func.h
-//    Version:          2.0
-//    Target Devices:   UltraScale+ Architecture
-//    Tool versions:    2017.1
-//    Description:      This header provides the functions necessary to  
-//                      calculate the DRP register values for the V6 PLL.
-//                      
-//	Revision Notes:	8/11 - PLLE3 updated for PLLE3 file 4564419
-//	Revision Notes:	6/15 - pll_filter_lookup fixed for max M of 19
-//                           M_Rise bits have been removed for PLLE3
-//	Revision Notes:	2/28/17 - pll_filter_lookup and CPRES updated for 
-//                           Ultrascale+ and for max M of 21
-// 
-//    Disclaimer:  XILINX IS PROVIDING THIS DESIGN, CODE, OR
-//                 INFORMATION "AS IS" SOLELY FOR USE IN DEVELOPING
-//                 PROGRAMS AND SOLUTIONS FOR XILINX DEVICES.  BY
-//                 PROVIDING THIS DESIGN, CODE, OR INFORMATION AS
-//                 ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE,
-//                 APPLICATION OR STANDARD, XILINX IS MAKING NO
-//                 REPRESENTATION THAT THIS IMPLEMENTATION IS FREE
-//                 FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE
-//                 RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY
-//                 REQUIRE FOR YOUR IMPLEMENTATION.  XILINX
-//                 EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH
-//                 RESPECT TO THE ADEQUACY OF THE IMPLEMENTATION,
-//                 INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR
-//                 REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE
-//                 FROM CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES
-//                 OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-//                 PURPOSE.
-// 
-//                 (c) Copyright 2009-2017 Xilinx, Inc.
-//                 All rights reserved.
-// 
-///////////////////////////////////////////////////////////////////////////////
-
-// These are user functions that should not be modified.  Changes to the defines
-// or code within the functions may alter the accuracy of the calculations.
-
-// Define debug to provide extra messages durring elaboration
-//`define DEBUG 1
-
-// FRAC_PRECISION describes the width of the fractional portion of the fixed
-//    point numbers.  These should not be modified, they are for development 
-//    only
-`define FRAC_PRECISION  10
-// FIXED_WIDTH describes the total size for fixed point calculations(int+frac).
-// Warning: L.50 and below will not calculate properly with FIXED_WIDTHs 
-//    greater than 32
-`define FIXED_WIDTH     32 
-
-// This function takes a fixed point number and rounds it to the nearest
-//    fractional precision bit.
-function [`FIXED_WIDTH:1] round_frac
-   (
-      // Input is (FIXED_WIDTH-FRAC_PRECISION).FRAC_PRECISION fixed point number
-      input [`FIXED_WIDTH:1] decimal,  
-
-      // This describes the precision of the fraction, for example a value
-      //    of 1 would modify the fractional so that instead of being a .16
-      //    fractional, it would be a .1 (rounded to the nearest 0.5 in turn)
-      input [`FIXED_WIDTH:1] precision 
-   );
-
-   begin
-   
-   `ifdef DEBUG
-      $display("round_frac - decimal: %h, precision: %h", decimal, precision);
-   `endif
-      // If the fractional precision bit is high then round up
-      if( decimal[(`FRAC_PRECISION-precision)] == 1'b1) begin
-         round_frac = decimal + (1'b1 << (`FRAC_PRECISION-precision));
-      end else begin
-         round_frac = decimal;
-      end
-   `ifdef DEBUG
-      $display("round_frac: %h", round_frac);
-   `endif
-   end
-endfunction
-
-// This function calculates high_time, low_time, w_edge, and no_count
-//    of a non-fractional counter based on the divide and duty cycle
-//
-// NOTE: high_time and low_time are returned as integers between 0 and 63 
-//    inclusive.  64 should equal 6'b000000 (in other words it is okay to 
-//    ignore the overflow)
-function [13:0] mmcm_pll_divider
-   (
-      input [7:0] divide,        // Max divide is 128
-      input [31:0] duty_cycle    // Duty cycle is multiplied by 100,000
-   );
-
-   reg [`FIXED_WIDTH:1]    duty_cycle_fix;
-   
-   // High/Low time is initially calculated with a wider integer to prevent a
-   // calculation error when it overflows to 64.
-   reg [6:0]               high_time;
-   reg [6:0]               low_time;
-   reg                     w_edge;
-   reg                     no_count;
-
-   reg [`FIXED_WIDTH:1]    temp;
-
-   begin
-      // Duty Cycle must be between 0 and 1,000
-      if(duty_cycle <=0 || duty_cycle >= 100000) begin
-`ifndef SYNTHESIS
-         $display("ERROR: duty_cycle: %d is invalid", duty_cycle);
-   `endif
-         $finish;
-      end
-
-      // Convert to FIXED_WIDTH-FRAC_PRECISION.FRAC_PRECISION fixed point
-      duty_cycle_fix = (duty_cycle << `FRAC_PRECISION) / 100_000;
-      
-   `ifdef DEBUG
-      $display("duty_cycle_fix: %h", duty_cycle_fix);
-   `endif
-
-      // If the divide is 1 nothing needs to be set except the no_count bit.
-      //    Other values are dummies
-      if(divide == 7'h01) begin
-         high_time   = 7'h01;
-         w_edge      = 1'b0;
-         low_time    = 7'h01;
-         no_count    = 1'b1;
-      end else begin
-         temp = round_frac(duty_cycle_fix*divide, 1);
-
-         // comes from above round_frac
-         high_time   = temp[`FRAC_PRECISION+7:`FRAC_PRECISION+1]; 
-         // If the duty cycle * divide rounded is .5 or greater then this bit
-         //    is set.
-         w_edge      = temp[`FRAC_PRECISION]; // comes from round_frac
-         
-         // If the high time comes out to 0, it needs to be set to at least 1
-         // and w_edge set to 0
-         if(high_time == 7'h00) begin
-            high_time   = 7'h01;
-            w_edge      = 1'b0;
-         end
-
-         if(high_time == divide) begin
-            high_time   = divide - 1;
-            w_edge      = 1'b1;
-         end
-         
-         // Calculate low_time based on the divide setting and set no_count to
-         //    0 as it is only used when divide is 1.
-         low_time    = divide - high_time; 
-         no_count    = 1'b0;
-      end
-
-      // Set the return value.
-      mmcm_pll_divider = {w_edge,no_count,high_time[5:0],low_time[5:0]};
-   end
-endfunction
-
-// This function calculates mx, delay_time, and phase_mux 
-//  of a non-fractional counter based on the divide and phase
-//
-// NOTE: The only valid value for the MX bits is 2'b00 to ensure the coarse mux
-//    is used.
-function [10:0] mmcm_pll_phase
-   (
-      // divide must be an integer (use fractional if not)
-      //  assumed that divide already checked to be valid
-      input [7:0] divide, // Max divide is 128
-
-      // Phase is given in degrees (-360,000 to 360,000)
-      input signed [31:0] phase
-   );
-
-   reg [`FIXED_WIDTH:1] phase_in_cycles;
-   reg [`FIXED_WIDTH:1] phase_fixed;
-   reg [1:0]            mx;
-   reg [5:0]            delay_time;
-   reg [2:0]            phase_mux;
-
-   reg [`FIXED_WIDTH:1] temp;
-
-   begin
-`ifdef DEBUG
-      $display("pll_phase-divide:%d,phase:%d",
-         divide, phase);
-`endif
-   
-      if ((phase < -360000) || (phase > 360000)) begin
-`ifndef SYNTHESIS
-         $display("ERROR: phase of $phase is not between -360000 and 360000");
-`endif
-         $finish;
-      end
-
-      // If phase is less than 0, convert it to a positive phase shift
-      // Convert to (FIXED_WIDTH-FRAC_PRECISION).FRAC_PRECISION fixed point
-      if(phase < 0) begin
-         phase_fixed = ( (phase + 360000) << `FRAC_PRECISION ) / 1000;
-      end else begin
-         phase_fixed = ( phase << `FRAC_PRECISION ) / 1000;
-      end
-
-      // Put phase in terms of decimal number of vco clock cycles
-      phase_in_cycles = ( phase_fixed * divide ) / 360;
-
-`ifdef DEBUG
-      $display("phase_in_cycles: %h", phase_in_cycles);
-`endif  
-      
-
-	 temp  =  round_frac(phase_in_cycles, 3);
-
-	 // set mx to 2'b00 that the phase mux from the VCO is enabled
-	 mx    			=  2'b00; 
-	 phase_mux      =  temp[`FRAC_PRECISION:`FRAC_PRECISION-2];
-	 delay_time     =  temp[`FRAC_PRECISION+6:`FRAC_PRECISION+1];
-      
-   `ifdef DEBUG
-      $display("temp: %h", temp);
-   `endif
-
-      // Setup the return value
-      mmcm_pll_phase={mx, phase_mux, delay_time};
-   end
-endfunction
-
-// This function takes the divide value and outputs the necessary lock values
-function [39:0] mmcm_pll_lock_lookup
-   (
-      input [6:0] divide // Max divide is 21
-   );
-   
-   reg [839:0]   lookup;
-   
-   begin
-      lookup = {
-         // This table is composed of:
-         // LockRefDly_LockFBDly_LockCnt_LockSatHigh_UnlockCnt
-         40'b00110_00110_1111101000_1111101001_0000000001, //1 illegal in Ultrascale+
-         40'b00110_00110_1111101000_1111101001_0000000001, //2
-         40'b01000_01000_1111101000_1111101001_0000000001, //3
-         40'b01011_01011_1111101000_1111101001_0000000001, //4
-         40'b01110_01110_1111101000_1111101001_0000000001, //5
-         40'b10001_10001_1111101000_1111101001_0000000001, //6
-         40'b10011_10011_1111101000_1111101001_0000000001, //7
-         40'b10110_10110_1111101000_1111101001_0000000001, //8
-         40'b11001_11001_1111101000_1111101001_0000000001, //9
-         40'b11100_11100_1111101000_1111101001_0000000001, //10
-         40'b11111_11111_1110000100_1111101001_0000000001, //11
-         40'b11111_11111_1100111001_1111101001_0000000001, //12
-         40'b11111_11111_1011101110_1111101001_0000000001, //13
-         40'b11111_11111_1010111100_1111101001_0000000001, //14
-         40'b11111_11111_1010001010_1111101001_0000000001, //15
-         40'b11111_11111_1001110001_1111101001_0000000001, //16
-         40'b11111_11111_1000111111_1111101001_0000000001, //17
-         40'b11111_11111_1000100110_1111101001_0000000001, //18
-         40'b11111_11111_1000001101_1111101001_0000000001, //19
-         40'b11111_11111_0111110100_1111101001_0000000001, //20
-         40'b11111_11111_0111011011_1111101001_0000000001  //21
-      };
-      
-      // Set lookup_entry with the explicit bits from lookup with a part select
-      mmcm_pll_lock_lookup = lookup[ ((21-divide)*40) +: 40];
-   `ifdef DEBUG
-      $display("lock_lookup: %b", pll_lock_lookup);
-   `endif
-   end
-endfunction
-
-// This function takes the divide value and the bandwidth setting of the PLL
-//  and outputs the digital filter settings necessary. Removing bandwidth setting for PLLE3.
-function [9:0] mmcm_pll_filter_lookup
-   (
-      input [6:0] divide // Max divide is 21
-   );
-   
-   reg [209:0] lookup;
-   reg [9:0] lookup_entry;
-   
-   begin
-
-      lookup = {
-         // CP_RES_LFHF
-         10'b0011_0111_11, //1  not legal in Ultrascale+
-         10'b0011_0111_11, //2
-         10'b0011_0011_11, //3
-         10'b0011_1001_11, //4
-         10'b0011_0001_11, //5
-         10'b0100_1110_11, //6
-         10'b0011_0110_11, //7
-         10'b0011_1010_11, //8
-         10'b0111_1001_11, //9
-         10'b0111_1001_11, //10
-         10'b0101_0110_11, //11
-         10'b1100_0101_11, //12
-         10'b0101_1010_11, //13
-         10'b0110_0110_11, //14
-         10'b0110_1010_11, //15
-         10'b0111_0110_11, //16
-         10'b1111_0101_11, //17
-         10'b1100_0110_11, //18
-         10'b1110_0001_11, //19
-         10'b1101_0110_11, //20
-         10'b1111_0001_11  //21
-      };
-      
-         mmcm_pll_filter_lookup = lookup [ ((21-divide)*10) +: 10];
-      
-   `ifdef DEBUG
-      $display("filter_lookup: %b", pll_filter_lookup);
-   `endif
-   end
-endfunction
-
-// This function set the CLKOUTPHY divide settings to match
-// the desired CLKOUTPHY_MODE setting. To create VCO_X2, then
-// the CLKOUTPHY will be set to 2'b00 since the VCO is internally
-// doubled and 2'b00 will represent divide by 1. Similarly "VCO" 
-// will need to divide the doubled clock VCO clock frequency by 
-// 2 therefore 2'b01 will match a divide by 2.And VCO_HALF will 
-// need to divide the doubled VCO by 4, therefore 2'b10
-function [9:0] mmcm_pll_clkoutphy_calc
-   (
-      input [8*9:0] CLKOUTPHY_MODE
-   );
-
-      if(CLKOUTPHY_MODE == "VCO_X2") begin
-         mmcm_pll_clkoutphy_calc= 2'b00;
-      end else if(CLKOUTPHY_MODE == "VCO") begin
-         mmcm_pll_clkoutphy_calc= 2'b01;
-      end else if(CLKOUTPHY_MODE == "CLKIN") begin
-         mmcm_pll_clkoutphy_calc= 2'b11;
-      end else begin // Assume "VCO_HALF"
-         mmcm_pll_clkoutphy_calc= 2'b10;
-      end
-      
-endfunction
-
-
-// This function takes in the divide, phase, and duty cycle
-// setting to calculate the upper and lower counter registers.
-function [37:0] mmcm_pll_count_calc
-   (
-      input [7:0] divide, // Max divide is 128
-      input signed [31:0] phase,
-      input [31:0] duty_cycle // Multiplied by 100,000
-   );
-   
-   reg [13:0] div_calc;
-   reg [16:0] phase_calc;
-   
-   begin
-   `ifdef DEBUG
-      $display("pll_count_calc- divide:%h, phase:%d, duty_cycle:%d",
-         divide, phase, duty_cycle);
-   `endif
-   
-      // w_edge[13], no_count[12], high_time[11:6], low_time[5:0]
-      div_calc = mmcm_pll_divider(divide, duty_cycle);
-      // mx[10:9], pm[8:6], dt[5:0]
-      phase_calc = mmcm_pll_phase(divide, phase);
-
-      // Return value is the upper and lower address of counter
-      //    Upper address is:
-      //       RESERVED    [31:26]
-      //       MX          [25:24]
-      //       EDGE        [23]
-      //       NOCOUNT     [22]
-      //       DELAY_TIME  [21:16]
-      //    Lower Address is:
-      //       PHASE_MUX   [15:13]
-      //       RESERVED    [12]
-      //       HIGH_TIME   [11:6]
-      //       LOW_TIME    [5:0]
-      
-   `ifdef DEBUG
-      $display("div:%d dc:%d phase:%d ht:%d lt:%d ed:%d nc:%d mx:%d dt:%d pm:%d",
-         divide, duty_cycle, phase, div_calc[11:6], div_calc[5:0], 
-         div_calc[13], div_calc[12], 
-         phase_calc[16:15], phase_calc[5:0], 3'b000); //Removed PM_Rise bits
-   `endif
-      
-      mmcm_pll_count_calc =
-         {
-            // Upper Address
-            6'h00, phase_calc[10:9], div_calc[13:12], phase_calc[5:0], 
-            // Lower Address
-            phase_calc[8:6], 1'b0, div_calc[11:0]
-         };
-   end
-endfunction
-
-
-// This function takes in the divide, phase, and duty cycle
-// setting to calculate the upper and lower counter registers.
-// for fractional multiply/divide functions.
-//
-// 
-function [37:0] mmcm_pll_frac_count_calc
-   (
-      input [7:0] divide, // Max divide is 128
-      input signed [31:0] phase,
-      input [31:0] duty_cycle, // Multiplied by 1,000
-      input [9:0] frac // Multiplied by 1000
-   );
-   
-	//Required for fractional divide calculations
-			  reg	[7:0]			lt_frac;
-			  reg	[7:0]			ht_frac;
-			
-			  reg	/*[7:0]*/			wf_fall_frac;
-			  reg	/*[7:0]*/			wf_rise_frac;
-
-			  reg [31:0] a;
-			  reg	[7:0]			pm_rise_frac_filtered ;
-			  reg	[7:0]			pm_fall_frac_filtered ;	
-			  reg [7:0]			clkout0_divide_int;
-			  reg [2:0]			clkout0_divide_frac;
-			  reg	[7:0]			even_part_high;
-			  reg	[7:0]			even_part_low;
-
-			  reg	[7:0]			odd;
-			  reg	[7:0]			odd_and_frac;
-
-			  reg	[7:0]			pm_fall;
-			  reg	[7:0]			pm_rise;
-			  reg	[7:0]			dt;
-			  reg	[7:0]			dt_int; 
-			  reg [63:0]		dt_calc;
-
-			  reg	[7:0]			pm_rise_frac; 
-			  reg	[7:0]			pm_fall_frac;
-	 
-			  reg [31:0] a_per_in_octets;
-			  reg [31:0] a_phase_in_cycles;
-
-				parameter precision = 0.125;
-
-			  reg [31:0] phase_fixed; // changed to 31:0 from 32:1 jt 5/2/11
-			  reg [31: 0] phase_pos;
-			  reg [31: 0] phase_vco;
-			  reg [31:0] temp;// changed to 31:0 from 32:1 jt 5/2/11
-			  reg [13:0] div_calc;
-			  reg [16:0] phase_calc;
-
-   begin
-	`ifdef DEBUG
-			$display("pll_frac_count_calc- divide:%h, phase:%d, duty_cycle:%d",
-				divide, phase, duty_cycle);
-	`endif
-   
-   //convert phase to fixed
-   if ((phase < -360000) || (phase > 360000)) begin
-`ifndef SYNTHESIS
-      $display("ERROR: phase of $phase is not between -360000 and 360000");
-	`endif
-      $finish;
-   end
-
-
-      // Return value is
-      //    Transfer data
-      //       RESERVED     [37:36]
-      //       FRAC_TIME    [35:33]
-      //       FRAC_WF_FALL [32]
-      //    Upper address is:
-      //       RESERVED     [31:26]
-      //       MX           [25:24]
-      //       EDGE         [23]
-      //       NOCOUNT      [22]
-      //       DELAY_TIME   [21:16]
-      //    Lower Address is:
-      //       PHASE_MUX    [15:13]
-      //       RESERVED     [12]
-      //       HIGH_TIME    [11:6]
-      //       LOW_TIME     [5:0]
-      
-      
-
-	clkout0_divide_frac = frac / 125;
-	clkout0_divide_int = divide;
-
-	even_part_high = clkout0_divide_int >> 1;//$rtoi(clkout0_divide_int / 2);
-	even_part_low = even_part_high;
-									
-	odd = clkout0_divide_int - even_part_high - even_part_low;
-	odd_and_frac = (8*odd) + clkout0_divide_frac;
-
-	lt_frac = even_part_high - (odd_and_frac <= 9);//IF(odd_and_frac>9,even_part_high, even_part_high - 1)
-	ht_frac = even_part_low  - (odd_and_frac <= 8);//IF(odd_and_frac>8,even_part_low, even_part_low- 1)
-
-	pm_fall =  {odd[6:0],2'b00} + {6'h00, clkout0_divide_frac[2:1]}; // using >> instead of clkout0_divide_frac / 2 
-	pm_rise = 0; //0
-    
-	wf_fall_frac = (odd_and_frac >=2) && (odd_and_frac <=9);//IF(odd_and_frac>=2,IF(odd_and_frac <= 9,1,0),0)
-	wf_rise_frac = (odd_and_frac >=1) && (odd_and_frac <=8);//IF(odd_and_frac>=1,IF(odd_and_frac <= 8,1,0),0)
-
-
-
-	//Calculate phase in fractional cycles
-	a_per_in_octets		= (8 * divide) + (frac / 125) ;
-	a_phase_in_cycles	= (phase+10) * a_per_in_octets / 360000 ;//Adding 1 due to rounding errors
-	pm_rise_frac		= (a_phase_in_cycles[7:0] ==8'h00)?8'h00:a_phase_in_cycles[7:0] - {a_phase_in_cycles[7:3],3'b000};
-
-	dt_calc 	= ((phase+10) * a_per_in_octets / 8 )/360000 ;//TRUNC(phase* divide / 360); //or_simply (a_per_in_octets / 8)
-	dt 	= dt_calc[7:0];
-
-	pm_rise_frac_filtered = (pm_rise_frac >=8) ? (pm_rise_frac ) - 8: pm_rise_frac ;				//((phase_fixed * (divide + frac / 1000)) / 360) - {pm_rise_frac[7:3],3'b000};//$rtoi(clkout0_phase * clkout0_divide / 45);//a;
-
-	dt_int			= dt + (& pm_rise_frac[7:4]); //IF(pm_rise_overwriting>7,dt+1,dt)
-	pm_fall_frac		= pm_fall + pm_rise_frac;
-	pm_fall_frac_filtered	= pm_fall + pm_rise_frac - {pm_fall_frac[7:3], 3'b000};
-
-	div_calc	= mmcm_pll_divider(divide, duty_cycle); //Use to determine edge[7], no count[6]
-	phase_calc	= mmcm_pll_phase(divide, phase);// returns{mx[1:0], phase_mux[2:0], delay_time[5:0]}
-		
-      mmcm_pll_frac_count_calc[37:0] =
-         {		2'b00, pm_fall_frac_filtered[2:0], wf_fall_frac,
-			1'b0, clkout0_divide_frac[2:0], 1'b1, wf_rise_frac, phase_calc[10:9], div_calc[13:12], dt[5:0], 
-			3'b000, 1'b0, ht_frac[5:0], lt_frac[5:0] //Removed PM_Rise bits
-		} ;
-
-   `ifdef DEBUG
-      $display("-%d.%d p%d>>  :DADDR_9_15 frac30to28.frac_en.wf_r_frac.dt:%b%d%d_%b:DADDR_7_13 pm_f_frac_filtered_29to27.wf_f_frac_26:%b%d:DADDR_8_14.pm_r_frac_filt_15to13.ht_frac.lt_frac:%b%b%b:", divide, frac, phase, clkout0_divide_frac, 1, wf_rise_frac, dt, pm_fall_frac_filtered, wf_fall_frac, 3'b000, ht_frac, lt_frac);
-   `endif
-
-   end
-endfunction
-

LAB2/src/pak_depak/pak_depak.bd

@@ -1,474 +0,0 @@
-{
-  "design": {
-    "design_info": {
-      "boundary_crc": "0x9157799052A71E23",
-      "device": "xc7a35tcpg236-1",
-      "name": "pak_depak",
-      "rev_ctrl_bd_flag": "RevCtrlBdOff",
-      "synth_flow_mode": "None",
-      "tool_version": "2020.2"
-    },
-    "design_tree": {
-      "proc_sys_reset_0": "",
-      "clk_wiz_0": "",
-      "AXI4Stream_UART_0": "",
-      "depacketizer_0": "",
-      "packetizer_0": ""
-    },
-    "interface_ports": {
-      "usb_uart": {
-        "mode": "Master",
-        "vlnv": "xilinx.com:interface:uart_rtl:1.0"
-      }
-    },
-    "ports": {
-      "reset": {
-        "type": "rst",
-        "direction": "I",
-        "parameters": {
-          "POLARITY": {
-            "value": "ACTIVE_HIGH"
-          }
-        }
-      },
-      "sys_clock": {
-        "type": "clk",
-        "direction": "I",
-        "parameters": {
-          "FREQ_HZ": {
-            "value": "100000000"
-          },
-          "PHASE": {
-            "value": "0.000"
-          }
-        }
-      }
-    },
-    "components": {
-      "proc_sys_reset_0": {
-        "vlnv": "xilinx.com:ip:proc_sys_reset:5.0",
-        "xci_name": "pak_depak_proc_sys_reset_0_0",
-        "xci_path": "ip\\pak_depak_proc_sys_reset_0_0\\pak_depak_proc_sys_reset_0_0.xci",
-        "inst_hier_path": "proc_sys_reset_0",
-        "parameters": {
-          "RESET_BOARD_INTERFACE": {
-            "value": "reset"
-          },
-          "USE_BOARD_FLOW": {
-            "value": "true"
-          }
-        }
-      },
-      "clk_wiz_0": {
-        "vlnv": "xilinx.com:ip:clk_wiz:6.0",
-        "xci_name": "pak_depak_clk_wiz_0_1",
-        "xci_path": "ip\\pak_depak_clk_wiz_0_1\\pak_depak_clk_wiz_0_1.xci",
-        "inst_hier_path": "clk_wiz_0",
-        "parameters": {
-          "CLK_IN1_BOARD_INTERFACE": {
-            "value": "sys_clock"
-          },
-          "RESET_BOARD_INTERFACE": {
-            "value": "reset"
-          },
-          "USE_BOARD_FLOW": {
-            "value": "true"
-          }
-        }
-      },
-      "AXI4Stream_UART_0": {
-        "vlnv": "DigiLAB:ip:AXI4Stream_UART:1.1",
-        "xci_name": "pak_depak_AXI4Stream_UART_0_0",
-        "xci_path": "ip\\pak_depak_AXI4Stream_UART_0_0\\pak_depak_AXI4Stream_UART_0_0.xci",
-        "inst_hier_path": "AXI4Stream_UART_0",
-        "parameters": {
-          "UART_BOARD_INTERFACE": {
-            "value": "usb_uart"
-          },
-          "USE_BOARD_FLOW": {
-            "value": "true"
-          }
-        }
-      },
-      "depacketizer_0": {
-        "vlnv": "xilinx.com:module_ref:depacketizer:1.0",
-        "xci_name": "pak_depak_depacketizer_0_0",
-        "xci_path": "ip\\pak_depak_depacketizer_0_0\\pak_depak_depacketizer_0_0.xci",
-        "inst_hier_path": "depacketizer_0",
-        "reference_info": {
-          "ref_type": "hdl",
-          "ref_name": "depacketizer",
-          "boundary_crc": "0x0"
-        },
-        "interface_ports": {
-          "m_axis": {
-            "mode": "Master",
-            "vlnv": "xilinx.com:interface:axis_rtl:1.0",
-            "parameters": {
-              "TDATA_NUM_BYTES": {
-                "value": "1",
-                "value_src": "constant"
-              },
-              "TDEST_WIDTH": {
-                "value": "0",
-                "value_src": "constant"
-              },
-              "TID_WIDTH": {
-                "value": "0",
-                "value_src": "constant"
-              },
-              "TUSER_WIDTH": {
-                "value": "0",
-                "value_src": "constant"
-              },
-              "HAS_TREADY": {
-                "value": "1",
-                "value_src": "constant"
-              },
-              "HAS_TSTRB": {
-                "value": "0",
-                "value_src": "constant"
-              },
-              "HAS_TKEEP": {
-                "value": "0",
-                "value_src": "constant"
-              },
-              "HAS_TLAST": {
-                "value": "1",
-                "value_src": "constant"
-              }
-            },
-            "port_maps": {
-              "TDATA": {
-                "physical_name": "m_axis_tdata",
-                "direction": "O",
-                "left": "7",
-                "right": "0"
-              },
-              "TLAST": {
-                "physical_name": "m_axis_tlast",
-                "direction": "O"
-              },
-              "TVALID": {
-                "physical_name": "m_axis_tvalid",
-                "direction": "O"
-              },
-              "TREADY": {
-                "physical_name": "m_axis_tready",
-                "direction": "I"
-              }
-            }
-          },
-          "s_axis": {
-            "mode": "Slave",
-            "vlnv": "xilinx.com:interface:axis_rtl:1.0",
-            "parameters": {
-              "TDATA_NUM_BYTES": {
-                "value": "1",
-                "value_src": "constant"
-              },
-              "TDEST_WIDTH": {
-                "value": "0",
-                "value_src": "constant"
-              },
-              "TID_WIDTH": {
-                "value": "0",
-                "value_src": "constant"
-              },
-              "TUSER_WIDTH": {
-                "value": "0",
-                "value_src": "constant"
-              },
-              "HAS_TREADY": {
-                "value": "1",
-                "value_src": "constant"
-              },
-              "HAS_TSTRB": {
-                "value": "0",
-                "value_src": "constant"
-              },
-              "HAS_TKEEP": {
-                "value": "0",
-                "value_src": "constant"
-              },
-              "HAS_TLAST": {
-                "value": "0",
-                "value_src": "constant"
-              }
-            },
-            "port_maps": {
-              "TDATA": {
-                "physical_name": "s_axis_tdata",
-                "direction": "I",
-                "left": "7",
-                "right": "0"
-              },
-              "TVALID": {
-                "physical_name": "s_axis_tvalid",
-                "direction": "I"
-              },
-              "TREADY": {
-                "physical_name": "s_axis_tready",
-                "direction": "O"
-              }
-            }
-          }
-        },
-        "ports": {
-          "clk": {
-            "type": "clk",
-            "direction": "I",
-            "parameters": {
-              "ASSOCIATED_BUSIF": {
-                "value": "m_axis:s_axis",
-                "value_src": "constant"
-              },
-              "ASSOCIATED_RESET": {
-                "value": "aresetn",
-                "value_src": "constant"
-              }
-            }
-          },
-          "aresetn": {
-            "type": "rst",
-            "direction": "I",
-            "parameters": {
-              "POLARITY": {
-                "value": "ACTIVE_LOW",
-                "value_src": "constant"
-              }
-            }
-          }
-        }
-      },
-      "packetizer_0": {
-        "vlnv": "xilinx.com:module_ref:packetizer:1.0",
-        "xci_name": "pak_depak_packetizer_0_0",
-        "xci_path": "ip\\pak_depak_packetizer_0_0\\pak_depak_packetizer_0_0.xci",
-        "inst_hier_path": "packetizer_0",
-        "reference_info": {
-          "ref_type": "hdl",
-          "ref_name": "packetizer",
-          "boundary_crc": "0x0"
-        },
-        "interface_ports": {
-          "m_axis": {
-            "mode": "Master",
-            "vlnv": "xilinx.com:interface:axis_rtl:1.0",
-            "parameters": {
-              "TDATA_NUM_BYTES": {
-                "value": "1",
-                "value_src": "constant"
-              },
-              "TDEST_WIDTH": {
-                "value": "0",
-                "value_src": "constant"
-              },
-              "TID_WIDTH": {
-                "value": "0",
-                "value_src": "constant"
-              },
-              "TUSER_WIDTH": {
-                "value": "0",
-                "value_src": "constant"
-              },
-              "HAS_TREADY": {
-                "value": "1",
-                "value_src": "constant"
-              },
-              "HAS_TSTRB": {
-                "value": "0",
-                "value_src": "constant"
-              },
-              "HAS_TKEEP": {
-                "value": "0",
-                "value_src": "constant"
-              },
-              "HAS_TLAST": {
-                "value": "1",
-                "value_src": "constant"
-              }
-            },
-            "port_maps": {
-              "TDATA": {
-                "physical_name": "m_axis_tdata",
-                "direction": "O",
-                "left": "7",
-                "right": "0"
-              },
-              "TLAST": {
-                "physical_name": "m_axis_tlast",
-                "direction": "O"
-              },
-              "TVALID": {
-                "physical_name": "m_axis_tvalid",
-                "direction": "O"
-              },
-              "TREADY": {
-                "physical_name": "m_axis_tready",
-                "direction": "I"
-              }
-            }
-          },
-          "s_axis": {
-            "mode": "Slave",
-            "vlnv": "xilinx.com:interface:axis_rtl:1.0",
-            "parameters": {
-              "TDATA_NUM_BYTES": {
-                "value": "1",
-                "value_src": "constant"
-              },
-              "TDEST_WIDTH": {
-                "value": "0",
-                "value_src": "constant"
-              },
-              "TID_WIDTH": {
-                "value": "0",
-                "value_src": "constant"
-              },
-              "TUSER_WIDTH": {
-                "value": "0",
-                "value_src": "constant"
-              },
-              "HAS_TREADY": {
-                "value": "1",
-                "value_src": "constant"
-              },
-              "HAS_TSTRB": {
-                "value": "0",
-                "value_src": "constant"
-              },
-              "HAS_TKEEP": {
-                "value": "0",
-                "value_src": "constant"
-              },
-              "HAS_TLAST": {
-                "value": "1",
-                "value_src": "constant"
-              }
-            },
-            "port_maps": {
-              "TDATA": {
-                "physical_name": "s_axis_tdata",
-                "direction": "I",
-                "left": "7",
-                "right": "0"
-              },
-              "TLAST": {
-                "physical_name": "s_axis_tlast",
-                "direction": "I"
-              },
-              "TVALID": {
-                "physical_name": "s_axis_tvalid",
-                "direction": "I"
-              },
-              "TREADY": {
-                "physical_name": "s_axis_tready",
-                "direction": "O"
-              }
-            }
-          }
-        },
-        "ports": {
-          "clk": {
-            "type": "clk",
-            "direction": "I",
-            "parameters": {
-              "ASSOCIATED_BUSIF": {
-                "value": "m_axis:s_axis",
-                "value_src": "constant"
-              },
-              "ASSOCIATED_RESET": {
-                "value": "aresetn",
-                "value_src": "constant"
-              }
-            }
-          },
-          "aresetn": {
-            "type": "rst",
-            "direction": "I",
-            "parameters": {
-              "POLARITY": {
-                "value": "ACTIVE_LOW",
-                "value_src": "constant"
-              }
-            }
-          }
-        }
-      }
-    },
-    "interface_nets": {
-      "AXI4Stream_UART_0_UART": {
-        "interface_ports": [
-          "usb_uart",
-          "AXI4Stream_UART_0/UART"
-        ]
-      },
-      "packetizer_0_m_axis": {
-        "interface_ports": [
-          "packetizer_0/m_axis",
-          "AXI4Stream_UART_0/S00_AXIS_TX"
-        ]
-      },
-      "depacketizer_0_m_axis": {
-        "interface_ports": [
-          "depacketizer_0/m_axis",
-          "packetizer_0/s_axis"
-        ]
-      },
-      "AXI4Stream_UART_0_M00_AXIS_RX": {
-        "interface_ports": [
-          "AXI4Stream_UART_0/M00_AXIS_RX",
-          "depacketizer_0/s_axis"
-        ]
-      }
-    },
-    "nets": {
-      "reset_1": {
-        "ports": [
-          "reset",
-          "proc_sys_reset_0/ext_reset_in",
-          "clk_wiz_0/reset"
-        ]
-      },
-      "sys_clock_1": {
-        "ports": [
-          "sys_clock",
-          "clk_wiz_0/clk_in1"
-        ]
-      },
-      "clk_wiz_0_clk_out1": {
-        "ports": [
-          "clk_wiz_0/clk_out1",
-          "AXI4Stream_UART_0/clk_uart",
-          "proc_sys_reset_0/slowest_sync_clk",
-          "AXI4Stream_UART_0/m00_axis_rx_aclk",
-          "AXI4Stream_UART_0/s00_axis_tx_aclk",
-          "depacketizer_0/clk",
-          "packetizer_0/clk"
-        ]
-      },
-      "proc_sys_reset_0_peripheral_reset": {
-        "ports": [
-          "proc_sys_reset_0/peripheral_reset",
-          "AXI4Stream_UART_0/rst"
-        ]
-      },
-      "clk_wiz_0_locked": {
-        "ports": [
-          "clk_wiz_0/locked",
-          "proc_sys_reset_0/dcm_locked"
-        ]
-      },
-      "proc_sys_reset_0_peripheral_aresetn": {
-        "ports": [
-          "proc_sys_reset_0/peripheral_aresetn",
-          "AXI4Stream_UART_0/m00_axis_rx_aresetn",
-          "AXI4Stream_UART_0/s00_axis_tx_aresetn",
-          "depacketizer_0/aresetn",
-          "packetizer_0/aresetn"
-        ]
-      }
-    }
-  }
-}

LAB2/src/pak_depak/pak_depak.bda

@@ -1,42 +0,0 @@
-<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
-<graphml xmlns="http://graphml.graphdrawing.org/xmlns" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:schemaLocation="http://graphml.graphdrawing.org/xmlns http://graphml.graphdrawing.org/xmlns/1.0/graphml.xsd">
-  <key attr.name="base_addr" attr.type="string" for="node" id="BA"/>
-  <key attr.name="base_param" attr.type="string" for="node" id="BP"/>
-  <key attr.name="edge_hid" attr.type="int" for="edge" id="EH"/>
-  <key attr.name="high_addr" attr.type="string" for="node" id="HA"/>
-  <key attr.name="high_param" attr.type="string" for="node" id="HP"/>
-  <key attr.name="master_addrspace" attr.type="string" for="node" id="MA"/>
-  <key attr.name="master_instance" attr.type="string" for="node" id="MX"/>
-  <key attr.name="master_interface" attr.type="string" for="node" id="MI"/>
-  <key attr.name="master_segment" attr.type="string" for="node" id="MS"/>
-  <key attr.name="master_vlnv" attr.type="string" for="node" id="MV"/>
-  <key attr.name="memory_type" attr.type="string" for="node" id="TM"/>
-  <key attr.name="slave_instance" attr.type="string" for="node" id="SX"/>
-  <key attr.name="slave_interface" attr.type="string" for="node" id="SI"/>
-  <key attr.name="slave_segment" attr.type="string" for="node" id="SS"/>
-  <key attr.name="slave_vlnv" attr.type="string" for="node" id="SV"/>
-  <key attr.name="usage_type" attr.type="string" for="node" id="TU"/>
-  <key attr.name="vert_hid" attr.type="int" for="node" id="VH"/>
-  <key attr.name="vert_name" attr.type="string" for="node" id="VM"/>
-  <key attr.name="vert_type" attr.type="string" for="node" id="VT"/>
-  <graph edgedefault="undirected" id="G" parse.edgeids="canonical" parse.nodeids="canonical" parse.order="nodesfirst">
-    <node id="n0">
-      <data key="TU">active</data>
-      <data key="VH">2</data>
-      <data key="VT">PM</data>
-    </node>
-    <node id="n1">
-      <data key="VM">pak_depak</data>
-      <data key="VT">BC</data>
-    </node>
-    <node id="n2">
-      <data key="VH">2</data>
-      <data key="VM">pak_depak</data>
-      <data key="VT">VR</data>
-    </node>
-    <edge id="e0" source="n1" target="n2">
-    </edge>
-    <edge id="e1" source="n2" target="n0">
-    </edge>
-  </graph>
-</graphml>

LAB2/src/pak_depak/ui/bd_c9b29a54.ui

@@ -1,33 +0,0 @@
-{
-   "ActiveEmotionalView":"Default View",
-   "Default View_ScaleFactor":"1.00128",
-   "Default View_TopLeft":"-106,-179",
-   "ExpandedHierarchyInLayout":"",
-   "guistr":"# # String gsaved with Nlview 7.0r6  2020-01-29 bk=1.5227 VDI=41 GEI=36 GUI=JA:10.0 non-TLS
-#  -string -flagsOSRD
-preplace port usb_uart -pg 1 -lvl 6 -x 1360 -y 180 -defaultsOSRD
-preplace port reset -pg 1 -lvl 0 -x 0 -y 190 -defaultsOSRD
-preplace port sys_clock -pg 1 -lvl 0 -x 0 -y 270 -defaultsOSRD
-preplace inst proc_sys_reset_0 -pg 1 -lvl 2 -x 380 -y 210 -defaultsOSRD
-preplace inst clk_wiz_0 -pg 1 -lvl 1 -x 110 -y 260 -defaultsOSRD
-preplace inst AXI4Stream_UART_0 -pg 1 -lvl 5 -x 1190 -y 170 -defaultsOSRD
-preplace inst depacketizer_0 -pg 1 -lvl 3 -x 670 -y 90 -defaultsOSRD
-preplace inst packetizer_0 -pg 1 -lvl 4 -x 910 -y 110 -defaultsOSRD
-preplace netloc reset_1 1 0 2 20 190 NJ
-preplace netloc sys_clock_1 1 0 1 NJ 270
-preplace netloc clk_wiz_0_clk_out1 1 1 4 200 310 550 170 780 20 1030
-preplace netloc proc_sys_reset_0_peripheral_reset 1 2 3 NJ 210 790J 30 1020
-preplace netloc clk_wiz_0_locked 1 1 1 210 250n
-preplace netloc proc_sys_reset_0_peripheral_aresetn 1 2 3 560 180 800 190 1040
-preplace netloc AXI4Stream_UART_0_UART 1 5 1 N 180
-preplace netloc depacketizer_0_m_axis 1 3 1 N 90
-preplace netloc packetizer_0_m_axis 1 4 1 N 110
-preplace netloc AXI4Stream_UART_0_M00_AXIS_RX 1 2 4 550 10 NJ 10 NJ 10 1340
-levelinfo -pg 1 0 110 380 670 910 1190 1360
-pagesize -pg 1 -db -bbox -sgen -110 0 1470 330
-"
-}
-{
-   "da_board_cnt":"1",
-   "da_clkrst_cnt":"3"
-}

LAB2/src/rgb2gray.vhd

@@ -1,13 +1,6 @@
----------- DEFAULT LIBRARIES -------
 LIBRARY IEEE;
 USE IEEE.STD_LOGIC_1164.ALL;
 USE IEEE.NUMERIC_STD.ALL;
-USE IEEE.MATH_REAL.ALL; -- For logarithmic calculations (used for a constant)
-------------------------------------
-
----------- OTHER LIBRARIES ---------
--- NONE
-------------------------------------
 
 ENTITY rgb2gray IS
 	PORT (
@@ -34,19 +27,30 @@ ARCHITECTURE Behavioral OF rgb2gray IS
 		);
 		PORT (
 			dividend : IN UNSIGNED(BIT_DEPTH + 1 DOWNTO 0);
-			result : OUT UNSIGNED(BIT_DEPTH - 1 DOWNTO 0));
-	END COMPONENT divider_by_3;
+			result : OUT UNSIGNED(BIT_DEPTH - 1 DOWNTO 0)
+		);
+	END COMPONENT;
 
 	TYPE state_type IS (WAIT_R, WAIT_G, WAIT_B);
 	SIGNAL state : state_type := WAIT_R;
 
-	SIGNAL r_val, g_val : unsigned(7 DOWNTO 0);
-	SIGNAL sum : unsigned(8 DOWNTO 0);
+	SIGNAL r_val, g_val : UNSIGNED(7 DOWNTO 0);
+	SIGNAL sum : UNSIGNED(8 DOWNTO 0);
 	SIGNAL gray : UNSIGNED(6 DOWNTO 0);
 	SIGNAL send_data : STD_LOGIC := '0';
 
+	SIGNAL m_axis_tvalid_int : STD_LOGIC := '0';
+	SIGNAL m_axis_tdata_int : STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');
+	SIGNAL s_axis_tready_int : STD_LOGIC := '1';
+
 BEGIN
 
+	-- Port mappings
+	m_axis_tvalid <= m_axis_tvalid_int;
+	m_axis_tdata <= m_axis_tdata_int;
+	s_axis_tready <= s_axis_tready_int;
+
+	-- Divider instance
 	DIVIDER : divider_by_3
 	GENERIC MAP(
 		BIT_DEPTH => 7
@@ -62,55 +66,58 @@ BEGIN
 			IF resetn = '0' THEN
 				-- Reset all signals
 				state <= WAIT_R;
-				s_axis_tready <= '1';
-				m_axis_tvalid <= '0';
+				s_axis_tready_int <= '1';
+				m_axis_tvalid_int <= '0';
 				m_axis_tlast <= '0';
-				m_axis_tdata <= (OTHERS => '0');
+				m_axis_tdata_int <= (OTHERS => '0');
 				r_val <= (OTHERS => '0');
 				g_val <= (OTHERS => '0');
 				sum <= (OTHERS => '0');
-			ELSE
-				-- Default control signals
-				m_axis_tlast <= s_axis_tlast;
-				m_axis_tvalid <= '0';
+				send_data <= '0';
 
-				-- If downstream is ready, send the grayscale pixel
-				IF m_axis_tready = '1' AND send_data = '1' THEN
-					m_axis_tdata <= STD_LOGIC_VECTOR('0' & gray);
-					m_axis_tvalid <= '1';
+			ELSE
+				-- Propagate TLAST
+				m_axis_tlast <= s_axis_tlast;
+
+				-- Clear valid once data has been accepted
+				IF m_axis_tvalid_int = '1' AND m_axis_tready = '1' THEN
+					m_axis_tvalid_int <= '0';
+				END IF;
+
+				-- Issue new output only when back?pressure is released
+				IF send_data = '1' AND m_axis_tready = '1' THEN
+					m_axis_tdata_int <= '0' & STD_LOGIC_VECTOR(gray); -- MSB zero + 7?bit gray
+					m_axis_tvalid_int <= '1';
 					send_data <= '0';
 				END IF;
 
+				-- Back?pressure: blocca ingresso finch<63> non hai trasmesso
+				IF send_data = '1' OR (m_axis_tvalid_int = '1' AND m_axis_tready = '0') THEN
+					s_axis_tready_int <= '0';
+				ELSE
+					s_axis_tready_int <= '1';
+				END IF;
+
+				-- FSM per ricezione R, G, B
 				CASE state IS
 					WHEN WAIT_R =>
-						IF s_axis_tvalid = '1' THEN
+						IF s_axis_tvalid = '1' AND s_axis_tready_int = '1' THEN
 							r_val <= unsigned(s_axis_tdata);
-
-							IF m_axis_tready = '0' THEN
-								s_axis_tready <= '0';
-							END IF;
-
 							state <= WAIT_G;
 						END IF;
 
 					WHEN WAIT_G =>
-						IF s_axis_tvalid = '1' THEN
+						IF s_axis_tvalid = '1' AND s_axis_tready_int = '1' THEN
 							g_val <= unsigned(s_axis_tdata);
-
-							IF m_axis_tready = '1' THEN
-								s_axis_tready <= '1';
-								state <= WAIT_B;
-							END IF;
+							state <= WAIT_B;
 						END IF;
 
 					WHEN WAIT_B =>
-						IF s_axis_tvalid = '1' THEN
+						IF s_axis_tvalid = '1' AND s_axis_tready_int = '1' THEN
 							sum <= RESIZE(r_val + g_val + unsigned(s_axis_tdata), 9);
 							send_data <= '1';
-
 							state <= WAIT_R;
 						END IF;
-
 				END CASE;
 			END IF;
 		END IF;

LAB2/vivado/depacketizer_test/depacketizer_test.xpr

@@ -0,0 +1,211 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<!-- Product Version: Vivado v2020.2 (64-bit)              -->
+<!--                                                         -->
+<!-- Copyright 1986-2020 Xilinx, Inc. All Rights Reserved.   -->
+
+<Project Version="7" Minor="54" Path="C:/DESD/LAB2/vivado/depacketizer_test/depacketizer_test.xpr">
+  <DefaultLaunch Dir="$PRUNDIR"/>
+  <Configuration>
+    <Option Name="Id" Val="7b9c995611dd4a3a8cd1a23f331045b5"/>
+    <Option Name="Part" Val="xc7a35tcpg236-1"/>
+    <Option Name="CompiledLibDir" Val="$PCACHEDIR/compile_simlib"/>
+    <Option Name="CompiledLibDirXSim" Val=""/>
+    <Option Name="CompiledLibDirModelSim" Val="$PCACHEDIR/compile_simlib/modelsim"/>
+    <Option Name="CompiledLibDirQuesta" Val="$PCACHEDIR/compile_simlib/questa"/>
+    <Option Name="CompiledLibDirIES" Val="$PCACHEDIR/compile_simlib/ies"/>
+    <Option Name="CompiledLibDirXcelium" Val="$PCACHEDIR/compile_simlib/xcelium"/>
+    <Option Name="CompiledLibDirVCS" Val="$PCACHEDIR/compile_simlib/vcs"/>
+    <Option Name="CompiledLibDirRiviera" Val="$PCACHEDIR/compile_simlib/riviera"/>
+    <Option Name="CompiledLibDirActivehdl" Val="$PCACHEDIR/compile_simlib/activehdl"/>
+    <Option Name="SimulatorInstallDirModelSim" Val=""/>
+    <Option Name="SimulatorInstallDirQuesta" Val=""/>
+    <Option Name="SimulatorInstallDirIES" Val=""/>
+    <Option Name="SimulatorInstallDirXcelium" Val=""/>
+    <Option Name="SimulatorInstallDirVCS" Val=""/>
+    <Option Name="SimulatorInstallDirRiviera" Val=""/>
+    <Option Name="SimulatorInstallDirActiveHdl" Val=""/>
+    <Option Name="SimulatorGccInstallDirModelSim" Val=""/>
+    <Option Name="SimulatorGccInstallDirQuesta" Val=""/>
+    <Option Name="SimulatorGccInstallDirIES" Val=""/>
+    <Option Name="SimulatorGccInstallDirXcelium" Val=""/>
+    <Option Name="SimulatorGccInstallDirVCS" Val=""/>
+    <Option Name="SimulatorGccInstallDirRiviera" Val=""/>
+    <Option Name="SimulatorGccInstallDirActiveHdl" Val=""/>
+    <Option Name="TargetLanguage" Val="VHDL"/>
+    <Option Name="BoardPart" Val="digilentinc.com:basys3:part0:1.1"/>
+    <Option Name="BoardPartRepoPaths" Val="$PPRDIR/../../../../Users/david/AppData/Roaming/Xilinx/Vivado/2020.2/xhub/board_store/xilinx_board_store"/>
+    <Option Name="ActiveSimSet" Val="sim_1"/>
+    <Option Name="DefaultLib" Val="xil_defaultlib"/>
+    <Option Name="ProjectType" Val="Default"/>
+    <Option Name="IPOutputRepo" Val="$PCACHEDIR/ip"/>
+    <Option Name="IPDefaultOutputPath" Val="$PGENDIR/sources_1"/>
+    <Option Name="IPCachePermission" Val="read"/>
+    <Option Name="IPCachePermission" Val="write"/>
+    <Option Name="EnableCoreContainer" Val="FALSE"/>
+    <Option Name="CreateRefXciForCoreContainers" Val="FALSE"/>
+    <Option Name="IPUserFilesDir" Val="$PIPUSERFILESDIR"/>
+    <Option Name="IPStaticSourceDir" Val="$PIPUSERFILESDIR/ipstatic"/>
+    <Option Name="EnableBDX" Val="FALSE"/>
+    <Option Name="DSABoardId" Val="basys3"/>
+    <Option Name="WTXSimLaunchSim" Val="29"/>
+    <Option Name="WTModelSimLaunchSim" Val="0"/>
+    <Option Name="WTQuestaLaunchSim" Val="0"/>
+    <Option Name="WTIesLaunchSim" Val="0"/>
+    <Option Name="WTVcsLaunchSim" Val="0"/>
+    <Option Name="WTRivieraLaunchSim" Val="0"/>
+    <Option Name="WTActivehdlLaunchSim" Val="0"/>
+    <Option Name="WTXSimExportSim" Val="0"/>
+    <Option Name="WTModelSimExportSim" Val="0"/>
+    <Option Name="WTQuestaExportSim" Val="0"/>
+    <Option Name="WTIesExportSim" Val="0"/>
+    <Option Name="WTVcsExportSim" Val="0"/>
+    <Option Name="WTRivieraExportSim" Val="0"/>
+    <Option Name="WTActivehdlExportSim" Val="0"/>
+    <Option Name="GenerateIPUpgradeLog" Val="TRUE"/>
+    <Option Name="XSimRadix" Val="hex"/>
+    <Option Name="XSimTimeUnit" Val="ns"/>
+    <Option Name="XSimArrayDisplayLimit" Val="1024"/>
+    <Option Name="XSimTraceLimit" Val="65536"/>
+    <Option Name="SimTypes" Val="rtl"/>
+    <Option Name="SimTypes" Val="bfm"/>
+    <Option Name="SimTypes" Val="tlm"/>
+    <Option Name="SimTypes" Val="tlm_dpi"/>
+    <Option Name="MEMEnableMemoryMapGeneration" Val="TRUE"/>
+    <Option Name="DcpsUptoDate" Val="TRUE"/>
+  </Configuration>
+  <FileSets Version="1" Minor="31">
+    <FileSet Name="sources_1" Type="DesignSrcs" RelSrcDir="$PSRCDIR/sources_1" RelGenDir="$PGENDIR/sources_1">
+      <Filter Type="Srcs"/>
+      <File Path="$PPRDIR/../../src/depacketizer.vhd">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <Config>
+        <Option Name="DesignMode" Val="RTL"/>
+        <Option Name="TopModule" Val="depacketizer"/>
+        <Option Name="TopAutoSet" Val="TRUE"/>
+      </Config>
+    </FileSet>
+    <FileSet Name="constrs_1" Type="Constrs" RelSrcDir="$PSRCDIR/constrs_1" RelGenDir="$PGENDIR/constrs_1">
+      <Filter Type="Constrs"/>
+      <Config>
+        <Option Name="ConstrsType" Val="XDC"/>
+      </Config>
+    </FileSet>
+    <FileSet Name="sim_1" Type="SimulationSrcs" RelSrcDir="$PSRCDIR/sim_1" RelGenDir="$PGENDIR/sim_1">
+      <Filter Type="Srcs"/>
+      <File Path="$PPRDIR/../../sim/tb_depacketizer.vhd">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PPRDIR/tb_depacketizer_behav.wcfg">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <Config>
+        <Option Name="DesignMode" Val="RTL"/>
+        <Option Name="TopModule" Val="tb_depacketizer"/>
+        <Option Name="TopLib" Val="xil_defaultlib"/>
+        <Option Name="TopAutoSet" Val="TRUE"/>
+        <Option Name="TransportPathDelay" Val="0"/>
+        <Option Name="TransportIntDelay" Val="0"/>
+        <Option Name="SelectedSimModel" Val="rtl"/>
+        <Option Name="PamDesignTestbench" Val=""/>
+        <Option Name="PamDutBypassFile" Val="xil_dut_bypass"/>
+        <Option Name="PamSignalDriverFile" Val="xil_bypass_driver"/>
+        <Option Name="PamPseudoTop" Val="pseudo_tb"/>
+        <Option Name="SrcSet" Val="sources_1"/>
+        <Option Name="XSimWcfgFile" Val="$PPRDIR/tb_depacketizer_behav.wcfg"/>
+      </Config>
+    </FileSet>
+    <FileSet Name="utils_1" Type="Utils" RelSrcDir="$PSRCDIR/utils_1" RelGenDir="$PGENDIR/utils_1">
+      <Filter Type="Utils"/>
+      <Config>
+        <Option Name="TopAutoSet" Val="TRUE"/>
+      </Config>
+    </FileSet>
+  </FileSets>
+  <Simulators>
+    <Simulator Name="XSim">
+      <Option Name="Description" Val="Vivado Simulator"/>
+      <Option Name="CompiledLib" Val="0"/>
+    </Simulator>
+    <Simulator Name="ModelSim">
+      <Option Name="Description" Val="ModelSim Simulator"/>
+    </Simulator>
+    <Simulator Name="Questa">
+      <Option Name="Description" Val="Questa Advanced Simulator"/>
+    </Simulator>
+    <Simulator Name="Riviera">
+      <Option Name="Description" Val="Riviera-PRO Simulator"/>
+    </Simulator>
+    <Simulator Name="ActiveHDL">
+      <Option Name="Description" Val="Active-HDL Simulator"/>
+    </Simulator>
+  </Simulators>
+  <Runs Version="1" Minor="15">
+    <Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7a35tcpg236-1" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" IncludeInArchive="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/synth_1">
+      <Strategy Version="1" Minor="2">
+        <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2020"/>
+        <Step Id="synth_design"/>
+      </Strategy>
+      <ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2020"/>
+      <Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
+      <RQSFiles/>
+    </Run>
+    <Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7a35tcpg236-1" ConstrsSet="constrs_1" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" SynthRun="synth_1" IncludeInArchive="true" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/impl_1">
+      <Strategy Version="1" Minor="2">
+        <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2020"/>
+        <Step Id="init_design"/>
+        <Step Id="opt_design"/>
+        <Step Id="power_opt_design"/>
+        <Step Id="place_design"/>
+        <Step Id="post_place_power_opt_design"/>
+        <Step Id="phys_opt_design"/>
+        <Step Id="route_design"/>
+        <Step Id="post_route_phys_opt_design"/>
+        <Step Id="write_bitstream"/>
+      </Strategy>
+      <ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2020"/>
+      <Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
+      <RQSFiles/>
+    </Run>
+  </Runs>
+  <Board>
+    <Jumpers/>
+  </Board>
+  <DashboardSummary Version="1" Minor="0">
+    <Dashboards>
+      <Dashboard Name="default_dashboard">
+        <Gadgets>
+          <Gadget Name="drc_1" Type="drc" Version="1" Row="2" Column="0">
+            <GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_drc_0 "/>
+          </Gadget>
+          <Gadget Name="methodology_1" Type="methodology" Version="1" Row="2" Column="1">
+            <GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_methodology_0 "/>
+          </Gadget>
+          <Gadget Name="power_1" Type="power" Version="1" Row="1" Column="0">
+            <GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_power_0 "/>
+          </Gadget>
+          <Gadget Name="timing_1" Type="timing" Version="1" Row="0" Column="1">
+            <GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_timing_summary_0 "/>
+          </Gadget>
+          <Gadget Name="utilization_1" Type="utilization" Version="1" Row="0" Column="0">
+            <GadgetParam Name="REPORTS" Type="string_list" Value="synth_1#synth_1_synth_report_utilization_0 "/>
+            <GadgetParam Name="RUN.STEP" Type="string" Value="synth_design"/>
+            <GadgetParam Name="RUN.TYPE" Type="string" Value="synthesis"/>
+          </Gadget>
+          <Gadget Name="utilization_2" Type="utilization" Version="1" Row="1" Column="1">
+            <GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_place_report_utilization_0 "/>
+          </Gadget>
+        </Gadgets>
+      </Dashboard>
+      <CurrentDashboard>default_dashboard</CurrentDashboard>
+    </Dashboards>
+  </DashboardSummary>
+</Project>

LAB2/vivado/depacketizer_test/tb_depacketizer_behav.wcfg

@@ -0,0 +1,86 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<wave_config>
+   <wave_state>
+   </wave_state>
+   <db_ref_list>
+      <db_ref path="tb_depacketizer_behav.wdb" id="1">
+         <top_modules>
+            <top_module name="tb_depacketizer" />
+         </top_modules>
+      </db_ref>
+   </db_ref_list>
+   <zoom_setting>
+      <ZoomStartTime time="0fs"></ZoomStartTime>
+      <ZoomEndTime time="1000001fs"></ZoomEndTime>
+      <Cursor1Time time="150033fs"></Cursor1Time>
+   </zoom_setting>
+   <column_width_setting>
+      <NameColumnWidth column_width="248"></NameColumnWidth>
+      <ValueColumnWidth column_width="115"></ValueColumnWidth>
+   </column_width_setting>
+   <WVObjectSize size="14" />
+   <wvobject fp_name="/tb_depacketizer/mem" type="array">
+      <obj_property name="ElementShortName">mem[0:7][7:0]</obj_property>
+      <obj_property name="ObjectShortName">mem[0:7][7:0]</obj_property>
+   </wvobject>
+   <wvobject fp_name="/tb_depacketizer/clk" type="logic">
+      <obj_property name="ElementShortName">clk</obj_property>
+      <obj_property name="ObjectShortName">clk</obj_property>
+   </wvobject>
+   <wvobject fp_name="/tb_depacketizer/aresetn" type="logic">
+      <obj_property name="ElementShortName">aresetn</obj_property>
+      <obj_property name="ObjectShortName">aresetn</obj_property>
+   </wvobject>
+   <wvobject fp_name="/tb_depacketizer/uut/state" type="other">
+      <obj_property name="ElementShortName">state</obj_property>
+      <obj_property name="ObjectShortName">state</obj_property>
+      <obj_property name="CustomSignalColor">#00FFFF</obj_property>
+      <obj_property name="UseCustomSignalColor">true</obj_property>
+   </wvobject>
+   <wvobject fp_name="/tb_depacketizer/uut/data_buffer" type="array">
+      <obj_property name="ElementShortName">data_buffer[7:0]</obj_property>
+      <obj_property name="ObjectShortName">data_buffer[7:0]</obj_property>
+   </wvobject>
+   <wvobject type="divider" fp_name="divider19">
+      <obj_property name="label">s_axis</obj_property>
+      <obj_property name="DisplayName">label</obj_property>
+   </wvobject>
+   <wvobject fp_name="/tb_depacketizer/s_axis_tdata" type="array">
+      <obj_property name="ElementShortName">s_axis_tdata[7:0]</obj_property>
+      <obj_property name="ObjectShortName">s_axis_tdata[7:0]</obj_property>
+   </wvobject>
+   <wvobject fp_name="/tb_depacketizer/s_axis_tvalid" type="logic">
+      <obj_property name="ElementShortName">s_axis_tvalid</obj_property>
+      <obj_property name="ObjectShortName">s_axis_tvalid</obj_property>
+   </wvobject>
+   <wvobject fp_name="/tb_depacketizer/s_axis_tready" type="logic">
+      <obj_property name="ElementShortName">s_axis_tready</obj_property>
+      <obj_property name="ObjectShortName">s_axis_tready</obj_property>
+      <obj_property name="CustomSignalColor">#FFD700</obj_property>
+      <obj_property name="UseCustomSignalColor">true</obj_property>
+   </wvobject>
+   <wvobject type="divider" fp_name="divider20">
+      <obj_property name="label">m_axis</obj_property>
+      <obj_property name="DisplayName">label</obj_property>
+   </wvobject>
+   <wvobject fp_name="/tb_depacketizer/m_axis_tdata" type="array">
+      <obj_property name="ElementShortName">m_axis_tdata[7:0]</obj_property>
+      <obj_property name="ObjectShortName">m_axis_tdata[7:0]</obj_property>
+   </wvobject>
+   <wvobject fp_name="/tb_depacketizer/m_axis_tvalid" type="logic">
+      <obj_property name="ElementShortName">m_axis_tvalid</obj_property>
+      <obj_property name="ObjectShortName">m_axis_tvalid</obj_property>
+   </wvobject>
+   <wvobject fp_name="/tb_depacketizer/m_axis_tready" type="logic">
+      <obj_property name="ElementShortName">m_axis_tready</obj_property>
+      <obj_property name="ObjectShortName">m_axis_tready</obj_property>
+      <obj_property name="CustomSignalColor">#FFD700</obj_property>
+      <obj_property name="UseCustomSignalColor">true</obj_property>
+   </wvobject>
+   <wvobject fp_name="/tb_depacketizer/m_axis_tlast" type="logic">
+      <obj_property name="ElementShortName">m_axis_tlast</obj_property>
+      <obj_property name="ObjectShortName">m_axis_tlast</obj_property>
+      <obj_property name="CustomSignalColor">#0000FF</obj_property>
+      <obj_property name="UseCustomSignalColor">true</obj_property>
+   </wvobject>
+</wave_config>

LAB2/vivado/pak_depak/pak_depak.xpr

@@ -77,12 +77,6 @@
   <FileSets Version="1" Minor="31">
     <FileSet Name="sources_1" Type="DesignSrcs" RelSrcDir="$PSRCDIR/sources_1" RelGenDir="$PGENDIR/sources_1">
       <Filter Type="Srcs"/>
-      <File Path="$PPRDIR/../../src/fifo.vhd">
-        <FileInfo>
-          <Attr Name="UsedIn" Val="synthesis"/>
-          <Attr Name="UsedIn" Val="simulation"/>
-        </FileInfo>
-      </File>
       <File Path="$PPRDIR/../../src/depacketizer.vhd">
         <FileInfo>
           <Attr Name="UsedIn" Val="synthesis"/>
@@ -108,6 +102,13 @@
           <Attr Name="UsedIn" Val="simulation"/>
         </FileInfo>
       </File>
+      <File Path="$PPRDIR/../../src/fifo.vhd">
+        <FileInfo>
+          <Attr Name="AutoDisabled" Val="1"/>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
       <Config>
         <Option Name="DesignMode" Val="RTL"/>
         <Option Name="TopModule" Val="pak_depak_wrapper"/>
@@ -120,12 +121,11 @@
       </Config>
     </FileSet>
     <FileSet Name="sim_1" Type="SimulationSrcs" RelSrcDir="$PSRCDIR/sim_1" RelGenDir="$PGENDIR/sim_1">
+      <Filter Type="Srcs"/>
       <Config>
         <Option Name="DesignMode" Val="RTL"/>
-        <Option Name="TopModule" Val="depacketizer"/>
+        <Option Name="TopModule" Val="pak_depak_wrapper"/>
         <Option Name="TopLib" Val="xil_defaultlib"/>
-        <Option Name="TopArchitecture" Val="rtl"/>
-        <Option Name="TopRTLFile" Val="$PPRDIR/../../src/depacketizer.vhd"/>
         <Option Name="TopAutoSet" Val="TRUE"/>
         <Option Name="TransportPathDelay" Val="0"/>
         <Option Name="TransportIntDelay" Val="0"/>
@@ -165,9 +165,7 @@
   <Runs Version="1" Minor="15">
     <Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7a35tcpg236-1" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" Dir="$PRUNDIR/synth_1" IncludeInArchive="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/synth_1">
       <Strategy Version="1" Minor="2">
-        <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2020">
-          <Desc>Vivado Synthesis Defaults</Desc>
-        </StratHandle>
+        <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2020"/>
         <Step Id="synth_design"/>
       </Strategy>
       <GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
@@ -177,9 +175,7 @@
     </Run>
     <Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7a35tcpg236-1" ConstrsSet="constrs_1" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" Dir="$PRUNDIR/impl_1" SynthRun="synth_1" IncludeInArchive="true" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/impl_1">
       <Strategy Version="1" Minor="2">
-        <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2020">
-          <Desc>Default settings for Implementation.</Desc>
-        </StratHandle>
+        <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2020"/>
         <Step Id="init_design"/>
         <Step Id="opt_design"/>
         <Step Id="power_opt_design"/>

LAB2/vivado/rgb2grey_test/rgb2grey_test.xpr

@@ -47,7 +47,7 @@
     <Option Name="IPStaticSourceDir" Val="$PIPUSERFILESDIR/ipstatic"/>
     <Option Name="EnableBDX" Val="FALSE"/>
     <Option Name="DSABoardId" Val="basys3"/>
-    <Option Name="WTXSimLaunchSim" Val="84"/>
+    <Option Name="WTXSimLaunchSim" Val="93"/>
     <Option Name="WTModelSimLaunchSim" Val="0"/>
     <Option Name="WTQuestaLaunchSim" Val="0"/>
     <Option Name="WTIesLaunchSim" Val="0"/>