5 Commits

Author	SHA1	Message	Date
Cd16d	1b6bae5183	Refactor volume_saturator VHDL code for improved readability and structure; update project files for consistent path references and disable unused components in lab3 design.	2025-05-19 16:24:36 +02:00
Davide	6ab3f7bcde	Refactor LFO and design files: update LFO entity parameters, adjust signal handling, and modify project file paths for improved functionality and organization.	2025-05-18 20:35:05 +02:00
Cd16d	a4ec7ce43a	Add lab_3_wrapper VHDL file and update project files for LAB3	2025-05-12 14:58:06 +02:00
Cd16d	c99622188d	Update design files for LAB3: reorganize components and adjust simulation settings	2025-05-12 14:38:11 +02:00
Cd16d	60a8aa912d	Add initial design files and project configuration for LAB3 ... - Created a new Block Design Archive (lab_3.bda) for LAB3, defining nodes and edges for the design. - Added a placeholder README file in the simulation directory. - Initialized a Vivado project file (lab3.xpr) with configuration settings and source files for synthesis and simulation. - Updated vhdl_ls.toml to include LAB3 source and simulation files for VHDL language server support.	2025-05-12 14:20:41 +02:00