3 Commits

Author	SHA1	Message	Date
Davide	360ae72198	Reorder reset, sys_clock and USB UART ports in lab_2_wrapper and update synthesis flow mode in lab_2.bd	2025-04-09 11:40:21 +02:00
Davide	a5264642a6	Add new VHDL entities for image processing and update test scripts for Lab2	2025-03-29 00:50:32 +01:00
Davide	163ad448f8	Update .gitignore and enhance README.md; add new VHDL files for KittCarPWM, ShiftRegisters, and PulseWidthModulator	2025-03-20 15:05:27 +01:00