3 Commits

Include renames

Author	SHA1	Message	Date
PickleRick	360ae72198	Reorder reset, sys_clock and USB UART ports in lab_2_wrapper and update synthesis flow mode in lab_2.bd	2025-04-09 11:40:21 +02:00
PickleRick	cd5d1b8a0c	Add new AXI4-Stream UART IP and update .gitignore for Lab2 files	2025-03-31 18:35:29 +02:00
PickleRick	a5264642a6	Add new VHDL entities for image processing and update test scripts for Lab2	2025-03-29 00:50:32 +01:00