- Created new design file `pak_depak.bd` with components including `proc_sys_reset`, `clk_wiz`, `AXI4Stream_UART`, `depacketizer`, and `packetizer`.
- Added associated architecture file `pak_depak.bda` for design representation.
- Introduced UI configuration file `bd_c9b29a54.ui` for graphical representation of the design.
- Updated project file `lab2.xpr` to replace references to old source files with new ones.
- Added new project file `pak_depak.xpr` for the pak_depak design with necessary configurations and file sets.
- Updated the rgb2gray.vhd file to improve readability and structure, including consistent casing for keywords and signals.
- Implemented a new divider_by_3 component to calculate the grayscale value by dividing the sum of RGB channels by 3.
- Enhanced the state machine in rgb2gray to handle RGB input and output grayscale values correctly.
- Updated the Vivado project file to include the new divider_by_3.vhd for synthesis and simulation.
- Modified vhdl_ls.toml to include unisim files for third-party library support.
