- Updated node connections in lab_2.bda and pak_depak.bda to correct source and target references.
- Modified pak_depak_wrapper.vhd to reflect the correct timestamp.
- Rearranged the order of components in pak_depak.bd for clarity and consistency.
- Adjusted BRAM writer logic in bram_writer.vhd for improved data handling and comments for clarity.
- Enhanced depacketizer.vhd with additional comments and logic adjustments for better data reception.
- Refined divider_by_3.vhd to optimize division calculations and improve clarity in comments.
- Improved img_conv.vhd with better state management and comments for the convolution process.
- Updated led_blinker.vhd to enhance readability and maintainability with clearer comments.
- Enhanced packetizer.vhd to improve data handling and added comments for better understanding.
- Adjusted rgb2gray.vhd to include standard library comments for consistency.
- Updated test.py to improve image processing logic and added visualization for differences.
- Added new binary files for test_nopath.exe and archived project files for lab2 and pak_depak.
- Updated Vivado project files to ensure correct paths and settings for synthesis and implementation.
- Created new design file `pak_depak.bd` with components including `proc_sys_reset`, `clk_wiz`, `AXI4Stream_UART`, `depacketizer`, and `packetizer`.
- Added associated architecture file `pak_depak.bda` for design representation.
- Introduced UI configuration file `bd_c9b29a54.ui` for graphical representation of the design.
- Updated project file `lab2.xpr` to replace references to old source files with new ones.
- Added new project file `pak_depak.xpr` for the pak_depak design with necessary configurations and file sets.
- Updated the rgb2gray.vhd file to improve readability and structure, including consistent casing for keywords and signals.
- Implemented a new divider_by_3 component to calculate the grayscale value by dividing the sum of RGB channels by 3.
- Enhanced the state machine in rgb2gray to handle RGB input and output grayscale values correctly.
- Updated the Vivado project file to include the new divider_by_3.vhd for synthesis and simulation.
- Modified vhdl_ls.toml to include unisim files for third-party library support.
