5 Commits

Author	SHA1	Message	Date
Cd16d	55c5c84247	Refactor lab_3.bda to update node IDs and edge connections; modify digilent_jstk2.vhd to increase packet delay and adjust state machine; enhance uart_viewer.py for real-time coordinate visualization using matplotlib; update diligent_jstk.xpr simulation settings and remove unused file sets; add new Vivado project zip files for diligent_jstk and lab3.	2025-05-16 16:43:45 +02:00
Cd16d	b11c65043f	Add AXI4-Stream UART IP and associated files ... - Created board.xit for physical constraints related to UART interface. - Added vv_index.xml to define the AXI4-Stream UART IP with relevant metadata. - Implemented GUI for AXI4-Stream UART parameters in AXI4Stream_UART_v1_0.tcl and AXI4Stream_UART_v1_1.tcl. - Initialized Vivado project files for diligent_jstk and loopback_I2S designs, including synthesis and implementation settings. - Configured file sets and simulation options for both projects.	2025-05-12 18:16:58 +02:00
Cd16d	a4ec7ce43a	Add lab_3_wrapper VHDL file and update project files for LAB3	2025-05-12 14:58:06 +02:00
Cd16d	c99622188d	Update design files for LAB3: reorganize components and adjust simulation settings	2025-05-12 14:38:11 +02:00
Cd16d	60a8aa912d	Add initial design files and project configuration for LAB3 ... - Created a new Block Design Archive (lab_3.bda) for LAB3, defining nodes and edges for the design. - Added a placeholder README file in the simulation directory. - Initialized a Vivado project file (lab3.xpr) with configuration settings and source files for synthesis and simulation. - Updated vhdl_ls.toml to include LAB3 source and simulation files for VHDL language server support.	2025-05-12 14:20:41 +02:00