- Created a new Block Design Archive (lab_3.bda) for LAB3, defining nodes and edges for the design.
- Added a placeholder README file in the simulation directory.
- Initialized a Vivado project file (lab3.xpr) with configuration settings and source files for synthesis and simulation.
- Updated vhdl_ls.toml to include LAB3 source and simulation files for VHDL language server support.
- Updated the rgb2gray.vhd file to improve readability and structure, including consistent casing for keywords and signals.
- Implemented a new divider_by_3 component to calculate the grayscale value by dividing the sum of RGB channels by 3.
- Enhanced the state machine in rgb2gray to handle RGB input and output grayscale values correctly.
- Updated the Vivado project file to include the new divider_by_3.vhd for synthesis and simulation.
- Modified vhdl_ls.toml to include unisim files for third-party library support.
