118 lines
3.0 KiB
VHDL
118 lines
3.0 KiB
VHDL
LIBRARY IEEE;
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USE IEEE.STD_LOGIC_1164.ALL;
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USE ieee.numeric_std.ALL;
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ENTITY balance_controller IS
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GENERIC (
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TDATA_WIDTH : POSITIVE := 24;
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BALANCE_WIDTH : POSITIVE := 10;
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BALANCE_STEP_2 : POSITIVE := 6 -- i.e., balance_values_per_step = 2**BALANCE_STEP_2
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);
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PORT (
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aclk : IN STD_LOGIC;
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aresetn : IN STD_LOGIC;
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s_axis_tvalid : IN STD_LOGIC;
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s_axis_tdata : IN STD_LOGIC_VECTOR(TDATA_WIDTH - 1 DOWNTO 0);
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s_axis_tready : OUT STD_LOGIC;
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s_axis_tlast : IN STD_LOGIC;
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m_axis_tvalid : OUT STD_LOGIC;
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m_axis_tdata : OUT STD_LOGIC_VECTOR(TDATA_WIDTH - 1 DOWNTO 0);
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m_axis_tready : IN STD_LOGIC;
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m_axis_tlast : OUT STD_LOGIC;
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balance : IN STD_LOGIC_VECTOR(BALANCE_WIDTH - 1 DOWNTO 0)
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);
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END balance_controller;
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ARCHITECTURE Behavioral OF balance_controller IS
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CONSTANT BALANCE_STEPS : INTEGER := (2 ** (BALANCE_WIDTH - 1)) / (2 ** BALANCE_STEP_2) + 1;
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CONSTANT BAL_MID : INTEGER := 2 ** (BALANCE_WIDTH - 1); -- 512 for 10 bit
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CONSTANT BLOCK_SIZE : INTEGER := 2 ** BALANCE_STEP_2;
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CONSTANT DEAD_ZONE : INTEGER := BLOCK_SIZE / 2;
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SIGNAL left_channel : INTEGER RANGE 0 TO BALANCE_STEPS := 0;
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SIGNAL right_channel : INTEGER RANGE 0 TO BALANCE_STEPS := 0;
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SIGNAL m_axis_tvalid_int : STD_LOGIC;
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BEGIN
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-- Assigning the output signals
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m_axis_tvalid <= m_axis_tvalid_int;
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s_axis_tready <= m_axis_tready AND aresetn;
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-- Balance to exp
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PROCESS (aclk)
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BEGIN
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IF rising_edge(aclk) THEN
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IF aresetn = '0' THEN
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left_channel <= 0;
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right_channel <= 0;
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ELSE
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-- Balance left and right channels
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IF unsigned(balance) > (BAL_MID + DEAD_ZONE) THEN
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left_channel <= to_integer((unsigned(balance) - (BAL_MID + DEAD_ZONE)) SRL BALANCE_STEP_2) + 1;
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ELSE
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left_channel <= 0;
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END IF;
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IF unsigned(balance) < (BAL_MID - DEAD_ZONE) THEN
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right_channel <= to_integer(((BAL_MID - DEAD_ZONE) - unsigned(balance)) SRL BALANCE_STEP_2) + 1;
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ELSE
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right_channel <= 0;
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END IF;
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END IF;
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END IF;
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END PROCESS;
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-- Handle AXIS stream
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PROCESS (aclk)
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BEGIN
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IF rising_edge(aclk) THEN
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IF aresetn = '0' THEN
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m_axis_tvalid_int <= '0';
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m_axis_tlast <= '0';
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m_axis_tdata <= (OTHERS => '0');
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ELSE
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-- Default output signals
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m_axis_tlast <= '0';
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-- Clear valid flag when master interface is ready
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IF m_axis_tready = '1' THEN
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m_axis_tvalid_int <= '0';
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END IF;
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-- Handle the data flow
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IF s_axis_tvalid = '1' AND m_axis_tready = '1' THEN
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-- Joystick datasheet: (x-axis) a 0 value corresponds to the axis
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-- being tilted fully to the left and a value of 1023
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-- corresponds fully to the right
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IF s_axis_tlast = '0' THEN -- left
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m_axis_tdata <= STD_LOGIC_VECTOR(shift_right(signed(s_axis_tdata), left_channel));
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ELSE -- right
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m_axis_tdata <= STD_LOGIC_VECTOR(shift_right(signed(s_axis_tdata), right_channel));
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END IF;
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m_axis_tvalid_int <= '1';
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m_axis_tlast <= s_axis_tlast;
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END IF;
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END IF;
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END IF;
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END PROCESS;
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END Behavioral; |